Military Field Programmable Gate Arrays Features ACT 3 Features * Highly Predictable Performance with 100 Percent Automatic Placement and Routing * Device Sizes from 1200 to 10,000 gates (up to 25,000 PLD equivalent gates) * Up to 4, Fast, Low-Skew Clock Networks * Up to 228 User-Programmable I/O Pins * More Than 500 Macro Functions * Replaces up to 250 TTL Packages * Replaces up to 100 20-pin PAL Packages * Up to 1153 Dedicated Flip-Flops * I/O Drive to 10 mA * Devices Available to DESC SMD * CQFP and CPGA Packaging * Nonvolatile, User Programmable * Logic Fully Tested Prior to Shipment * Highest-Performance, Highest-Capacity FPGA Family * System Performance to 60 MHz over Military Temperature * Low-Power 0.8-micron CMOS Technology ACT 2 Features * Best-Value, High-Capacity FPGA Family * System Performance to 40 MHz over Military Temperature * Low-Power 1.0-micron CMOS Technology ACT 1 Features * Lowest-Cost FPGA Family * System Performance to 20 MHz over Military Temperature * Low-Power 1.0-micron CMOS Technology Product Family Profile Family ACT 3 Device ACT 2 ACT 1 A1425A A1460A A14100A A1240A A1280A A1010B A1020B 2500 6250 60 25 6000 15,000 150 60 10,000 25,000 250 100 4000 10,000 100 40 8000 20,000 200 80 1200 3000 30 12 2000 6000 50 20 Logic Modules S-Modules C-Modules 310 160 150 848 432 416 1377 697 680 684 348 336 1232 624 608 295 -- 295 547 -- 547 Flip-Flops (maximum) 435 976 1493 568 998 147 273 User I/Os (maximum) 100 168 228 104 140 57 69 133 132 207 196 257 256 132 -- 176 172 84 -- 84 84 60 MHz 60 MHz 60 MHz 40 MHz 40 MHz 20 MHz 20 MHz Capacity Gate Array Equivalent Gates PLD Equivalent Gates TTL Equivalent Packages (40 gates) 20-Pin PAL Equivalent Packages (100 gates) Packages1 (by pin count) CPGA CQFP Performance System Speed (maximum) Note: 1. See Product Plan on page 1-5 for package availability. Ma y 1 9 9 5 (c) 1995 Actel Corporation 1-1 1 High-Reliability, Low-Risk Solution Actel builds the most reliable field programmable gate arrays (FPGAs) in the industry, with overall antifuse reliability ratings of less than 10 Failures-In-Time (FITs), corresponding to a useful life of more than 40 years. Actel FGPAs have been production proven, with more than five million devices shipped and more than one trillion antifuses manufactured. Actel devices are fully tested prior to shipment, with an outgoing defect level of only 122 ppm. (Further reliability data is available in the "Actel Reliability Report.") 100 Percent Tested Device functionality is fully tested before shipment and during device programming. Routing tracks, logic modules, and programming, debug, and test circuits are 100 percent tested before shipment. Antifuse integrity also is tested before shipment. Programming algorithms are tested when a device is programmed using Actel's Activator(R) 2 or Activator 2S programming stations. Benefits No Cost Risk--Once you have a Designer/Designer AdvantageTM System, Actel's CAE software and programming package, you can produce as many chips as you like for just the cost of the device itself, with no NRE charges to eat up your development budget every time you want to try out a new design. No Time Risk--After entering your design, placement and routing is automatic, and programming the device takes only about 5 to 15 minutes for an average design. You save time in the design entry process by using tools that are familiar to you. The Action Logic System software interfaces with popular CAE packages such as Cadence, Mentor Graphics, OrCAD, and Viewlogic, running on platforms such as HP, Sun, and PC. In addition, synthesis capability is provided with support of synthesis tools from Synopsys, IST, Exemplar, and DATA I/O. No Reliability Risk--The PLICE(R) antifuse is a one-time programmable, nonvolatile connection. Since Actel devices are permanently programmed, no downloading from EPROM or SRAM storage is required. Inadvertent erasure is impossible, and there is no need to reload the program after power disruptions. Both the PLICE antifuses and the base process are radiation tolerant. 1-2 Fabrication using a low-power CMOS process means cooler junction temperatures. Actel's non-PLD architecture delivers lower dynamic operating current. Our reliability tests show a very low failure rate of 66 FITs at 90C junction temperature with no degradation in AC performance. Special stress testing at wafer test eliminates infant mortalities prior to packaging. No Security Risk--Reverse engineering of programmed Actel devices from optical or electrical data is extremely difficult. Programmed antifuses cannot be identified from a photograph or by using a SEM. The antifuse map cannot be deciphered either electrically or by microprobing. Each device has a silicon signature that identifies its origins, down to the wafer lot and fabrication facility. No Testing Risk--Unprogrammed Actel parts are fully tested at the factory. This includes the logic modules, interconnect tracks, and I/Os. AC performance is ensured by special speed path tests, and programming circuitry is verified on test antifuses. During the programming process, an algorithm is run to ensure that all antifuses are correctly programmed. In addition, Actel's Actionprobe(R) diagnostic tools allow 100 percent observability of all internal nodes to check and debug your design. Actel FPGA Description The Actel families of FPGAs offer a variety of packages, speed/performance characteristics, and processing levels for use in all high-reliability and military applications. Devices are implemented in a silicon gate, two-level metal CMOS process, utilizing Actel's PLICE antifuse technology. This unique architecture offers gate array flexibility, high performance, and quick turnaround through user programming. Device utilization is typically 95 percent of available logic modules. Actel devices also provide system designers with on-chip diagnostic probe/debug capability, allowing the user to observe 100 percent of the nodes within the design, even while the device is operating in-system. All Actel devices include on-chip clock drivers and a hard-wired distribution network. User-definable I/Os are capable of driving at both TTL and CMOS drive levels. Available packages for the military are the Ceramic Quad Flat Pack (CQFP) and the Ceramic Pin Grid Array (CPGA). See Product Plan on page 2-293 for details. Mi l i ta ry F i e l d P ro g ra m m a b l e G ate Arrays All Actel FPGAs are supported by the Actel Designer Series, which offers automatic or user-definable pin assignment, validation of electrical and design rules, automatic placement and routing, timing analysis, user programming, and debug/diagnostic probe capabilities. The Designer Series fully supports schematic capture and backannotated simulation through design kits for Cadence, Mentor Graphics, OrCAD, and Viewlogic. Synthesis is supported with kits for use with synthesis tools from Synopsys, IST, Exemplar, and DATA I/O. ACT 2 Description Also available is an FPGA fitter (ACTmap) that provides logic synthesis and optimization from PAL language or VHDL description inputs. An FPGA macro generator (ACTgen) is provided, allowing the user easily to create higher-level functions such as counters and adders. Finally, ChipEdit is a graphical/visual design tool that allows the user to modify the automatic place and route results. The ACT 1 family is the first Actel FPGA family and the first antifuse-based FPGA. This family offers the lowest-cost logic integration, with devices ranging from 1,200 to 2,000 gates, with system performance to 20 MHz over the military temperature range. The devices have one routed array clock distribution network. ACT 1 devices are manufactured using 1.0 micron CMOS technology. The ACT 2 family is the second-generation Actel FPGA family. This family offers the best-value, high-capacity devices, ranging from 4,000 to 8,000 gates, with system performance to 40 MHz over the military temperature range. The devices have two routed array clock distribution networks. ACT 2 devices are manufactured using 1.0 micron CMOS technology. ACT 1 Description 1 ACT 3 Description The ACT 3 family is the third-generation Actel FPGA family. This family offers the highest-performance and highest-capacity devices, ranging from 2,500 to 10,000 gates, with system performance to 60 MHz over the military temperature range. The devices have four clock distribution networks, including dedicated array and I/O clocks. In addition, the ACT 3 family offers the highest I/O-to-gate ratio available. ACT 3 devices are manufactured using 0.8 micron CMOS technology. 1-3 Military Device Ordering Information A14100 A - 1 CQ 256 B Application (Temperature Range) C = Commercial (0 to +70C) M = Military (-55 to +125C) B = MIL-STD-883 Class B E = Extended Flow (Space Level) Package Lead Count Package Type CQ = Ceramic Quad Flatpack (CQFP) PG = Ceramic Pin Grid Array (CPGA) Speed Grade Std = Standard Speed -1 = Approximately 15% faster than Standard Device Revision Part Number A1010 A1020 A1240 A1280 A1425 A1460 A14100 = = = = = = = 1200 Gates--ACT 1 2000 Gates--ACT 1 4000 Gates--ACT 2 8000 Gates--ACT 2 2500 Gates--ACT 3 6000 Gates--ACT 3 10,000 Gates--ACT 3 DESC SMD/Actel Part Number Cross-Reference Actel Part Number DESC SMD DESC SMD (Gold Leads) (Gold Leads) (Solder Dipped) A1010B-PG84B 5962-9096403MXC 5962-9096403MXA A1010B-1PG84B 5962-9096404MXC 5962-9096404MXA A1020B-PG84B 5962-9096503MUC 5962-9096503MUA A1020B-1PG84B 5962-9096504MUC 5962-9096504MUA A1020B-CQ84B 5962-9096503MTC 5962-9096503MTA A1020B-1CQ84B 5962-9096504MTC 5962-9096504MTA A1240A-PG132B 5962-9322101MXC 5962-9322101MXA A1240A-1PG132B 5962-9322102MXC 5962-9322102MXA A1280A-PG176B 5962-9215601MXC 5962-9215601MXA A1280A-1PG176B 5962-9215602MXC 5962-9215602MXA A1280A-CQ172B 5962-9215601MYC 5962-9215601MYA A1280A-1CQ172B 5962-9215602MYC 5962-9215602MYA A1425A TBD TBD A1460A TBD TBD A14100A TBD TBD 1-4 Mi l i ta ry F i e l d P ro g ra m m a b l e G ate Arrays Product Plan Speed Grade ACT 3 Family Application Std -1 C M B E 132-pin Ceramic Quad Flatpack (CQFP) -- 133-pin Ceramic Pin Grid Array (CPGA) -- 196-pin Ceramic Quad Flatpack (CQFP) P P P -- 207-pin Ceramic Pin Grid Array (CPGA) P P P -- 256-pin Ceramic Quad Flatpack (CQFP) P P P -- 257-pin Ceramic Pin Grid Array (CPGA) P P P -- A1425A Device A1460A Device 1 A14100A Device Speed Grade ACT 2 Family Application Std -1 C M B E -- 172-pin Ceramic Quad Flatpack (CQFP) 176-pin Ceramic Pin Grid Array (CPGA) A1240A Device 132-pin Ceramic Pin Grid Array (CPGA) A1280A Device Speed Grade ACT 1 Family Application Std -1 C M B E -- 84-pin Ceramic Quad Flatpack (CQFP) 84-pin Ceramic Pin Grid Array (CPGA) A1010B Device 84-pin Ceramic Pin Grid Array (CPGA) A1020B Device Applications: C M B E = = = = Commercial Military MIL-STD-883 Extended Flow Availability: = Available Now * Speed Grade: -1 = Approx. 15% faster than Standard P = Planned -- = Not Planned 1-5 ACT 3 Device Resources User I/Os FPGA Device Type Logic Modules Gate Array Equivalent Gates CQFP CPGA 132-pin 196-pin 256-pin 133-pin 207-pin 257-pin A1425A 310 2500 100 -- -- 100 -- -- A1460A 848 6000 -- 168 -- -- 168 -- A14100A 1377 10,000 -- -- 228 -- -- 228 ACT 2 Device Resources User I/Os FPGA Device Type Logic Modules Gate Array Equivalent Gates CQFP CPGA 172-pin 132-pin 176-pin A1240A 684 4000 -- 104 -- A1280A 1232 8000 140 -- 140 ACT 1 Device Resources User I/Os FPGA Device Type Gate Array Equivalent Gates CQFP CPGA Logic Modules 84-pin 84-pin A1010B 295 1200 -- 57 A1020B 547 2000 69 69 1-6 Mi l i ta ry F i e l d P ro g ra m m a b l e G ate Arrays Pin Description CLK Clock (Input) ACT 1 only. TTL Clock input for global clock distribution network. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. CLKA Clock A (Input) ACT 2 and ACT 3 only. TTL Clock input for global clock distribution networks. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. CLKB Clock B (Input) ACT 2 and ACT 3 only. TTL Clock input for global clock distribution networks. The Clock input is buffered prior to clocking the logic modules. This pin can also be used as an I/O. DCLK Diagnostic Clock (Input) TTL Clock input for diagnostic probe and device programming. DCLK is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. GND Ground LOW supply voltage. HCLK Dedicated (Hard-wired) Array Clock (Input) ACT 3 only. TTL Clock input for sequential modules. This input is directly wired to each S-module and offers clock speeds independent of the number of S-modules being driven. This pin can also be used as an I/O. I/O Input/Output (Input, Output) I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output levels are compatible with standard TTL and CMOS specifications. Unused I/O pins are automatically driven LOW. IOCLK Dedicated (Hard-wired) I/O Clock (Input) ACT 3 only. TTL Clock input for I/O modules. This input is directly wired to each I/O module and offers clock speeds independent of the number of I/O modules being driven. This pin can also be used as an I/O. IOPCL Dedicated (Hard-wired) I/O Preset/Clear (Input) ACT 3 only. TTL input for I/O preset or clear. This global input is directly wired to the preset and clear inputs of all I/O registers. This pin functions as an I/O when no I/O preset or clear macros are used. MODE Mode (Input) The MODE pin controls the use of diagnostic pins (DCLK, PRA, PRB, SDI). When the MODE pin is HIGH, the special functions are active. When the MODE pin is LOW, the pins function as I/Os. NC No Connection This pin is not connected to circuitry within the device. PRA Probe A (Output) The Probe A pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe B pin to allow real-time diagnostic output of any signal path within the device. The Probe A pin can be used as a user-defined I/O when debugging has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. PRA is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. PRB Probe B (Output) The Probe B pin is used to output data from any user-defined design node within the device. This independent diagnostic pin can be used in conjunction with the Probe A pin to allow real-time diagnostic output of any signal path within the device. The Probe B pin can be used as a user-defined I/O when debugging has been completed. The pin's probe capabilities can be permanently disabled to protect programmed design confidentiality. PRB is accessible when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. SDI Serial Data Input (Input) Serial data input for diagnostic probe and device programming. SDI is active when the MODE pin is HIGH. This pin functions as an I/O when the MODE pin is LOW. V CC 5V Supply Voltage HIGH supply voltage. V KS Programming Voltage ACT 2 and ACT 3 only. Supply voltage used for device programming. This pin must be connected to GND during normal operation. V PP Programming Voltage Supply voltage used for device programming. This pin must be connected to VCC during normal operation. V SV Programming Voltage ACT 2 and ACT 3 only. Supply voltage used for device programming. This pin must be connected to VCC during normal operation. 1-7 1 Actel Military Product Flow Step 833--Class B 833 Method Screen 833--Class B Requirement Military Datasheet Requirement 1.0 Internal Visual 2010, Test Condition B 100% 100% 2.0 Temperature Cycling 1010, Test Condition C 100% 100% 3.0 Constant Acceleration 2001, Test Condition E (min), Y1, Orientation Only 100% 100% 4.0 Seal a. Fine b. Gross 1014 100% 100% 100% 100% 5.0 Visual Inspection 2009 100% 100% 6.0 Pre-burn-in Electrical Parameters In accordance with Actel applicable device specification 100% N/A 7.0 Burn-in Test 1015 Condition D 160 hours @ 125C Min. 100% N/A 8.0 Interim (Post-burn-in) Electrical Parameters In accordance with Actel applicable device specification 100% 100% (as final test) 9.0 Percent Defective Allowable 5% All Lots N/A 10.0 Final Electrical Test In accordance with Actel applicable device specification a. Static Tests (1) 25C (Subgroup 1, Table I, 5005) (2) -55C and +125C (Subgroups 2, 3, Table I, 5005) 100% 100% b. Dynamic and Functional Tests (1) 25C (Subgroup 7, Table I, 5005) (2) -55C and +125C (Subgroups 8A and 8B, Table I, 5005) 100% 100% c. Switching Tests at 25C (Subgroup 9, Table I, 5005) 100% 100% 11.0 Qualification or Quality Confirmation Inspection Test Sample Selection (Group A) 5005 All Lots N/A 12.0 External Visual 2009 100% Actel specification 1-8 Mi l i ta ry F i e l d P ro g ra m m a b l e G ate Arrays Actel Extended Flow 1, 2 Screen Method Requirement 1. Wafer Lot Acceptance3 5007 with step coverage waiver All Lots 2. Destructive In-Line Bond Pull4 2011, condition D Sample 3. Internal Visual 2010, condition A 100% 4. Serialization 5. Temperature Cycling 1010, condition C 100% 6. Constant Acceleration 2001, condition E (min), Y1 orientation only 100% 7. Visual Inspection 2009 100% 8. Particle Impact Noise Detection 2020, condition A 100% 100% 9. Radiographic 2012 100% 10. Pre-burn-in Test In accordance with Actel applicable device specification 100% 11. Burn-in Test 1015, condition D, 240 hours @ 125C minimum 100% 12. Interim (Post-burn-in) Electrical Parameters In accordance with Actel applicable device specification 100% 13. Reverse Bias Burn-in 1010, condition C, 72 hours @ 150C minimum 100% 14. Interim (Post-burn-in) Electrical Parameters In accordance with Actel applicable device specification 100% 15. Percent Defective Allowable (PDA) Calculation 5%, 3% functional parameters @ 25C Final Electrical Test In accordance with Actel applicable device specification 16. a. Static Tests (1) 25C (Subgroup 1, Table1) (2) -55C and +125C (Subgroups 2, 3, Table 1) All Lots 100% 100% 5005 5005 b. Dynamic and Functional Tests 5005 (1) 25C (Subgroup 7, Table 15) 5005 (2) -55C and +125C (Subgroups 5 and 6, 8a and b, Table 1) 17. 1 100% c. Switching Tests at 25C (Subgroup 9, Table I, 5005) 5005 Seal 1014 100% 100% a.Fine b.Gross 18. Qualification or Quality Conformance Inspection Test Sample Selection 5005 Group A & Group B 19 External Visual 2009 100% Note: 1. Actel offers the Extended Flow in order to satisfy those customers that require additional screening beyond the requirements of MIL-STD-883, Class B. Actel is compliant to the requirements of MIL-STD-883, Paragraph 1.2.1, and MIL-I-38535, Appendix A. Actel is offering this extended flow incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883 Class S. The exceptions to Method 5004 are shown in notes 2 to 4 below. 2. Method 5004 requires a 100 percent Radiation latch-up testing to Method 1020. Actel will not be performing any radiation testing, and this requirement must be waived in its entirety. Wafer lot acceptance is performed to Method 5007; however the step coverage requirement as specified in Method 2018 must be waived. Method 5004 requires a 100 percent, nondestructive bond pull to Method 2023. Actel substitutes a destructive bond pull to Method 2011, condition D on a sample basis only. 3. 4. 1-9 Absolute Maximum Ratings 1 Recommended Operating Conditions Free air temperature range Symbol Parameter Parameter Supply Voltage2, 3, 4 Limits Units -0.5 to +7.0 V VCC DC VI Input Voltage -0.5 to VCC +0.5 V VO Output Voltage -0.5 to VCC +0.5 V IIO I/O Source Sink Current5 20 mA TSTG Storage Temperature Commercial Military Units Temperature Range1 0 to +70 -55 to +125 C Power Supply Tolerance 5 10 %VCC Note: 1. C -65 to +150 Ambient temperature (TA) is used for commercial and industrial; case temperature (TC) is used for military. Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Device should not be operated outside the recommended operating conditions. 2. 3. 4. 5. VPP = VCC , except during device programming. VSV = VCC , except during device programming. VKS = GND, except during device programming. Device inputs are normally high impedance and draw extremely low current. However, when input voltage is greater than VCC + 0.5 V or less than GND - 0.5 V, the internal protection diode will be forward biased and can draw excessive current. Package Thermal Characteristics The device junction to case thermal characteristic is jc, and the junction to ambient air characteristic is ja. The thermal characteristics for ja are shown with two different air flow rates. Maximum junction temperature is 150C. A sample calculation of the absolute maximum power dissipation allowed for a CPGA 176-pin package at military temperature is as follows: Max. junction temp. (C) - Max. military temp. 150C - 125C ------------------------------------------------------------------------------------------------------------------ = ------------------------------------ = 1.1 W ja (C/W) 23C/W Pin Count ja Still Air ja 300 ft/min Units Ceramic Pin Grid Array 84 132 133 176 207 257 33 26 37 23 22 21 20 16 24 12 14 13 C/W C/W C/W C/W C/W C/W Ceramic Quad Flatpack 84 132 172 196 256 40 55 25 36 30 25 30 15 24 18 C/W C/W C/W C/W C/W Package Type 1-10 Mi l i ta ry F i e l d P ro g ra m m a b l e Gate Arrays Electrical Specifications Commercial Symbol Parameter Units Min. VOH1, 2 HIGH Level Output Max. IOH = -6 mA (CMOS) Max. 3.7 V 3.84 V LOW Level Output IOL = +6 mA (CMOS) VIH HIGH Level Input TTL Inputs 2.0 VCC + 0.3 VIL LOW Level Input TTL Inputs -0.3 IIN Input Leakage VI = VCC or GND IOZ 3-state Output Leakage VO = VCC or GND CIO I/O Capacitance3, 4 ICC(S) Standby VCC Supply Current Dynamic VCC Supply Current Min. IOH = -4 mA (CMOS) VOL1, 2 ICC(D) Military Test Condition 0.33 0.4 V 2.0 VCC + 0.3 V 0.8 -0.3 0.8 V -10 +10 -10 +10 A -10 +10 -10 +10 A 10 10 pF IO = 0 mA 2 20 mA ACT 1 3 20 mA ACT 2/3 2 20 mA VI = VCC or GND, See "Power Dissipation" Section Notes: 1. Actel devices can drive and receive either CMOS or TTL signal levels. No assignment of I/Os as TTL or CMOS is required. 2. 3. 4. Tested one output at a time, VCC = min. Not tested; for information only. VOUT = 0V, f = 1 MHz General Power Equation P = [ICCstandby + ICCactive] * VCC + IOL * VOL * N + IOH * (VCC - VOH) * M Where: ICCstandby is the current flowing when no inputs or outputs are changing. ICCactive is the current flowing due to CMOS switching. IOL, IOH are TTL sink/source currents. VOL, VOH are TTL level output voltages. N equals the number of outputs driving TTL loads to VOL. M equals the number of outputs driving TTL loads to VOH. An accurate determination of N and M is problematical because their values depend on the family type, on design details, and on the system I/O. The power can be divided into two components--static and active. Static Power Component Actel FPGAs have small static power components that result in power dissipation lower than that of PALs or PLDs. By integrating multiple PALs or PLDs into one FPGA, an even greater reduction in board-level power dissipation can be achieved. The power due to standby current is typically a small component of the overall power. Standby power is calculated below for commercial, worst-case conditions. Family ICC VCC Power ACT 1 ACT 2 ACT 3 3 mA 2 mA 2 mA 5.25 V 5.25 V 5.25 V 15.8 mW 10.5 mW 10.5 mW The static power dissipated by TTL loads depends on the number of outputs driving high or low and the DC load current. Again, this value is typically small. For instance, a 32-bit bus sinking 4 mA at 0.33 V will generate 42 mW with all outputs driving low, and 140 mW with all outputs driving high. Active Power Component Power dissipation in CMOS devices is usually dominated by the active (dynamic) power dissipation. This component is frequency dependent, a function of the logic and the external I/O. Active power dissipation results from charging internal chip capacitances of the interconnect, unprogrammed antifuses, module inputs, and module outputs, plus external capacitance due to PC board traces and load device inputs. An additional component of the active power dissipation is the totem-pole current in CMOS transistor pairs. The net effect can be associated 1-11 1 with an equivalent capacitance that can be combined with frequency and voltage to represent active power dissipation. Equivalent Capacitance The power dissipated by a CMOS circuit can be expressed by the equation 1 Power (uW) = CEQ * VCC2 * F (1) Where: CEQ is the equivalent capacitance expressed in pF. VCC is the power supply in volts. F is the switching frequency in MHz. Equivalent capacitance is calculated by measuring ICCactive at a specified frequency and voltage for each circuit component of interest. Measurements are made over a range of frequencies at a fixed value of VCC. Equivalent capacitance is frequency independent so that the results can be used over a wide range of operating conditions. Equivalent capacitance values are shown below. fq2)routed_Clk2 + (r2 * fq2)routed_Clk2 + 0.5 * (s1 * CEQCD * fs1)dedicated_Clk + (s2 * CEQCI * fs2)IO_Clk] Where: m = Number of logic modules switching at fm n = Number of input buffers switching at fn p = Number of output buffers switching at fp q1 = Number of clock loads on the first routed array clock (all families) q2 = Number of clock loads on the second routed array clock (ACT 2, 3 only) r1 = Fixed capacitance due to first routed array clock (all families) r2 = Fixed capacitance due to second routed array clock (ACT 2, 3 only) s1 = Fixed number of clock loads on the dedicated array clock (ACT 3 only) s2 = Fixed number of clock loads on the dedicated I/O clock (ACT 3 only) CEQ Values for Actel FPGAs ACT 1 ACT 2 ACT 3 (2) CEQM = Equivalent capacitance of logic modules in pF 3.7 5.8 6.7 CEQI = Equivalent capacitance of input buffers in pF Input Buffers (CEQI) 22.1 12.9 7.2 CEQO = Equivalent capacitance of output buffers in pF Output Buffers (CEQO) 31.2 23.8 10.4 Routed Array Clock Buffer Loads (CEQCR) CEQCR = Equivalent capacitance of routed array clock in pF 4.6 3.9 1.6 Dedicated Clock Buffer Loads (CEQCD) CEQCD = Equivalent capacitance of dedicated array clock in pF n/a n/a 0.7 I/O Clock Buffer Loads (CEQCI) n/a n/a 0.9 CEQCI = Equivalent capacitance of dedicated I/O clock in pF Modules (CEQM) To calculate the active power dissipated from the complete design, the switching frequency of each part of the logic must be known. Equation 2 shows a piecewise linear summation over all components, it applies to all ACT 1, ACT 2, and ACT 3 devices. Since the ACT 1 family has only one routed array clock, the terms labeled routed_Clk2, dedicated_Clk, and IO_Clk do not apply. Similarly, the ACT 2 family has two routed array clocks, and the dedicated_Clk and IO_Clk terms do not apply. For ACT 3 devices, all terms will apply. Power = VCC2 * [(m * CEQM* fm)modules + (n * CEQI* fn)inputs + (p * (CEQO+ CL) * fp)outputs + 0.5 * (q1 * CEQCR * fq1)routed_Clk1 + (r1 * fq1)routed_Clk1 + 0.5 * (q2 * CEQCR * 1-12 CL = Output lead capacitance in pF fm = Average logic module switching rate in MHz fn = Average input buffer switching rate in MHz fp = Average output buffer switching rate in MHz fq1 = Average first routed array clock rate in MHz (all families) fq2 = Average second routed array clock rate in MHz (ACT 2, 3 only) fs1 = Average dedicated array clock rate in MHz (ACT 3 only) fs2 = Average dedicated I/O clock rate in MHz (ACT 3 only) Mi l i ta ry F i e l d P ro g ra m m a b l e G ate Arrays Fixed Clock Loads (s 1 /s 2 --ACT 3 Only) Fixed Capacitance Values for Actel FPGAs (pF) r1 routed_Clk1 r2 routed_Clk2 A1010B 41 n/a A1020B 69 n/a A1240A 134 134 A1280A 168 168 A1425A 75 75 A1460A 165 165 A14100A 195 195 Device Type s1 Clock Loads on Dedicated Array Clock s2 Clock Loads on Dedicated I/O Clock A1425A 160 100 A1460A 432 168 A14100A 697 228 Device Type Determining Average Switching Frequency To determine the switching frequency for a design, you must have a detailed understanding of the data values input to the circuit. The guidelines in the table below are meant to represent worst-case scenarios so that they can be generally used to predict the upper limits of power dissipation. Type ACT 1 ACT 2 ACT 3 Logic modules (m) 90% of modules 80% of modules 80% of modules Input switching (n) # inputs/4 # inputs/4 # inputs/4 Outputs switching (p) #outputs/4 #outputs/4 #outputs/4 First routed array clock loads (q1) 40% of modules 40% of sequential modules 40% of sequential modules Second routed array clock loads (q2) n/a 40% of sequential modules 40% of sequential modules Load capacitance (CL) 35 pF 35 pF 35 pF Average logic module switching rate (fm) F/10 F/10 F/10 Average input switching rate (fn) F/5 F/5 F/5 Average output switching rate (fp) F/10 F/10 F/10 Average first routed array clock rate (fq1) F F F/2 Average second routed array clock rate (fq2) n/a F/2 F/2 Average dedicated array clock rate (fs1) n/a n/a F Average dedicated I/O clock rate (fs2) n/a n/a F 1-13 1 Parameter Measurement Output Buffer Delays E D VCC In 50% PAD VOL TRIBUFF PAD To AC test loads (shown below) VCC GND 50% VOH E 1.5 V 1.5 V 50% VCC 50% VCC GND 1.5 V PAD E PAD GND 10% VOL tDHL tDLH tENZL 90% 1.5 V tENHZ tENZH tENLZ GND 50% VOH 50% AC Test Load Load 1 (Used to measure propagation delay) Load 2 (Used to measure rising/falling edges) VCC GND To the output under test 50 pF R to VCC for tPLZ/tPZL R to GND for tPHZ/tPZH R = 1 k To the output under test 50 pF Input Buffer Delays Combinatorial Macro Delays PAD S A B Y INBUF Y VCC S, A, or B 50% 50% VCC Y GND 50% 3V PAD 1.5 V 1.5 V VCC Y GND 50% 50% tINYH 1-14 0V tINYL tPLH GND 50% tPHL VCC Y 50% tPHL GND tPLH 50% Mi l i ta ry F i e l d P ro g ra m m a b l e G ate Arrays Sequential Timing Characteristics Flip-Flops and Latches (ACT 1 and ACT 2) D E CLK Y PRE CLR (Positive edge triggered) 1 tHD D1 tSUD tA tWCLKA G, CLK tSUENA tHENA E tCO Q tRS PRE, CLR tWASYN Note: 1. D represents all data functions involving A, B, and S for multiplexed flip-flops. 1-15 Sequential Ti ming Characteristics Flip-Flops and Latches (ACT 3) D E CLK Y CLR (Positive edge triggered) tHD D1 tSUD tA tWCLKA G, CLK tSUENA tHENA E tCO Q tCLR CLR tWASYN Note: 1. 1-16 D represents all data functions involving A, B, and S for multiplexed flip-flops. Mi l i ta ry F i e l d P ro g ra m m a b l e G ate Arrays Sequential Timing Characteristics (continued) Input Buffer Latches (ACT 2 only) PAD IBDL G 1 PAD CLK CLKBUF PAD tINH G tINSU tHEXT CLK tSUEXT Output Buffer Latches (ACT 2 only) D PAD OBDLHS G D tOUTSU G tOUTH 1-17