LTC1096LCS8#PBF - Linear Technology

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

TYPICAL APPLICATION

DESCRIPTION

Micropower Sampling

8-Bit Serial I/O A/D Converters

The LTC

1096/LTC1096L/LTC1098/LTC1098L are

micropower, 8-bit A/D converters that draw only 80μA of

supply current when converting. They automatically power

down to 1nA typical supply current whenever they are not

performing conversions. They are packaged in 8-pin SO

packages and have both 3V (L) and 5V versions. These

8-bit, switched-capacitor, successive approximation ADCs

include sample-and-hold. The LTC1096/LTC1096L have a

single differential analog input. The LTC1098/LTC1098L

offer a software selectable 2-channel MUX.

On-chip serial ports allow efﬁ cient data transfer to a wide

range of microprocessors and microcontrollers over three

wires. This, coupled with micropower consumption, makes

remote location possible and facilitates transmitting data

through isolation barriers.

These circuits can be used in ratiometric applications or

with an external reference. The high impedance analog

inputs and the ability to operate with reduced spans (be-

low 1V full scale) allow direct connection to sensors and

transducers in many applications, eliminating the need

for gain stages.

L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.

All other trademarks are the property of their respective owners.

FEATURES

APPLICATIONS

n 80μA Maximum Supply Current

n 1nA Typical Supply Current in Shutdown

n 5V Operation (LTC1096/LTC1098)

n 3V Operation (LTC1096L/LTC1098L)(2.65V Min)

n Sample-and-Hold

n 16μs Conversion Time

n 33kHz Sample Rate

n ±0.5LSB Total Unadjusted Error Over Temp

n Direct 3-Wire Interface to Most MPU Serial Ports and

All MPU Parallel I/O Ports

n 8-Pin SO Plastic Package

n Battery-Operated Systems

n Remote Data Acquisition

n Battery Monitoring

n Battery Gas Gauges

n Temperature Measurement

n Isolated Data Acquisition

Supply Current vs Sample Rate10μW, S8 Package, 8-Bit A/D

Samples at 200Hz and Runs Off a 5V Battery

5V1μF

ANALOG INPUT

0V TO 5V RANGE –IN

GND

VCC

CLK

DOUT

VREF

LTC1096

MPU

(e.g., 8051)

P1.4

P1.3

P1.2

+IN

10968 TA01

CS/

SHUTDOWN

SAMPLE FREQUENCY, fSMPL (kHz)

0.1

SUPPLY CURRENT, ICC (μA)

100

1000

1 10 100

10968 TA02

TA = 25°C

VCC = VREF = 5V

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

ABSOLUTE MAXIMUM RATINGS

(Notes 1 and 2)

LTC1096 LTC1098

TOP VIEW

+IN

–IN

GND

VCC

CLK

DOUT

VREF

N8 PACKAGE

8-LEAD PLASTIC DIP

CS/

SHUTDOWN

S8 PACKAGE

8-LEAD PLASTIC SOIC

TJMAX = 150°C, θJA = 130°C/W (N8)

TJMAX = 150°C, θJA = 175°C/W (S8)

TOP VIEW

CH0

CH1

GND

VCC(VREF)

CLK

DOUT

DIN

N8 PACKAGE

8-LEAD PLASTIC DIP

CS/

SHUTDOWN

S8 PACKAGE

8-LEAD PLASTIC SOIC

TJMAX = 150°C, θJA = 130°C/W (N8)

TJMAX = 150°C, θJA = 175°C/W (S8)

PIN CONFIGURATION

ORDER INFORMATION

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC1096ACN8#PBF LTC1096ACN8#TRPBF LTC1096ACN8 8-Lead Plastic DIP 0°C to 70°C

LTC1096ACS8#PBF LTC1096ACS8#TRPBF 1096A 8-Lead Plastic SOIC 0°C to 70°C

LTC1096AIN8#PBF LTC1096AIN8#TRPBF LTC1096AIN8 8-Lead Plastic DIP –40°C to 85°C

LTC1096AIS8#PBF LTC1096AIS8#TRPBF 1096AI 8-Lead Plastic SOIC –40°C to 85°C

LTC1096CN8#PBF LTC1096CN8#TRPBF LTC1096CN8 8-Lead Plastic DIP 0°C to 70°C

LTC1096CS8#PBF LTC1096CS8#TRPBF 1096 8-Lead Plastic SOIC 0°C to 70°C

LTC1096IN8#PBF LTC1096IN8#TRPBF LTC1096IN8 8-Lead Plastic DIP –40°C to 85°C

LTC1096IS8#PBF LTC1096IS8#TRPBF 1096I 8-Lead Plastic SOIC –40°C to 85°C

LTC1096LCS8#PBF LTC1096LCS8#TRPBF 1096L 8-Lead Plastic SOIC 0°C to 70°C

LTC1096LIS8#PBF LTC1096LIS8#TRPBF 1096LI 8-Lead Plastic SOIC –40°C to 85°C

LTC1098ACN8#PBF LTC1098ACN8#TRPBF LTC1098ACN8 8-Lead Plastic DIP 0°C to 70°C

LTC1098ACS8#PBF LTC1098ACS8#TRPBF 1098A 8-Lead Plastic SOIC 0°C to 70°C

LTC1098CN8#PBF LTC1098CN8#TRPBF LTC1098CN8 8-Lead Plastic DIP 0°C to 70°C

LTC1098CS8#PBF LTC1098CS8#TRPBF 1098 8-Lead Plastic SOIC 0°C to 70°C

LTC1098IN8#PBF LTC1098IN8#TRPBF LTC1098IN8 8-Lead Plastic DIP –40°C to 85°C

LTC1098IS8#PBF LTC1098IS8#TRPBF 1098I 8-Lead Plastic SOIC –40°C to 85°C

LTC1098LCS8#PBF LTC1098LCS8#TRPBF 1098L 8-Lead Plastic SOIC 0°C to 70°C

LTC1098LIS8#PBF LTC1098LIS8#TRPBF 1098LI 8-Lead Plastic SOIC –40°C to 85°C

Operating Temperature

LTC1096AC/LTC1096C/LTC1096LC/

LTC1098AC/LTC1098C/LTC1098LC .......... 0°C to 70°C

LTC1096AI/LTC1096I/LTC1096LI/

LTC1098AI/LTC1098I/LTC1098LI ......... –40°C to 85°C

Lead Temperature (Soldering, 10 sec.) ................. 300°C

Supply Voltage (VCC) to GND ...................................12V

Voltage

Analog and Reference ................ –0.3V to VCC + 0.3V

Digital Inputs ........................................ –0.3V to 12V

Digital Outputs ........................... –0.3V to VCC + 0.3V

Power Dissipation ...............................................500mW

Storage Temperature Range ................... –65°C to 150°C

(Note 3)

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

RECOMMENDED OPERATING CONDITIONS

LTC1096/LTC1098

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VCC Supply Voltage LTC1096

LTC1098

3.0

VCC = 5V Operation

fCLK Clock Frequency VCC = 5V 25 500 kHz

tCYC Total Cycle Time LTC1096, fCLK = 500kHz

LTC1098, fCLK = 500kHz

μs

thDI Hold Time, DIN After CLK↑VCC = 5V 150 ns

tsuCS Setup Time CS↓ Before First CLK↑ (See Operating Sequence) VCC = 5V, LTC1096

VCC = 5V, LTC1098

500

tWAKEUP Wake-Up Time CS↓ Before First CLK↓ After First CLK↑

(See Figure 1 LTC1096 Operating Sequence)

VCC = 5V, LTC1096 10 μs

Wake-Up Time CS↓ Before MSBF Bit CLK↓

(See Figure 2 LTC1098 Operating Sequence)

VCC = 5V, LTC1098 10 μs

tsuDI Setup Time, DIN Stable Before CLK↑VCC = 5V 400 ns

tWHCLK CLK High Time VCC = 5V 0.8 μs

tWLCLK CLK Low Time VCC = 5V 0.8 μs

ORDER INFORMATION

LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC1096ACN8 LTC1096ACN8#TR LTC1096ACN8 8-Lead Plastic DIP 0°C to 70°C

LTC1096ACS8 LTC1096ACS8#TR 1096A 8-Lead Plastic SOIC 0°C to 70°C

LTC1096AIN8 LTC1096AIN8#TR LTC1096AIN8 8-Lead Plastic DIP –40°C to 85°C

LTC1096AIS8 LTC1096AIS8#TR 1096AI 8-Lead Plastic SOIC –40°C to 85°C

LTC1096CN8 LTC1096CN8#TR LTC1096CN8 8-Lead Plastic DIP 0°C to 70°C

LTC1096CS8 LTC1096CS8#TR 1096 8-Lead Plastic SOIC 0°C to 70°C

LTC1096IN8 LTC1096IN8#TR LTC1096IN8 8-Lead Plastic DIP –40°C to 85°C

LTC1096IS8 LTC1096IS8#TR 1096I 8-Lead Plastic SOIC –40°C to 85°C

LTC1096LCS8 LTC1096LCS8#TR 1096L 8-Lead Plastic SOIC 0°C to 70°C

LTC1096LIS8 LTC1096LIS8#TR 1096LI 8-Lead Plastic SOIC –40°C to 85°C

LTC1098ACN8 LTC1098ACN8#TR LTC1098ACN8 8-Lead Plastic DIP 0°C to 70°C

LTC1098ACS8 LTC1098ACS8#TR 1098A 8-Lead Plastic SOIC 0°C to 70°C

LTC1098CN8 LTC1098CN8#TR LTC1098CN8 8-Lead Plastic DIP 0°C to 70°C

LTC1098CS8 LTC1098CS8#TR 1098 8-Lead Plastic SOIC 0°C to 70°C

LTC1098IN8 LTC1098IN8#TR LTC1098IN8 8-Lead Plastic DIP –40°C to 85°C

LTC1098IS8 LTC1098IS8#TR 1098I 8-Lead Plastic SOIC –40°C to 85°C

LTC1098LCS8 LTC1098LCS8#TR 1098L 8-Lead Plastic SOIC 0°C to 70°C

LTC1098LIS8 LTC1098LIS8#TR 1098LI 8-Lead Plastic SOIC –40°C to 85°C

Consult LTC Marketing for parts speciﬁ ed with wider operating temperature ranges. *The temperature grade is identiﬁ ed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

This product is only offered in trays. For more information go to: http://www.linear.com/packaging/

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

tWHCS CS High Time Between Data Transfer Cycles VCC = 5V 1 μs

tWLCS CS Low Time During Data Transfer LTC1096, fCLK = 500kHz

LTC1098, fCLK = 500kHz

μs

VCC = 3V Operation

fCLK Clock Frequency VCC = 3V 25 250 kHz

tCYC Total Cycle Time LTC1096, fCLK = 250kHz

LTC1098, fCLK = 250kHz

μs

thDI Hold Time, DIN After CLK↑VCC = 3V 450 ns

tsuCS Setup Time CS↓ Before First CLK↑ (See Operating Sequence) VCC = 3V, LTC1096

VCC = 3V, LTC1098

μs

tWAKEUP Wake-Up Time CS↓ Before First CLK↓ After First CLK↑

(See Figure 1 LTC1096 Operating Sequence)

VCC = 3V, LTC1096 10 μs

Wake-Up Time CS↓ Before MSBF Bit CLK↓

(See Figure 2 LTC1098 Operating Sequence)

VCC = 3V, LTC1098 10 μs

tsuDI Setup Time, DIN Stable Before CLK↑VCC = 3V 1 μs

tWHCLK CLK High Time VCC = 3V 1.6 μs

tWLCLK CLK Low Time VCC = 3V 1.6 μs

tWHCS CS High Time Between Data Transfer Cycles VCC = 3V 2 μs

tWLCS CS Low Time During Data Transfer LTC1096, fCLK = 250kHz

LTC1098, fCLK = 250kHz

μs

LTC1096/LTC1098

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VCC Supply Voltage 2.65 4.0 V

fCLK Clock Frequency VCC = 2.65V 25 250 kHz

tCYC Total Cycle Time LTC1096L, fCLK = 250kHz

LTC1098L, fCLK = 250kHz

μs

thDI Hold Time, DIN After CLK↑VCC = 2.65V 450 ns

tsuCS Setup Time CS↓ Before First CLK↑ (See Operating Sequence) VCC = 2.65V, LTC1096L

VCC = 2.65V, LTC1098L

μs

tWAKEUP Wake-Up Time CS↓ Before First CLK↓ After First CLK↑

(See Figure 1 LTC1096L Operating Sequence)

VCC = 2.65V, LTC1096L 10 μs

Wake-Up Time CS↓ Before MSBF Bit CLK↓

(See Figure 2 LTC1098L Operating Sequence)

VCC = 2.65V, LTC1098L 10 μs

tsuDI Setup Time, DIN Stable Before CLK↑VCC = 2.65V 1 μs

tWHCLK CLK High Time VCC = 2.65V 1.6 μs

tWLCLK CLK Low Time VCC = 2.65V 1.6 μs

tWHCS CS High Time Between Data Transfer Cycles VCC = 2.65V 2 μs

tWLCS CS Low Time During Data Transfer LTC1096L, fCLK = 250kHz

LTC1098L, fCLK = 250kHz

μs

LTC1096L/LTC1098L

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

CONVERTER AND MULTIPLEXER CHARACTERISTICS

LTC1096/LTC1098

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C.

VCC = 5V, VREF = 5V, fCLK = 500kHz, unless otherwise noted.

PARAMETER CONDITIONS

LTC1096A/LTC1098A LTC1096/LTC1098

UNITSMIN TYP MAX MIN TYP MAX

Resolution (No Missing Code) l8 8 Bits

Offset Error l±0.5 ±0.5 LSB

Linearity Error (Note 4) l±0.5 ±0.5 LSB

Full Scale Error l±0.5 ±1.0 LSB

Total Unadjusted Error (Note 5) VREF = 5.000V l±0.5 ±1.0 LSB

Analog Input Range (Notes 6, 7) –0.05V to VCC + 0.05V V

REF Input Range (Notes 6, 7) 4.5 ≤ VCC ≤ 6V

6V < VCC ≤ 9V, LTC1096

–0.05V to VCC + 0.05V

–0.05V to 6V

Analog Input Leakage Current (Note 8) l±1.0 ±1.0 μA

LTC1096/LTC1098

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C.

VCC = 3V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.

PARAMETER CONDITIONS

LTC1096A/LTC1098A LTC1096/LTC1098

UNITSMIN TYP MAX MIN TYP MAX

Resolution (No Missing Code) l8 8 Bits

Offset Error l±0.75 ±1.0 LSB

Linearity Error (Notes 4, 9) l±0.5 ±1.0 LSB

Full-Scale Error l±1.0 ±1.0 LSB

Total Unadjusted Error (Notes 5, 9) VREF = 2.500V l±1.0 ±1.5 LSB

Analog Input Range (Notes 6, 7) –0.05V to VCC + 0.05V V

REF Input Range (Notes 6, 7, 9) 3V ≤ VCC ≤ 6V –0.05V to VCC + 0.05V V

Analog Input Leakage Current (Notes 8, 9) l±1.0 ±1.0 μA

LTC1096L/LTC1098L

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C.

VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.

PARAMETER CONDITIONS

LTC1096A/LTC1098A

UNITSMIN TYP MAX

Resolution (No Missing Code) l8 Bits

Offset Error l±1.0 LSB

Linearity Error (Note 4) l±1.0 LSB

Full-Scale Error l±1.0 LSB

Total Unadjusted Error (Note 5) VREF = 2.5V l±1.5 LSB

Analog Input Range (Notes 6, 7) –0.05V to VCC + 0.05V V

REF Input Range (Note 6) 2.65V ≤ VCC ≤ 4.0V –0.05V to VCC + 0.05V V

Analog Input Leakage Current (Note 8) l±1.0 μA

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

DIGITAL AND DC ELECTRICAL CHARACTERISTICS

LTC1096/LTC1098

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C.

VCC = 5V, VREF = 5V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIH High Level Input Voltage VCC = 5.25V l2.0 V

VIL Low Level Input Voltage VCC = 4.75V l0.8 V

IIH High Level Input Current VIN = VCC l2.5 μA

IIL Low Level Input Current VIN = 0V l–2.5 μA

VOH High Level Output Voltage VCC = 4.75V, IO = 10μA

VCC = 4.75V, IO = 360μA

4.5

2.4

4.74

4.72

VOL Low Level Output Voltage VCC = 4.75V, IO = 1.6mA l0.4 V

IOZ Hi-Z Output Leakage CS ≥ VIH l±3.0 μA

ISOURCE Output Source Current VOUT = 0V –25 mA

ISINK Output Sink Current VOUT = VCC 45 mA

IREF Reference Current CS = VCC

tCYC ≥ 200μs, fCLK ≤ 50kHz

tCYC = 29μs, fCLK = 500kHz

0.001

3.500

35.000

2.5

7.5

50.0

μA

ICC Supply Current CS = VCC l0.001 3.0 μA

LTC1096, tCYC ≥ 200μs, fCLK ≤ 50kHz

LTC1096, tCYC = 29μs, fCLK = 500kHz

120

180

μA

LTC1098, tCYC ≥ 200μs, fCLK ≤ 50kHz

LTC1098, tCYC = 29μs, fCLK = 500kHz

155

230

μA

LTC1096/LTC1098

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C.

VCC = 3V, VREF = 2.5V, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIH High Level Input Voltage VCC = 3.6V l1.9 V

VIL Low Level Input Voltage VCC = 3V l0.45 V

IIH High Level Input Current (Note 9) VIN = VCC l2.5 μA

IIL Low Level Input Current (Note 9) VIN = 0V l–2.5 μA

VOH High Level Output Voltage VCC = 3V, IO = 10μA

VCC = 3V, IO = 360μA

2.3

2.1

2.69

2.64

VOL Low Level Output Voltage VCC = 3V, IO = 400μA l0.3 V

IOZ Hi-Z Output Leakage (Note 9) CS ≥ VIH l±3.0 μA

ISOURCE Output Source Current (Note 9) VOUT = 0V –10 mA

ISINK Output Sink Current (Note 9) VOUT = VCC 15 mA

IREF Reference Current (Note 9) CS = VCC

tCYC ≥ 200μs, fCLK ≤ 50kHz

tCYC = 58μs, fCLK = 250kHz

0.001

3.500

35.000

2.5

7.5

50.0

μA

ICC Supply Current (Note 9) CS = VCC l0.001 3.0 μA

LTC1096, tCYC ≥ 200μs, fCLK ≤ 50kHz

LTC1096, tCYC = 58μs, fCLK = 250kHz

120

180

μA

LTC1098, tCYC ≥ 200μs, fCLK ≤ 50kHz

LTC1098, tCYC = 58μs, fCLK = 250kHz

155

230

μA

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

DIGITAL AND DC ELECTRICAL CHARACTERISTICS

LTC1096L/LTC1098L

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C.

VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VIH High Level Input Voltage VCC = 3.6V l1.9 V

VIL Low Level Input Voltage VCC = 2.65V l0.45 V

IIH High Level Input Current VIN = VCC l2.5 μA

IIL Low Level Input Current VIN = 0V l–2.5 μA

VOH High Level Output Voltage VCC = 2.65V, IO = 10μA

VCC = 2.65V, IO = 360μA

2.3

2.1

2.64

2.50

VOL Low Level Output Voltage VCC = 2.65V, IO = 400μA l0.3 V

IOZ Hi-Z Output Leakage CS ≥ High l±3.0 μA

ISOURCE Output Source Current VOUT = 0V –10 mA

ISINK Output Sink Current VOUT = VCC 15 mA

IREF Reference Current CS = VCC

tCYC ≥ 200μs, fCLK ≤ 50kHz

tCYC = 58μs, fCLK = 250kHz

0.001

3.500

35.000

2.5

7.5

50.0

μA

ICC Supply Current CS = VCC l0.001 3.0 μA

LTC1096L, tCYC ≥ 200μs, fCLK ≤ 50kHz

LTC1096L, tCYC = 58μs, fCLK = 250kHz

120

180

μA

LTC1098L, tCYC ≥ 200μs, fCLK ≤ 50kHz

LTC1098L, tCYC = 58μs, fCLK = 250kHz

155

230

μA

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

tSMPL Analog Input Sample Time See Operating Sequence 1.5 CLK Cycles

fSMPL(MAX) Maximum Sampling Frequency l33 kHz

tCONV Conversion Time See Operating Sequence 8 CLK Cycles

tdDO Delay Time, CLK↓ to DOUT Data Valid See Test Circuits l200 450 ns

tdis Delay Time, CS↑ to DOUT Hi-Z See Test Circuits l170 450 ns

ten Delay Time, CLK↓ to DOUT Enable See Test Circuits l60 250 ns

thDO Time Output Data Remains Valid After CLK↓ CLOAD = 100pF 180 ns

tfDOUT Fall Time See Test Circuits l70 250 ns

trDOUT Rise Time See Test Circuits l25 100 ns

CIN Input Capacitance Analog Inputs On Channel

Analog Inputs Off Channel

Digital Input 5 pF

AC CHARACTERISTICS

LTC1096/LTC1098

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C.

VCC = 5V, VREF = 5V, fCLK = 500kHz, unless otherwise noted.

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltage values are with respect to GND.

Note 3: For the 8-lead PDIP, consult the factory.

Note 4: Linearity error is speciﬁ ed between the actual and points of the

A/D transfer curve.

Note 5: Total unadjusted error includes offset, full scale, linearity,

multiplexer and hold step errors.

Note 6: Two on-chip diodes are tied to each reference and analog input

which will conduct for reference or analog input voltages one diode

drop below GND or one diode drop above VCC. This spec allows 50mV

forward bias of either diode. This means that as long as the reference or

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

tSMPL Analog Input Sample Time See Operating Sequence 1.5 CLK Cycles

fSMPL(MAX) Maximum Sampling Frequency l16.5 kHz

tCONV Conversion Time See Operating Sequence 8 CLK Cycles

tdDO Delay Time, CLK↓ to DOUT Data Valid See Test Circuits (Note 9) l500 1000 ns

tdis Delay Time, CS↑ to DOUT Hi-Z See Test Circuits (Note 9) l220 800 ns

ten Delay Time, CLK↓ to DOUT Enable See Test Circuits (Note 9) l160 480 ns

thDO Time Output Data Remains Valid After CLK↓ CLOAD = 100pF 400 ns

tfDOUT Fall Time See Test Circuits (Note 9) l70 250 ns

trDOUT Rise Time See Test Circuits (Note 9) l50 150 ns

CIN Input Capacitance Analog Inputs On Channel

Analog Inputs Off Channel

Digital Input 5 pF

AC CHARACTERISTICS

LTC1096/LTC1098

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C.

VCC = 3V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

tSMPL Analog Input Sample Time See Operating Sequence 1.5 CLK Cycles

fSMPL(MAX) Maximum Sampling Frequency l16.5 kHz

tCONV Conversion Time See Operating Sequence 8 CLK Cycles

tdDO Delay Time, CLK↓ to DOUT Data Valid See Test Circuits l500 1000 ns

tdis Delay Time, CS↑ to DOUT Hi-Z See Test Circuits l220 800 ns

ten Delay Time, CLK↓ to DOUT Enable See Test Circuits l160 480 ns

thDO Time Output Data Remains Valid After CLK↓ CLOAD = 100pF 400 ns

tfDOUT Fall Time See Test Circuits l70 250 ns

trDOUT Rise Time See Test Circuits l50 200 ns

CIN Input Capacitance Analog Inputs On Channel

Analog Inputs Off Channel

Digital Input 5 pF

LTC1096L/LTC1098L

The l denotes the speciﬁ cations which apply over the full operating temperature range, otherwise speciﬁ cations are at TA = 25°C.

VCC = 2.65V, VREF = 2.5V, fCLK = 250kHz, unless otherwise noted.

analog input does not exceed the supply voltage by more than 50mV, the

output code will be correct. To achieve an absolute 0V to 5V input voltage

range will therefore require a minimum supply voltage of 4.950V over

initial tolerance, temperature variations and loading. For 5.5V < VCC ≤ 9V,

reference and analog input range cannot exceed 5.55V. If reference and

analog input range are greater than 5.55V, the output code will not be

guaranteed to be correct.

Note 7: The supply voltage range for the LTC1096L/LTC1098L is from

2.65V to 4V. The supply voltage range for the LTC1096 is from 3V to 9V,

but the supply voltage range for the LTC1098 is only from 3V to 6V.

Note 8: Channel leakage current is measured after the channel selection.

Note 9: These speciﬁ cations are either correlated from 5V speciﬁ cations or

guaranteed by design.

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

TYPICAL PERFORMANCE CHARACTERISTICS

Change in Offset vs

Reference Voltage LTC1096

Change in Offset vs

Supply Voltage

Change in Linearity vs

Reference Voltage LTC1096

Change in Linearity vs

Supply Voltage Change in Gain vs Supply Voltage

Change in Gain vs

Reference Voltage LTC1096

Supply Current vs Clock Rate

for Active and Shutdown Modes

Supply Current vs Supply Voltage

Active and Shutdown Modes

Supply Current vs Sample

Frequency LTC1096

FREQUENCY (kHz)

SUPPLY CURRENT, ICC (μA)

150

200

250

10 100 1000

10968 G01

100

TA = 25°C

CS = 0V

VCC = 9V

VCC = 5V

CS = VCC

0.002

SUPPLY VOLTAGE,VCC (V)

SUPPLY CURRENT, ICC (μA)

100

2459

10968 G02

13 678

TA = 25°C

VREF = 2.5V

“ACTIVE” MODE CS = 0

“SHUTDOWN” MODE CS = VCC

0.001

SAMPLE FREQUENCY, fSMPL (kHz)

0.1

SUPPLY CURRENT, ICC (μA)

100

1000

1 10 100

10968 G03

TA = 25°C

VCC = VREF = 5V

REFERENCE VOLTAGE (V)

MAGNITUDE OF OFFSET CHANGE (LSB = 1/256 s VREF)

0.25

10968 G04

–0.25

–0.50 1235

0.50

TA = 25°C

VCC = 5V

FCLK = 500kHz

SUPPLY VOLTAGE, VCC (V)

MAGNITUDE OF OFFSET CHANGE (LSB)

0.1

0.3

0.5

10968 G05

–0.1

–0.3

–0.5 24610

0.2

0.4

–0.2

–0.4

357

TA = 25°C

VREF = 2.5V

FCLK = 100kHz

REFERENCE VOLTAGE (V)

CHANGE IN LINEARITY (LSB)

0.25

10968 G06

–0.25

–O.50 1235

0.50

TA = 25°C

VCC = 5V

FCLK = 500kHz

SUPPLY VOLTAGE, VCC (V)

CHANGE IN LINEARTY (LSB)

0.1

0.3

0.5

10968 G07

–0.1

–0.3

–0.5 24610

0.2

0.4

–0.2

–0.4

357

TA = 25°C

VREF = 2.5V

FCLK = 100kHz

SUPPLY VOLTAGE, VCC (V)

CHANGE IN GAIN (LSB)

0.1

0.3

0.5

10968 G08

–0.1

–0.3

–0.5 24610

0.2

0.4

–0.2

–0.4

357

TA = 25°C

VREF = 2.5V

FCLK = 100kHz

VOLTAGE REFERENCE (V)

CHANGE IN GAIN (LSB)

0.25

10968 G09

–0.25

–O.50 1235

0.50

TA = 25°C

VCC = 5V

FCLK = 500kHz

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

TYPICAL PERFORMANCE CHARACTERISTICS

Wake-Up Time vs Supply Voltage

Minimum Wake-Up Time

vs Source Resistance

Input Channel Leakage Current

vs Temperature

Minimum Clock Frequency for

0.1LSB Error† vs Temperature ENOBs vs Frequency FFT Plot

Maximum Clock Frequency vs

Source Resistance

Maximum Clock Frequency vs

Supply Voltage

Digital Input Logic Threshold

vs Supply Voltage

* Maximum CLK frequency represents the clock frequency at which a 0.1LSB shift in the error at any code

transition from its 0.75MHz value is ﬁ rst detected.

† As the CLK frequency is decreased from 500kHz, minimum CLK frequency (Δerror ≤ 0.1LSB) represents

the frequency at which a 0.1LSB shift in any code transition from its 500kHz value is ﬁ rst detected.

RSOURCE– (kΩ)

MAXIMUM CLOCK FREQUENCY* (MHz)

0.25

0.50

10 100

10968 G10

0.75

+ INPUT

– INPUT

RSOURCE–

VIN

TA = 25°C

VCC = VREF = 5V

SUPPLY VOLTAGE (V)

MAXIMUM CLOCK FREQUENCY (MHz)

0.25

0.5

0.75

1.0

1.25

1.5

2468

10968 G11

TA = 25°C

VREF = 2.5V

SUPPLY VOLTAGE, VCC (V)

LOGIC THRESH0LD (V)

10968 G12

024610

TA = 25°C

SUPPLY VOLTAGE, VCC (V)

WAKE-UP TIME (μs)

10968 G13

024610

TA = 25°C

VREF = 2.5V

RSOURCE (kΩ)

MINIMUM WAKE-UP TIME (μs)

2.5

5.0

10 100

10968 G14

7.5

TA = 25°C

VREF = 5V

–

VIN

RSOURCE+

TEMPERATURE (°C)

–60

LEAKAGE CURRENT (nA)

100

1000

100

10968 G15

0.1

0.01 –20 20 60 140

–40 0 40 80 120

VREF = 5V

VCC = 5V

ON CHANNEL

OFF CHANNEL

TEMPERATURE (°C)

–60

MINIMUM CLOCK FREQUENCY (kHz)

120

160

200

100

10968 G16

0–20 20 60 140

–40 0 40 80 120

VREF = 5V

VCC = 5V

180

140

100

FREQUENCY (kHz)

ENOBs

10 100

10968 G17

TA = 25°C

VCC = VREF = 5V

fSMPL = 31.25kHz

FREQUENCY (kHz)

–100

AMPLITUDE (dB)

–90

–70

–60

–50

–30

10968 G18

–80

–20

–10

–40

6810 12 14 16

TA = 25°C

VCC = VREF = 5V

fSMPL = 31.25kHz

fIN = 5.8kHz

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

PIN FUNCTIONS

LTC1096/LTC1096L

CS/SHDN (Pin 1): Chip Select Input. A logic low on this

input enables the LTC1096/LTC1096L. A logic high on this

input disables the LTC1096/LTC1096L and disconnects the

power to the LTC1096/LTC1096L.

IN+ (Pin 2): Analog Input. This input must be free of noise

with respect to GND.

IN– (Pin 3): Analog Input. This input must be free of noise

with respect to GND.

GND (Pin 4): Analog Ground. GND should be tied directly

to an analog ground plane.

VREF (Pin 5): Reference Input. The reference input deﬁ nes

the span of the A/D converter and must be kept free of

noise with respect to GND.

DOUT (Pin 6): Digital Data Output. The A/D conversion

result is shifted out of this output.

CLK (Pin 7): Shift Clock. This clock synchronizes the se-

rial data transfer.

VCC (Pin 8): Power Supply Voltage. This pin provides power

to the A/D converter. It must be free of noise and ripple by

bypassing directly to the analog ground plane.

LTC1098/LTC1098L

CS/SHDN (Pin 1): Chip Select Input. A logic low on this

input enables the LTC1098/LTC1098L. A logic high on this

input disables the LTC1098/LTC1098L and disconnects the

power to the LTC1098/LTC1098L.

CH0 (Pin 2): Analog Input. This input must be free of noise

with respect to GND.

CH1 (Pin 3): Analog Input. This input must be free of noise

with respect to GND.

GND (Pin 4): Analog Ground. GND should be tied directly

to an analog ground plane.

DIN (Pin 5): Digital Data Input. The multiplexer address

is shifted into this pin.

DOUT (Pin 6): Digital Data Output. The A/D conversion

result is shifted out of this output.

CLK (Pin 7): Shift Clock. This clock synchronizes the se-

rial data transfer.

VCC (VREF)(Pin 8): Power Supply Voltage. This pin provides

power and deﬁ nes the span of the A/D converter. It must

be free of noise and ripple by bypassing directly to the

analog ground plane.

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

BLOCK DIAGRAM

LTC1096/LTC1096L

–

CSAMPLE

BIAS AND

SHUTDOWN CIRCUIT SERIAL PORT

VCC (VCC/VREF)CS CLK

DOUT

IN+ (CH0)

IN– (CH1)

MICROPOWER

COMPARATOR

CAPACITIVE DAC

SAR

VREF

GND PIN NAMES IN PARENTHESES

REFER TO THE LTC1098/LTC1098L

(DIN)

10968 BD

TEST CIRCUITS

On and Off Channel Leakage Current Load Circuit for tdDO, tr and tf

DOUT

1.4V

3kΩ

100pF

TEST POINT

10968 TC02

IOFF

ION

POLARITY

OFF

CHANNEL

ON CHANNEL

10968 TC01

•

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

TEST CIRCUITS

Load Circuit for tdis and ten

Voltage Waveforms for DOUT Delay Time, tdDO Voltage Waveforms for DOUT Rise and Fall Times, tr, tf

Voltage Waveforms for tdis

CLK

DOUT

VIL

tdDO

VOH

VOL

10968 TC03

DOUT

trtf10968 TC04

VOH

VOL

DOUT

100pF

TEST POINT

5V tdis WAVEFORM 2, ten

tdis WAVEFORM 1

10968 TC05

DOUT

WAVEFORM 1

(SEE NOTE 1)

2.0V

tdis

90%

10%

DOUT

WAVEFORM 2

(SEE NOTE 2)

NOTE 1: WAVEFORM 1 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS HIGH UNLESS DISABLED BY THE OUTPUT CONTROL.

NOTE 2: WAVEFORM 2 IS FOR AN OUTPUT WITH INTERNAL CONDITIONS SUCH

THAT THE OUTPUT IS LOW UNLESS DISABLED BY THE OUTPUT CONTROL.

10968 TC06

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

TEST CIRCUITS

Voltage Waveforms for ten

12345

LTC1098/LTC1098L

DIN

CLK

DOUT

START

ten

10968 TC08

VOL

10968 TC07

tWAKEUP

LTC1096/LTC1096L

CLK

DOUT

ten

VOL

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

10968 AI Ex

CLK

NULL BIT B7

tWAKEUP

10μs

tsu

tWAKEUP

DOUT

CLK

DOUT

APPLICATIONS INFORMATION

OVERVIEW

The LTC1096/LTC1096L/LTC1098/LTC1098L are 8-bit

micropower, switched-capacitor A/D converters. These

sampling ADCs typically draw 120μA of supply current

when sampling up to 33kHz. Supply current drops linearly

as the sample rate is reduced (see Supply Current vs

Sample Rate on the ﬁ rst page of this data sheet). The ADCs

automatically power down when not performing conver-

sion, drawing only leakage current. They are packaged in

8-pin SO packages. The LTC1096L/LTC1098L operate on

a single supply ranging from 2.65V to 4V. The LTC1096

operates on a single supply ranging from 3V to 9V while

the LTC1098 operates from 3V to 6V supplies.

The LTC1096/LTC1096L/LTC1098/LTC1098L comprise an

8-bit, switched-capacitor ADC, a sample-and-hold and a

serial port (see Block Diagram). Although they share the

same basic design, the LTC1096(L) and LTC1098(L) differ

in some respects. The LTC1096(L) has a differential input

and has an external reference input pin. It can measure

signals ﬂ oating on a DC common mode voltage and can

operate with reduced spans down to 250mV. Reducing the

span allows it to achieve 1mV resolution. The LTC1098(L)

has a 2-channel input multiplexer and can convert either

channel with respect to ground or the difference between

the two.

SERIAL INTERFACE

The LTC1098(L) communicates with microprocessors and

other external circuitry via a synchronous, half duplex,

4-wire serial interface while the LTC1096(L) uses a 3-wire

interface (see Operating Sequence in Figures 1 and 2).

Power Down and Wake-Up Time

The LTC1096(L)/LTC1098(L) draw power when the CS

pin is low and shut themselves down when that pin is

high. In order to have a correct conversion result, a 10μs

wake-up time must be provided from CS falling to the

ﬁ rst falling clock (CLK) after the ﬁ rst rising CLK for the

LTC1096(L) and from CS falling to the MSBF bit CLK fall-

ing for the LTC1098(L) (see Operating Sequence). If the

LTC1096(L)/LTC1098(L) are running with clock frequency

less than or equal to 100kHz, the wake-up time is inher-

ently provided.

Example

Two cases are shown at right to illustrate the relationship

among wake-up time, setup time and CLK frequency for

the LT1096(L).

In Case 1 the clock frequency is 100kHz. One clock cycle

is 10μs which can be the wake-up time, while half of that

can be the setup time. In Case 2 the clock frequency is

50kHz, half of the clock cycle plus the setup time (=1μs)

can be the wake-up time. If the CLK frequency is higher

than 100kHz, Figure 1 shows the relationship between the

wake-up time and setup time.

Case 2. Timing Diagram

Case 1. Timing Diagram

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

The wake-up time is inherently provided for the LTC1098(L)

with setup time = 1μs (see Figure 2).

Data Transfer

The CLK synchronizes the data transfer with each bit being

transmitted on the falling CLK edge and captured on the

rising CLK edge in both transmitting and receiving sys-

tems. The LTC1098(L) ﬁ rst receives input data and then

transmits back the A/D conversion result (half duplex).

Because of the half duplex operation, DIN and DOUT may

be tied together allowing transmission over just three

wires: CS, CLK and DATA (DIN/DOUT).

Data transfer is initiated by a falling chip select (CS) signal.

After CS falls the LTC1098(L) looks for a start bit. After the

start bit is received, the 3-bit input word is shifted into the

DIN input which conﬁ gures the LTC1098(L) and starts the

conversion. After one null bit, the result of the conversion

Figure 1. LTC1096(L) Operating Sequence

is output on the DOUT line. At the end of the data exchange

CS should be brought high. This resets the LTC1098(L) in

preparation for the next data exchange.

The LTC1096(L) does not require a conﬁ guration input

word and has no DIN pin. A falling CS initiates data trans-

feras shown in the LTC1096(L) operating sequence. After

CS falls, the ﬁ rst CLK pulse enables DOUT

. After one null

bit, the A/D conversion result is output on the DOUT line.

Bringing CS high resets the LTC1096(L) for the next data

exchange.

CLK

tCYC

B7*B6B5

B2B1

B3B4B5

NULL

BIT Hi-Z

DOUT

10968 F01

POWER

DOWN

Hi-Z

tsuCS

tWAKEUP

tCONV

CLK

tCYC

POWER

DOWN

tWAKEUP

B4B5

B6B7 Hi-Z

DOUT

tCONV

HI-Z

tsuCS

NULL

BIT

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.

(MSB)

APPLICATIONS INFORMATION

DIN 1 DIN 2

DOUT 1 DOUT 2

SHIFT MUX

ADDRESS IN

1 NULL BIT SHIFT A/D CONVERSION

RESULT OUT

10968 AI01

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

Input Data Word

The LTC1096(L) requires no DIN word. It is permanently

conﬁ gured to have a single differential input. The conver-

sion result, in which output on the DOUT line is MSB-ﬁ rst

sequence, followed by LSB sequence providing easy

interface to MSB- or LSB-ﬁ rst serial ports.

The LTC1098(L) clocks data into the DIN input on the ris-

ing edge of the clock. The input data words are deﬁ ned

as follows:

Start Bit

The ﬁ rst “logical one” clocked into the DIN input after CS

goes low is the start bit. The start bit initiates the data

transfer. The LTC1098(L) will ignore all leading zeros which

precede this logical one. After the start bit is received,

the remaining bits of the input word will be clocked in.

Further inputs on the DIN pin are then ignored until the

next CS cycle.

APPLICATIONS INFORMATION

CLK

tCYC

POWER

DOWN

tsuCS

tWAKEUP

DIN

SGL/

DIFF

MSBF

B0*

B4B5

B6B7

NULL

BIT Hi-Z

DOUT

tCONV

tSMPL

HI-Z

START

ODD/

SIGN

DON'T CARE

MSB-FIRST DATA (MSBF = 0)

MSB-FIRST DATA (MSBF = 1)

10968 F02

CLK

tCYC

POWER

DOWN

tsuCS

tWAKEUP

DIN

SGL/

DIFF

MSBF

B1B2

B4B5

NULL

BIT Hi-Z

DOUT

tCONV

tSMPL

HI-Z

START

ODD/

SIGN

DON'T CARE

B7*B6B5

B3B2B1

*AFTER COMPLETING THE DATA TRANSFER, IF FURTHER CLOCKS ARE APPLIED WITH CS LOW, THE ADC WILL OUTPUT ZEROS INDEFINITELY.

(MSB)

Figure 2. LTC1098(L) Operating Sequence Example: Differential Inputs (CH+, CH–)

SGL/

DIFF

ODD/

SIGN MSBFSTART

MUX

ADDRESS

MSB-FIRST

LSB-FIRST

10968 AI02

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

APPLICATIONS INFORMATION

Multiplexer (MUX) Address

The bits of the input word following the START bit assign

the MUX conﬁ guration for the requested conversion. For

a given channel selection, the converter will measure the

voltage between the two channels indicated by the “+”

and “–” signs in the selected row of the followintg tables.

In single-ended mode, all input channels are measured

with respect to GND.

MSB-First/LSB-First (MSBF)

The output data of the LTC1098(L) is programmed for

MSB-ﬁ rst or LSB-ﬁ rst sequence using the MSBF bit.

When the MSBF bit is a logical one, data will appear on

the DOUT line in MSB-ﬁ rst format. Logical zeros will be

ﬁ lled in indeﬁ nitely following the last data bit. When the

MSBF bit is a logical zero, LSB-ﬁ rst data will follow the

normal MSB-ﬁ rst data on the DOUT line. (see Operating

Sequence)

MUX ADDRESS

SGL/DIFF

ODD/SIGN

CHANNEL #

–

GND

–

SINGLE-ENDED MUX MODE

DIFFERENTIAL MUX MODE

10968 AI03

OUTPUT CODE

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 0

•

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

INPUT VOLTAGE

VREF – 1LSB

VREF – 2LSB

•

1LSB

INPUT VOLTAGE

(VREF = 5.000V)

4.9805V

4.9609V

•

0.0195V

10968 AI05

1LSB

VREF–2LSB

VREF–1LSB

VREF

VIN

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 0

•

10968 AI04

Unipolar Transfer Curve

The LTC1096(L)/LTC1098(L) are permanently conﬁ gured

for unipolar only. The input span and code assignment for

this conversion type are shown in the following ﬁ gures

for a 5V reference.

Unipolar Transfer Curve

LTC1098(L) Channel Selection

Unipolar Output Code

Operation with DIN and DOUT Tied Together

The LTC1098(L) can be operated with DIN and DOUT tied

together. This eliminates one of the lines required to com-

municate to the microprocessor (MPU). Data is transmit-

ted in both directions on a single wire. The processor pin

connected to this data line should be conﬁ gurable as either

an input or an output. The LTC1098(L) will take control of

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

APPLICATIONS INFORMATION

Figure 3. LTC1098(L) Operation with DIN and DOUT Tied Together

Figure 4. Automatic Power Shutdown Between Conversions

Allows Power Consumption to Drop with Sample Rate

Figure 5. After a Conversion, When the Microprocessor

Drives CS High, the ADC Automatically Shuts Down Until the

Next Conversion. The Supply Current, Which Is Very Low

During cConversions, Drops to Zero in Shutdown

the data line and drive it low on the 4th falling CLK edge

after the start bit is received (see Figure 3). Therefore the

processor port line must be switched to an input before

this happens, to avoid a conﬂ ict.

In the Typical Applications section, there is an example of

interfacing the LTC1098(L) with DIN

and DOUT tied together

to the Intel 8051 MPU.

ACHIEVING MICROPOWER PERFORMANCE

With typical operating currents of 40μA and automatic

shutdown between conversions, the LTC1096/LTC1098

achieves extremely low power consumption over a wide

range of sample rates (see Figure 4). In systems that

convert continuously, the LTC1096/LTC1098 will draw

1234

CLK

DATA (DIN/DOUT) START SGL/DIFF ODD/SIGN MSBF B7 B6 •••

MSBF BIT LATCHED

BY LTC1098(L)

LTC1098(L) CONTROLS DATA LINE AND SENDS

A/D RESULT BACK TO MPU

MPU CONTROLS DATA LINE AND SENDS

MUX ADDRESS TO LTC1098(L)

PROCESSOR MUST RELEASE

DATA LINE AFTER 4TH RISING CLK

AND BEFORE THE 4TH FALLING CLK

LTC1098(L) TAKES CONTROL OF

DATA LINE ON 4TH FALLING CLK

10968 F03

its normal operating power continuously. Figure 5 shows

that the typical current varies from 40μA at clock rates

below 50kHz to 100μA at 500kHz. Several things must

be taken into account to achieve such a low power

consumption.

Sample Rate, fSAMPLE (kHz)

0.1

SUPPLY CURRENT, ICC (μA)

100

1000

1 10 100

10968 F04

TA = 25°C

VCC = 5V CLOCK FREQUENCY (Hz)

SUPPLY CURRENT, ICC (μA)

120

140

100 10k 100k 1M

10968 F05

100

0.002

TA = 25°C

VCC = 5V

ACTIVE (CS LOW)

SHUTDOWN (CS HIGH)

SUPPLY CURRENT vs CLOCK RATE FOR

ACTIVE AND SHUTDOWN MODES

Shutdown

Figures 1 and 2 show the operating sequence of the

LTC1096/LTC1098. The converter draws power when the

CS pin is low and powers itself down when that pin is high.

If the CS pin is not taken to ground when it is low and not

taken to supply voltage when it is high, the input buffers

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

APPLICATIONS INFORMATION

of the converter will draw current. This current may be

larger than the typical supply current. It is worthwhile to

bring the CS pin all the way to ground when it is low and

all the way to supply voltage when it is high to obtain the

lowest supply current.

When the CS pin is high (= supply voltage), the converter

is in shutdown mode and draws only leakage current. The

status of the DIN and CLK input have no effect on supply

current during this time. There is no need to stop DIN and

CLK with CS = high, except the MPU may beneﬁ t.

Minimize CS Low Time

In systems that have signiﬁ cant time between conversions,

lowest power drain will occur with the minimum CS low

time. Bringing CS low, waiting 10μs for the wake-up time,

transferring data as quickly as possible, and then bringing

it back high will result in the lowest current drain. This

minimizes the amount of time the device draws power.

Even though the device draws more power at high clock

rates, the net power is less because the device is on for

a shorter time.

DOUT Loading

Capacitive loading on the digital output can increase

power consumption. A 100pF capacitor on the DOUT pin

can more than double the 100μA supply current drain at a

500kHz clock frequency. An extra 100μA or so of current

goes into charging and discharging the load capacitor. The

same goes for digital lines driven at a high frequency by

any logic. The CxVxf currents must be evaluated and the

troublesome ones minimized.

Lower Supply Voltage

For lower supply voltages, LTC offers the LTC1096L/

LTC1098L. These pin compatible devices offer speciﬁ ed

performance to 2.65VMIN supply.

OPERATING ON OTHER THAN 5V SUPPLIES

The LTC1096 operates from 3V to 9V supplies and the

LTC1098 operates from 3V to 6V supplies. To operate the

LTC1096/LTC1098 on other than 5V supplies, a few things

must be kept in mind.

Wake-Up Time

A 10μs wake-up time must be provided for the ADCs

to convert correctly on a 5V supply. The wake-up time

is typically less than 3μs over the supply voltage range

(see typical curve of Wake-Up Time vs Supply Voltage).

With 10μs wake-up time provided over the supply range,

the ADCs will have adequate time to wake up and acquire

input signals.

Input Logic Levels

The input logic levels of CS, CLK and DIN are made to meet

TTL on 5V supply. When the supply voltage varies, the

input logic levels also change. For the LTC1096/LTC1098

to sample and convert correctly, the digital inputs have

to meet logic low and high levels relative to the operating

supply voltage (see typical curve of Digital Input Logic

Threshold vs Supply Voltage). If achieving micropower

consumption is desirable, the digital inputs must go rail-

to-rail between supply voltage and ground (see ACHIEVING

MICROPOWER PERFORMANCE section).

Clock Frequency

The maximum recommended clock frequency is 500kHz

for the LTC1096/LTC1098 running off a 5V supply. With the

supply voltage changing, the maximum clock frequency

for the devices also changes (see the typical curve of

Maximum Clock Rate vs Supply Voltage). If the maximum

clock frequency is used, care must be taken to ensure that

the device converts correctly.

Mixed Supplies

It is possible to have a microprocessor running off a 5V

supply and communicate with the LTC1096/LTC1098 op-

erating on 3V or 9V supplies. The requirement to achieve

this is that the outputs of CS, CLK and DIN from the MPU

have to be able to trip the equivalent inputs of the ADCs

and the output of DOUT from the ADCs must be able to

toggle the equivalent input of the MPU (see typical curve

of Digital Input Logic Threshold vs Supply Voltage). With

the LTC1096 operating on a 9V supply, the output of DOUT

may go between 0V and 9V. The 9V output may damage

the MPU running off a 5V supply. The way to get around

this possibility is to have a resistor divider on DOUT

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

APPLICATIONS INFORMATION

Figure 7. LTC1098(L) “+” and “–” Input Settling Windows

(Figure 6) and connect the center point to the MPU input.

It should be noted that to get full shutdown, the CS input

of the LTC1096/LTC1098 must be driven to the VCC volt-

age. This would require adding a level shift circuit to the

CS signal in Figure 6.

Figure 6. Interfacing a 9V Powered LTC1096 to a 5V System

BOARD LAYOUT CONSIDERATIONS

Grounding and Bypassing

The LTC1096(L)/LTC1098(L) should be used with an analog

ground plane and single point grounding techniques. The

GND pin should be tied directly to the ground plane.

The VCC pin should be bypassed to the ground plane with

a 1μF tantalum with leads as short as possible. If power

supply is clean, the LTC1096(L)/LTC1098(L) can also oper-

ate with smaller 0.1μF surface mount or ceramic bypass

capacitors. All analog inputs should be referenced directly

to the single point ground. Digital inputs and outputs should

be shielded from and/or routed away from the reference

and analog circuitry.

SAMPLE-AND-HOLD

Both the LTC1096(L) and the LTC1098(L) provide a built-in

sample-and-hold (S&H) function to acquire signals. The

S&H of the LTC1096(L) acquires input signals from “+”

input relative to “–” input during the tWAKEUP time (see

Figure 1). However, the S&H of the LTC1098(L) can sample

input signals in the single-ended mode or in the differential

inputs during the tSMPL time (see Figure 7).

Single-Ended Inputs

The sample-and-hold of the LTC1098(L) allows conversion

of rapidly varying signals. The input voltage is sampled

during the tSMPL time as shown in Figure 7. The sampling

interval begins as the bit preceding the MSBF bit is shifted

+IN

–IN

GND

VCC

CLK

DOUT

VREF

50k

50k6V

4.7μF

MPU

(e.g. 8051) 5V

P1.4

P1.3

P1.2

10968 F06

DIFFERENTIAL INPUTS

COMMON MODE RANGE

0V TO 6V

LTC1096

OPTIONAL

LEVEL SHIFT

CLK

DIN

DOUT

"+" INPUT

"–" INPUT

SAMPLE HOLD

"+" INPUT MUST

SETTLE DURING

THIS TIME

tSMPL tCONV

SGL/DIFFSTART MSBF DON'T CARE

1ST BIT TEST "–" INPUT MUST

SETTLE DURING THIS TIME

10968 F07

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

in and continues until the falling CLK edge after the MSBF

bit is received. On this falling edge, the S&H goes into hold

mode and the conversion begins.

Differential Inputs

With differential inputs, the ADC no longer converts just a

single voltage but rather the difference between two volt-

ages. In this case, the voltage on the selected “+” input

is still sampled and held and therefore may be rapidly

time varying just as in single-ended mode. However, the

voltage on the selected “–” input must remain constant

and be free of noise and ripple throughout the conver-

sion time. Otherwise, the differencing operation may not

be performed accurately. The conversion time is 8 CLK

cycles. Therefore, a change in the “–” input voltage during

this interval can cause conversion errors. For a sinusoidal

voltage on the “–” input this error would be:

ERROR (MAX) = VPEAK • 2 • π • f(“–”) • 8/fCLK

Where f(“–”) is the frequency of the “–” input voltage,

VPEAK is its peak amplitude and fCLK is the frequency of

the CLK. In most cases VERROR will not be signiﬁ cant. For

a 60Hz signal on the “–” input to generate a 1/4LSB error

(5mV) with the converter running at CLK = 500kHz, its

peak value would have to be 750mV.

ANALOG INPUTS

Because of the capacitive redistribution A/D conversion

techniques used, the analog inputs of the LTC1096(L)/

LTC1098(L )have capacitive switching input current spikes.

These current spikes settle quickly and do not cause a

problem. However, if large source resistances are used

or if slow settling op amps drive the inputs, care must be

taken to ensure that the transients caused by the current

spikes settle completely before the conversion begins.

“+” Input Settling

The input capacitor of the LTC1096(L) is switched onto

“+” input during the wake-up time (see Figure 1) and

samples the input signal within that time. However, the

input capacitor of the LTC1098(L) is switched onto “+”

input during the sample phase (tSMPL, see Figure 7). The

sample phase is 1.5 CLK cycles before conversion starts.

The voltage on the “+” input must settle completely within

tWAKEUP or tSMPL for the LTC1096(L) or the LTC1098(L)

respectively. Minimizing RSOURCE+ and C1 will improve the

input settling time. If a large “+” input source resistance

must be used, the sample time can be increased by using

a slower CLK frequency.

“–” Input Settling

At the end of the tWAKEUP or tSMPL, the input capacitor

switches to the “–” input and conversion starts (see

Figures 1 and 7). During the conversion the “+” input

voltage is effectively “held” by the sample-and-hold and

will not affect the conversion result. However, it is criti-

cal that the “–” input voltage settles completely during

the ﬁ rst CLK cycle of the conversion time and be free of

noise. Minimizing RSOURCE– and C2 will improve settling

time. If a large “–” input source resistance must be used,

the time allowed for settling can be extended by using a

slower CLK frequency.

Input Op Amps

When driving the analog inputs with an op amp it is im-

portant that the op amp settle within the allowed time (see

Figure 7). Again, the “+” and “–” input sampling times can

be extended as described above to accommodate slower

op amps. Most op amps, including the LT1006 and LT1413

single supply op amps, can be made to settle well even

with the minimum settling windows of 3μs (“+” input)

which occur at the maximum clock rate of 500kHz.

Source Resistance

The analog inputs of the LTC1096/LTC1098 look like a 25pF

capacitor (CIN) in series with a 500Ω resistor (RON) as

shown in Figure 8. CIN gets switched between the selected

“+” and “–” inputs once during each conversion cycle.

Figure 8. Analog Input Equivalent Circuit

RON = 500Ω

CIN = 25pF

LTC1096

LTC1098

“+”

INPUT

RSOURCE +

VIN +

“–”

INPUT

RSOURCE –

VIN –

10968 F08

APPLICATIONS INFORMATION

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

capacitive current spike will be generated on the reference

pin by the ADC. These current spikes settle quickly and do

not cause a problem.

Using a slower CLK will allow more time for the reference

to settle. Even at the maximum CLK rate of 500kHz most

references and op amps can be made to settle within the

Large external source resistors and capacitances will slow

the settling of the inputs. It is important that the overall

RC time constants be short enough to allow the analog

inputs to completely settle within the allowed time.

RC Input Filtering

It is possible to ﬁ lter the inputs with an RC network as

shown in Figure 9. For large values of CF (e.g., 1μF), the

capacitive input switching currents are averaged into a

net DC current. Therefore, a ﬁ lter should be chosen with

a small resistor and large capacitor to prevent DC drops

across the resistor. The magnitude of the DC current is

approximately IDC = 25pF(VIN/tCYC) and is roughly pro-

portional to VIN. When running at the minimum cycle time

of 29μs, the input current equals 4.3μA at VIN = 5V. In this

case, a ﬁ lter resistor of 390Ω will cause 0.1LSB of full-

scale error. If a larger ﬁ lter resistor must be used, errors

can be eliminated by increasing the cycle time.

Figure 9. RC Input Filtering

Input Leakage Current

Input leakage currents can also create errors if the source

resistance gets too large. For instance, the maximum input

leakage speciﬁ cation of 1μA (at 125°C) ﬂ owing through a

source resistance of 3.9k will cause a voltage drop of 3.9mV

or 0.2LSB. This error will be much reduced at lower tem-

peratures because leakage drops rapidly (see typical curve

of Input Channel Leakage Current vs Temperature).

REFERENCE INPUTS

The voltage on the reference input of the LTC1096 deﬁ nes

the voltage span of the A/D converter. The reference

input transient capacitive switching currents due to the

switched-capacitor conversion technique (see Figure 10).

During

each bit test of the conversion (every CLK cycle), a

Figure 10. Reference Input Equivalent Circuit

2μs bit time.

Reduced Reference Operation

The minimum reference voltage of the LTC1098 is limited

to 3V because the VCC supply and reference are internally

tied together. However, the LTC1096 can operate with

reference voltages below 1V.

The effective resolution of the LTC1096 can be increased

by reducing the input span of the converter. The LTC1096

exhibits good linearity and gain over a wide range of ref-

erence voltages (see typical curves of Linearity and Full

Scale Error vs Reference Voltage). However, care must be

taken when operating at low values of VREF because of the

reduced LSB step size and the resulting higher accuracy

requirement placed on the converter. The following factors

must be considered when operating at low VREF values.

1. Offset

2. Noise

3. Conversion speed (CLK frequency)

Offset with Reduced VREF

The offset of the LTC1096 has a larger effect on the output

code when the ADC is operated with reduced reference

voltage. The offset (which is typically a ﬁ xed voltage)

becomes a larger fraction of an LSB as the size of the

LSB is reduced. The typical curve of Unadjusted Offset

Error vs Reference Voltage shows how offset in LSBs is

APPLICATIONS INFORMATION

RFILTER

VIN

CFILTER

10968 F09

LTC1098

“+”

“–”

IDC

RON

5pF TO 30pF

LTC1096

REF+

ROUT

VREF

EVERY CLK CYCLE

GND

10968 F10

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

APPLICATIONS INFORMATION

related to reference voltage for a typical value of VOS. For

example, a VOS of 2mV which is 0.1LSB with a 5V reference

becomes 0.5LSB with a 1V reference and 2.5LSBs with

a 0.2V reference. If this offset is unacceptable, it can be

corrected digitally by the receiving system or by offsetting

the “–” input of the LTC1096.

Noise with Reduced VREF

The total input referred noise of the LTC1096 can be reduced

to approximately 1mV peak-to-peak using a ground plane,

good bypassing, good layout techniques and minimizing

noise on the reference inputs. This noise is insigniﬁ cant

with a 5V reference but will become a larger fraction of

an LSB as the size of the LSB is reduced.

For operation with a 5V reference, the 1mV noise is only

0.05LSB peak-to-peak. In this case, the LTC1096 noise

will contribute virtually no uncertainty to the output code.

However, for reduced references, the noise may become

a signiﬁ cant fraction of an LSB and cause undesirable jit-

ter in the output code. For example, with a 1V reference,

this same 1mV noise is 0.25LSB peak-to-peak. This will

reduce the range of input voltages over which a stable

output code can be achieved by 1LSB. If the reference is

further reduced to 200mV, the 1mV noise becomes equal

to 1.25LSBs and a stable code may be difﬁ cult to achieve.

In this case averaging readings may be necessary.

This noise data was taken in a very clean setup. Any setup-

induced noise (noise or ripple on VCC, VREF or VIN) will

add to the internal noise. The lower the reference voltage

to be used, the more critical it becomes to have a clean,

noise free setup.

Conversion Speed with Reduced VREF

With reduced reference voltages the LSB step size is

reduced and the LTC1096 internal comparator overdrive

is reduced. Therefore, it may be necessary to reduce

the maximum CLK frequency when low values of VREF

are used.

Input Divider

It is OK to use an input divider on the reference input of

the LTC1096 as long as the reference input can be made

to settle within the bit time at which the clock is running.

When using a larger value resistor divider on the reference

input the “–” input should be matched with an equivalent

resistance.

Bypassing Reference Input with Divider

Bypassing the reference input with a divider is also pos-

sible. However, care must be taken to make sure that the

DC voltage on the reference input will not drop too much

below the intended reference voltage.

AC PERFORMANCE

Two commonly used ﬁ gures of merit for specifying the

dynamic performance of the ADCs in digital signal pro-

cessing applications are the signal-to-noise ratio (SNR)

and the effective number of bits (ENOBs).

Signal-to-Noise Ratio

The signal-to-noise ratio (SNR) is the ratio between the

RMS amplitude of the fundamental input frequency to

the RMS amplitude of all other frequency components at

the A/D output. This includes distortion as well as noise

products and for this reason it is sometimes referred to as

signal-to-noise + distortion [S/(N + D)]. The output is band

limited to frequencies from DC to one half the sampling

frequency. Figure 11 shows spectral content from DC to

15.625kHz which is 1/2 the 31.25kHz sampling rate.

Figure 11. This Clean FFT of an 11.8kHz Input Shows

Remarkable Performance for an ADC That Draws Only 100μA

When Sampling at the 31.25kHz Rate

FREQUENCY (kHz)

AMPLITUDE (dB)

–60

–30

–20

10968 F11

–70

–80

–120 4812

–100

–10

–40

–50

–90

–110

2610 14

fSAMPLE = 31.25kHz

fIN = 11.8kHz

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

MICROPROCESSOR INTERFACES

The LTC1096(L)/LTC1098(L) can interface directly (without

external hardware to most popular microprocessor (MPU)

synchronous serial formats (see Table 1). If an MPU without

a dedicated serial port is used, then three or four of the

MPU’s parallel port lines can be programmed to form the

serial link to the LTC1096(L)/LTC1098(L). Included here

is one serial interface example and one example showing

a parallel port programmed to form the serial interface.

Motorola SPI (MC68HC05C4,CM68HC11)

The MC68HC05C4 has been chosen as an example of

an MPU with a dedicated serial port. This MPU transfer

data MSB-ﬁ rst and in 8-bit increments. With two 8-bit

transfers, the A/D result is read into the MPU. The ﬁ rst

8-bit transfer sends the DIN word to the LTC1098(L) and

clocks into the processor. The second 8-bit transfer clocks

the A/D conversion result, B7 through B0, into the MPU.

ANDing the ﬁ rst MUP received byte with 00Hex clears the

ﬁ rst byte. Notice how the position of the start bit in the

ﬁ rst MPU transmit word is used to position the A/D result

right-justiﬁ ed in two memory locations.

APPLICATIONS INFORMATION

TYPICAL APPLICATIONS

Effective Number of Bits

The effective number of bits (ENOBs) is a measurement

of the resolution of an A/D and is directly related to the

S/(N + D) by the equation:

ENOB = [S/(N + D) –1.76]/6.02

where S/(N + D) is expressed in dB. At the maximum sam-

pling rate of 33kHz the LTC1096 maintains 7.5 ENOBs or

better to 40kHz. Above 40kHz the ENOBs gradually decline,

as shown in Figure 12, due to increasing second harmonic

distortion. The noise ﬂ oor remains approximately 70dB.

Figure 12. Dynamic Accuracy Is Maintained Up to an Input

Frequency of 40kHz

INPUT FREQUENCY (kHz)

EFFECTIVE NUMBER OF BITS (ENOBs)

10968 F12

020 40

fSAMPLE = 31.25kHz

Table 1. Microprocessor with Hardware Serial Interfaces

Compatible with the LTC1096(L)/LTC1098(L)

PART NUMBER TYPE OF INTERFACE

Motorola

MC6805S2,S3

MC68HC11

MC68HC05

SPI

RCA

CDP68HC05 SPI

Hitachi

HD6305

HD63705

HD6301

HD63701

HD6303

HD64180

SCI Synchronous

CSI/O

National Semiconductor

COP400 Family

COP800 Family

NS8050U

HPC16000 Family

MICROWIRE™

MICROWIRE/PLUS™

MICROWIRE/PLUS

Texas Instruments

TMS7002

TMS7042

TMS70C02

TMS70C42

TMS32011*

TMS32020

Serial Port

* Requires external hardware

MICROWIRE and MICROWIRE/PLUS are trademarks of

National Semiconductor Corp.

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

TYPICAL APPLICATIONS

MPU TRANSMIT

WORD

CLK

DOUT

MPU RECEIVED

WORD

DIN

0001

ODD/

SIGN MSBF

SGL/

DIFF

XXXXXXXX

START

BIT

BYTE 1 BYTE 2 (DUMMY)

X = DON'T CARE

START

SGL/

DIFF

DON'T CARE

B7 B6 B5 B4 B3 B2 B1 B0

ODD/

SIGN MSBF

???????0 B7 B6 B5 B4 B3 B2 B1 B0

2ND TRANSFER1ST TRANSFER 10968 TA03

10968 TA04

CLK

DIN

ANALOG

INPUTS

SCK

DOUT

MISO

MOSI

MC68HC05C4

LTC1098

LOCATION A + 1

LSB

LOCATION A

BYTE 2

BYTE 1

10968 TA05

B7 B6 B5 B4 B3 B2 B1 B0

00000000

Data Exchange Between LTC1098(L) and MC68HC05C4

Hardware and Software Interface to Motorola MC68HC05C4

DOUT from LTC1098(L) Stored in MC68HC05C4

LABEL MNEMONIC COMMENTS

START BCLRn

LDA

STA

TST

BPL

LDA

STA

AND

STA

TST

BPL

BSETn

LDA

STA

Bit 0 Port C goes low (CS goes low)

Load LTC1098(L) DIN word into Acc.

Load LTC1098(L) DIN word into SPI from Acc.

Transfer begins.

Test status of SPIF

Loop to previous instruction if not done

with transfer

Load contents of SPI data register

into Acc. (DOUT MSBs)

Start next SPI cycle

Clear the ﬁ rst DOUT word

Store in memory location A (MSBs)

Test status of SPIF

Loop to previous instruction if not done

with transfer

Set B0 of Port C (CS goes high)

Load contents of SPI data register into

Acc. (DOUT LSBs)

Store in memory location A + 1 (LSBs)

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

TYPICAL APPLICATIONS

Interfacing to the Parallel Port of the

Intel 8051 Family

The Intel 8051 has been chosen to demonstrate the

interface between the LTC1098(L) and parallel port mi-

croprocessors. Normally the CS, CLK and DIN signals

would be generated on three port lines and the DOUT signal

read on a fourth port line. This works very well. However,

we will demonstrate here an interface with the DIN and

DOUT of the LTC1098(L) tied together as described in the

SERIAL INTERFACE section. This saves one wire.

The 8051 ﬁ rst sends the start bit and MUX address to the

LTC1098(L) over the data line connected to P1.2. Then

P1.2 is reconﬁ gured as an input (by writing to it a one) and

the 8051 reads back the 8-bit A/D result over the same

data line.

DOUT from LTC1098(L) Stored in 8051 RAM

CLK

DOUT

DIN

LTC1098(L)

ANALOG

INPUTS

P1.4

P1.3

P1.2 8051

MUX ADDRESS

A/D RESULT 10968 TA06

10968 TA07

MSB LSB

B7 B6 B5 B4 B3 B2 B1 B0

CLK

DATA (DIN/DOUT)START ODD/

SIGN MSBF B7

MSBF BIT LATCHED

BY LTC1098(L)

LTC1098(L) SENDS A/D RESULT

BACK TO 8051 P1.2

8051 P1.2 OUTPUTS DATA

TO LTC1098(L)

8051 P1.2 RECONFIGURED

AS AN INPUT AFTER THE 4TH RISING

CLK AND BEFORE THE 4TH FALLING CLK

LTC1098(L) TAKES CONTROL OF DATA LINE

ON 4TH FALLING CLK

234

SGL/

DIFF B6 B5 B4 B3 B2 B1 B0

10968 TA08

LABEL MNEMONIC OPERAND COMMENTS

LOOP 1

LOOP

MOV

SETB

CLR

MOV

RLC

CLR

MOV

SETB

DJNZ

MOV

CLR

MOV

RLC

SETB

CLR

DJNZ

MOV

SETB

A, #FFH

P1.4

R4, #04

P1.3

P1.2, C

P1.3

R4, LOOP 1

P1, #04

P1.3

R4, #09

C, P1.2

P1.3

R4, LOOP

R2, A

P1.4

DIN word for LTC1098(L)

Make sure CS is high

CS goes low

Load counter

Rotate DIN bit into Carry

CLK goes low

Output DIN bit to LTC1098(L)

CLK goes high

Next bit

Bit 2 becomes an input

CLK goes low

Load counter

Read data bit into Carry

Rotate data bit into Acc.

CLK goes high

CLK goes low

Next bit

Store MSBs in R2

CS goes high

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

A “Quick Look” Circuit for the LTC1096

Users can get a quick look at the function and timing of

the LT1096 by using the following simple circuit (Figure

13). VREF is tied to VCC. VIN is applied to the +IN input and

the –IN input is tied to the ground. CS is driven at 1/16

the clock rate by the 74C161 and DOUT outputs the data.

The output data from the DOUT pin can be viewed on an

oscilloscope that is set up to trigger on the falling edge

of CS (Figure 14). Note the LSB data is partially clocked

out before CS goes high.

Figure 15. The LTC1096’s High Impedance Input Connects

Directly to This Temperature Sensor, Eliminating Signal

Conditioning Circuitry in This 0°C to 70°C Thermometer

Figure 14. Scope Trace the LTC1096 “Quick Look” Circuit

Showing A/D Output 10101010 (AAHEX)

Figure 13. “Quick Look” Circuit for the LTC1096

Figure 15 shows a temperature measurement system.

The LTC1096 is connected directly to the low cost silicon

temperature sensor. The voltage applied to the VREF pin

adjusts the full scale of the A/D to the output range of the

sensor. The zero point of the converter is matched to the

zero output voltage of the sensor by the voltage on the

LTC1096’s negative input.

CLR

CLK

GND

VCC

LOAD

74C161

VIN

TO OSCILLOSCOPE

CLOCK IN 150kHz MAX

10968 F13

VCC

CLK

DOUT

VREF

LTC1096

CH0

CH1

GND

4.7μF 5V

LTC1096

+IN

–IN

VREF

CLK

DOUT

VCC

GND

TO μP

63.4k

0.01μF

182k

0.01μF

LT1004-1.2

0.1μF

75k

678Ω

13.5k

LM134

10968 F15

VERTICAL: 5V/DIV

HORIZONTAL: 10μs/DIV

NULL

BIT

CLK

DOUT

MSB

(B7)

LSB

(B0)

LSB DATA

(B1)

10968 F14

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

Remote or Isolated Systems

Figure 16 shows a ﬂ oating system that sends data to a

grounded host system. The ﬂ oating circuitry is isolated by

two optoisolators and powered by a simple capacitor diode

charge pump. The system has very low power requirements

because the LTC1096 shuts down between conversions

and the optoisolators draw power only when data is being

transferred. The system consumes only 50μA at a sample

rate of 10Hz (1ms on-time and 99ms off-time). This is

easily within the current supplied by the charge pump

running at 5MHz. If a truly isolated system is required,

the system’s low power simpliﬁ es generating an isolated

supply or powering the system from a battery.

Figure 16. Power for This Floating A/D System Is Provided by a Simple Capacitor Diode Charge Pump. The Two Optoisolators

Draw No Current Between Samples, Turning On Only to Send the Clock and Receive Data

LTC1096 +IN

–IN

DOUT

CLK

VCC

GND

VREF

75k

LT1004-2.5

20k

0.1μF

1N5817

0.022μF

47μF

1N5817

0.001μF

2kV

5MHz

100k

300Ω

10k

500k

ANALOG

INPUT

FLOATING SYSTEM

CLK

DATA

100k

10968 F16

2N3904

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

PACKAGE DESCRIPTION

N8 Package

8-Lead PDIP (Narrow .300 Inch)

(Reference LTC DWG # 05-08-1510)

N8 1002

.065

(1.651)

TYP

.045 – .065

(1.143 – 1.651)

.130 ± .005

(3.302 ± 0.127)

.020

(0.508)

MIN

.018 ± .003

(0.457 ± 0.076)

.120

(3.048)

MIN

12 34

87 65

.255 ± .015*

(6.477 ± 0.381)

.400*

(10.160)

MAX

.008 – .015

(0.203 – 0.381)

.300 – .325

(7.620 – 8.255)

.325 +.035

–.015

+0.889

–0.381

8.255

()

NOTE:

1. DIMENSIONS ARE INCHES

MILLIMETERS

*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .010 INCH (0.254mm)

.100

(2.54)

BSC

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

PACKAGE DESCRIPTION

S8 Package

8-Lead Plastic Small Outline (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1610)

.016 – .050

(0.406 – 1.270)

.010 – .020

(0.254 – 0.508)× 45°

0°– 8° TYP

.008 – .010

(0.203 – 0.254)

SO8 0303

.053 – .069

(1.346 – 1.752)

.014 – .019

(0.355 – 0.483)

TYP

.004 – .010

(0.101 – 0.254)

.050

(1.270)

BSC

1234

.150 – .157

(3.810 – 3.988)

NOTE 3

8765

.189 – .197

(4.801 – 5.004)

NOTE 3

.228 – .244

(5.791 – 6.197)

.245

MIN .160 ±.005

RECOMMENDED SOLDER PAD LAYOUT

.045 ±.005

.050 BSC

.030 ±.005

TYP

INCHES

(MILLIMETERS)

NOTE:

1. DIMENSIONS IN

2. DRAWING NOT TO SCALE

3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.

MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006" (0.15mm)

LTC1096/LTC1096L

LTC1098/LTC1098L

10968fc

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0708 REV C • PRINTED IN USA

RELATED PARTS

TYPICAL APPLICATION

PART NUMBER DESCRIPTION COMMENTS

LTC1196/LTC1198 8-Pin SO, 1Msps, 8-Bit ADCs Low Power, Small Size, Low Cost

LTC1286/LTC1298 8-Pin SO, 5V Micropower, 12-Bit ADCs 1- or 2-Channel, Auto Shutdown

LTC1285/LTC1298 8-Pin SO, 3V Micropower, 12-Bit ADCs 1- or 2-Channel, Auto Shutdown

LTC1400 5V High Speed,Serial 12-Bit ADC 400ksps, Complete with VREF, CLK, Sample-and-Hold

LTC1594/LTC1598 4- and 8-Channel, 5V Micropower, 12-Bit ADCs Low Power, Small Size, Low Cost

LTC1594L/LTC1598L 4- and 8-Channel, 3V Micropower, 12-Bit ADCs Low Power, Small Size, Low Cost

A/D Conversion for 3V Systems

The LTC1096/LTC1098 are ideal for 3V systems. Figure

17 shows a 3V to 6V battery current monitor that draws

only 70μA from the battery it monitors. The battery cur-

rent is sensed with the 0.02Ω resistor and ampliﬁ ed by

the LT1178. The LTC1096 digitizes the ampliﬁ er output

and sends it to the microprocessor in serial format. The

LT1004 provides the full-scale reference for the ADC. The

other half of the LTC1178 is used to provide low battery

detection. The circuit’s 70μA supply current is dominated

by the op amps and the reference. The circuit can be

located near the battery and data transmitted serially to

the microprocessor.

Figure 17. This 0A to 2A Battery Current Monitor Draws Only 70μA from a 3V Battery

–

750k

0.1μF

0.02Ω FOR 2A FULL SCALE

0.2Ω FOR 0.2A FULL SCALE

24.9k

1/2 LT1178 LTC1096

GND

VCC

CLK

DOUT

VREF

LT1004-1.2

73.2k 470k

20M

470k

LO BATTERY

0.1μF

–

3V TO 6V

TO μP

–

1/2 LT1178

10968 F17