LTC2365/LTC2366
1
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FEATURES
APPLICATIONS
DESCRIPTION
1Msps/3Msps, 12-Bit Serial
Sampling ADCs in TSOT
The LTC
®
2365/LTC2366 are 1Msps/3Msps, 12-bit, sam-
pling A/D converters that draw only 2mA and 2.6mA, re-
spectively, from a single 3V supply. These high performance
devices include a high dynamic range sample-and-hold
and a high speed serial interface. The full-scale input is
0V to VDD or VREF . Outstanding AC performance includes
72dB SINAD and –80dB THD at sample rates of 3Msps.
The serial interface provides fl exible power management
and allows maximum power effi ciency at low throughput
rates. These devices are available in tiny 6- and 8-lead
TSOT-23 packages.
The serial interface, tiny TSOT-23 package and extremely
high sample rate-to-power ratio make the LTC2365/LTC2366
ideal for compact, low power, high speed systems.
The high impedance single-ended analog input and the
ability to operate with reduced spans (down to 1.4V full
scale) allow direct connection to sensors and transducers in
many applications, eliminating the need for gain stages.
Single 3V Supply, 3Msps, 12-Bit Sampling ADC
n 12-Bit Resolution
n 1Msps/3Msps Sampling Rates
n Low Noise: 73dB SNR
n Low Power Dissipation: 6mW
n Single Supply 2.35V to 3.6V Operation
n No Data Latency
n Sleep Mode with 0.1μA Typical Supply Current
n Dedicated External Reference (TSOT23-8)
n 1V to 3.6V Digital Output Supply (TSOT23-8)
n SPI/MICROWIRE™ Compatible Serial I/O
n Guaranteed Operation from –40°C to 125°C
n 6- and 8-Lead TSOT-23 Packages
n Communication Systems
n Data Acquisition Systems
n Handheld Terminal Interface
n Medical Imaging
n Uninterrupted Power Supplies
n Battery-Operated Systems
n Automotive
1MHz Sine Wave 8192 FFT Plot
12-Bit TSOT23-6/-8 ADC Family
DATA OUTPUT RATE 3Msps 1Msps 500ksps 250ksps 100ksps
Part Number LTC2366 LTC2365 LTC2362 LTC2361 LTC2360
TYPICAL APPLICATION
VDD
VREF
GND
AIN
LTC2366
23656 TA01
ANALOG INPUT
0V TO 3V
3V
10μF
4.7μF
SERIAL DATA LINK TO
ASIC, PLD, MPU, DSP
OR SHIFT REGISTERS
DIGITAL OUTPUT SUPPLY
1V TO VDD
CS
SDO
SCK
OVDD
INPUT FREQUENCY (kHz)
0
0
–20
–40
–60
–80
–100
–120
–140 750 1250
23656 TA01b
250 500 1000 1500
MAGNITUE (dB)
VDD = 3V
fSMPL = 3Msps
fIN = 994kHz
SINAD = 72dB
THD = –80.3dB
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
LTC2365/LTC2366
2
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VDD) ...............................................4.0V
Supply Voltage (OVDD) ................ Min (VDD + 0.3V, 4.0V)
VREF and Analog Input Voltage
(Note 3) ........................................ –0.3V to (VDD + 0.3V)
Digital Input Voltage..................... –0.3V to (VDD + 0.3V)
Digital Output Voltage .................. –0.3V to (VDD + 0.3V)
(Notes 1, 2)
Lead Free Finish
TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2366CTS8#TRMPBF LTC2366CTS8#TRPBF LTCYZ 8-lead Plastic TSOT-23 0°C to 70°C
LTC2366ITS8#TRMPBF LTC2366ITS8#TRPBF LTCYZ 8-lead Plastic TSOT-23 –40°C to 85°C
LTC2366HTS8#TRMPBF LTC2366HTS8#TRPBF LTCYZ 8-lead Plastic TSOT-23 –40°C to 125°C
LTC2366CS6#TRMPBF LTC2366CS6#TRPBF LTCXK 6-lead Plastic TSOT-23 0°C to 70°C
LTC2366IS6#TRMPBF LTC2366IS6#TRPBF LTCXK 6-lead Plastic TSOT-23 –40°C to 85°C
LTC2366HS6#TRMPBF LTC2366HS6#TRPBF LTCXK 6-lead Plastic TSOT-23 –40°C to 125°C
LTC2365CTS8#TRMPBF LTC2365CTS8#TRPBF LTDCB 8-lead Plastic TSOT-23 0°C to 70°C
LTC2365ITS8#TRMPBF LTC2365ITS8#TRPBF LTDCB 8-lead Plastic TSOT-23 –40°C to 85°C
LTC2365HTS8#TRMPBF LTC2365HTS8#TRPBF LTDCB 8-lead Plastic TSOT-23 –40°C to 125°C
LTC2365CS6#TRMPBF LTC2365CS6#TRPBF LTDCC 6-lead Plastic TSOT-23 0°C to 70°C
LTC2365IS6#TRMPBF LTC2365IS6#TRPBF LTDCC 6-lead Plastic TSOT-23 –40°C to 85°C
LTC2365HS6#TRMPBF LTC2365HS6#TRPBF LTDCC 6-lead Plastic TSOT-23 –40°C to 125°C
TRM = 500 pieces. *Temperature grades are identifi ed by a label on the shipping container.
Consult LTC Marketing for information on lead based fi nish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifi cations, go to: http://www.linear.com/tapeandreel/
Power Dissipation ...............................................100mW
Operating Temperature Range
LTC2365C/LTC2366C .............................. 0°C to 70°C
LTC2365I/LTC2366I .............................–40°C to 85°C
LTC2365H/LTC2366H (Note 13) ........ –40°C to 125°C
Storage Temperature Range ..................–65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
VDD 1
VREF 2
GND 3
AIN 4
8CS
7 SCK
6 SDO
TOP VIEW
TS8 PACKAGE
8-LEAD PLASTIC TSOT-23
5 OVDD
TJMAX = 150°C, θJA = 250°C/W
VDD 1
GND 2
AIN 3
6CS
5 SDO
4 SCK
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
TJMAX = 150°C, θJA = 250°C/W
ORDER INFORMATION
PIN CONFIGURATION
LTC2365/LTC2366
3
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The l denotes the specifi cations which apply over the full operating
temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)
CONVERTER CHARACTERISTICS
PARAMETER CONDITIONS
LTC2365 LTC2366
UNITSMIN TYP MAX MIN TYP MAX
Resolution (No Missing Codes) l12 12 Bits
Integral Linearity Error (Note 5, 6) l±0.25 ±1 ±0.25 ±1 LSB
Differential Linearity Error (Note 6) l±0.25 ±1 ±0.25 ±1 LSB
Transition Noise (Note 7) 0.34 0.34 LSBRMS
Offset Error (Note 6) l2 ±3.5 2 ±3.5 LSB
Gain Error (Note 6) l1 ±2 1 ±2 LSB
Total Unadjusted Error S6 Package (Note 6)
TS8 Package (Note 6)
l
l
2
3
±3.5
±4.5
2
3
±3.5
±4.5
LSB
LSB
The l denotes the specifi cations which apply over the full operating temperature range, otherwise
specifi cations are at TA = 25°C. (Note 4)
ANALOG INPUTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Input Voltage S6 Package
TS8 Package
l
l
–0.05
–0.05
VDD + 0.05
VREF + 0.05
V
V
IIN Analog Input Leakage Current CS = High l±1 μA
CIN Analog Input Capacitance Between Conversions
During Conversions
20
4
pF
pF
VREF Reference Input Voltage TS8 Package l1.4 VDD + 0.05 V
IREF Reference Input Leakage Current TS8 Package l±1 μA
CREF Reference Input Capacitance TS8 Package 4 pF
tAP Sample-and-Hold Aperture Delay Time 1 ns
tJITTER Sample-and-Hold Aperture Delay Time Jitter 0.3 ns
DYNAMIC ACCURACY
The l denotes the specifi cations which apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS
LTC2365 LTC2366
UNITSMIN TYP MAX MIN TYP MAX
SINAD Signal-to-(Noise + Distortion) Ratio fIN = 1MHz l68 72 68 71 dB
SNR Signal-to-Noise Ratio fIN = 1MHz l70 73 69 72 dB
THD Total Harmonic Distortion fIN = 1MHz l–86 –72 –80 –72 dB
SFDR Spurious Free Dynamic Range fIN = 1MHz 87 82
IMD Intermodulation Distortion fIN1 = 0.97MHz, fIN2 = 1MHz for LTC2366
fIN1 = 97kHz, fIN2 = 100kHz for LTC2365 –76
–71.5 dB
Full-Power Bandwidth At 3dB
At 0.1dB
30
5
50
8
MHz
MHz
Full-Linear Bandwidth SINAD ≥ 68dB 2 2.5 MHz
LTC2365/LTC2366
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The l denotes the specifi cations which apply over the full
operating temperature range, otherwise specifi cations are at TA = 25°C. (Note 4)
DIGITAL INPUTS AND DIGITAL OUTPUTS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage 2.7V < VDD ≤ 3.6V
2.35V ≤ VDD ≤ 2.7V
l
l
2
1.7
V
V
VIL Low Level Input Voltage 2.7V < VDD ≤ 3.6V
2.35V ≤ VDD ≤ 2.7V
l
l
0.8
0.7
V
V
IIH High Level Input Current VIN = VDD l2.5 μA
IIL Low Level Input Current VIN = 0V l–2.5 μA
CIN Digital Input Capacitance 2pF
VOH High Level Output Voltage VDD = 2.35V to 3.6V, ISOURCE = 200μA lVDD – 0.2 V
VOL Low Level Output Voltage VDD = 2.35V to 3.6V, ISINK = 200μA l0.2 V
IOZ Hi-Z Output Leakage CS = VDD l±3 μA
COZ Hi-Z Output Capacitance CS = VDD 4pF
ISOURCE Output Source Current VOUT = 0V –10 mA
ISINK Output Sink Current VOUT = VDD 10 mA
POWER REQUIREMENT
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage l2.35 3.0 3.6 V
OVDD Digital Output Supply Voltage l1 3.6 V
IDD Supply Current, Static Mode
Operational Mode, LTC2366
Operational Mode, LTC2365
Sleep Mode
Sleep Mode
CS = 0V, SCK = 0V or VDD
fSMPL = 3Msps
fSMPL = 1Msps
–40°C to 85°C
85°C to 125°C
l
l
l
l
1
2.6
2
0.1
4
3.5
2
5
mA
mA
mA
μA
μA
PDPower Dissipation, Static Mode
Operational Mode, LTC2366
Operational Mode, LTC2365
Sleep Mode
Sleep Mode
CS = 0V, SCK = 0V or VDD
fSMPL = 3Msps
fSMPL = 1Msps
–40°C to 85°C
85°C to 125°C
l
l
l
l
7.8
6
0.3
3.6
14.4
12.6
7.2
18
mW
mW
mW
μW
μW
The l denotes the specifi cations which apply over the full operating temperature range,
otherwise specifi cations are at TA = 25°C. (Note 4)
LTC2365/LTC2366
5
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Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: When this pin, AIN, is taken below GND or above VDD, it will be
clamped by internal diodes. These products can handle input currents
greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = OVDD = VREF = 2.35V to 3.6V, fSMPL = fSMPL(MAX) and
fSCK = fSCK(MAX) unless otherwise specifi ed.
Note 5: Integral linearity is defi ned as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 6: Linearity, offset and gain specifi cations apply for a single-ended
AIN input with respect to GND.
Note 7: Typical RMS noise at code transitions.
Note 8: Guaranteed by characterization. All input signals are specifi ed with
tr = tf = 2ns (10% to 90% of VDD) and timed from a voltage level of 1.6V.
Note 9: All timing specifi cations given are with a 10pF capacitance load.
With a capacitance load greater than this value, a digital buffer or latch
must be used.
Note 10: Minimum fSCK at which specifi cations are guaranteed.
Note 11: The time required for the output to cross the VIH or VIL voltage.
Note 12: Guaranteed by design, not subject to test.
Note 13: High temperatures degrade operating lifetimes. Operating lifetime
is derated at temperatures greater than 105°C.
SYMBOL PARAMETER CONDITIONS
LTC2365 LTC2366
UNITSMIN TYP MAX MIN TYP MAX
fSMPL(MAX) Maximum Sampling Frequency (Notes 8, 9) l1 3 MHz
fSCK Shift Clock Frequency (Notes 8, 9, 10) l0.5 16 0.5 48 MHz
tSCK Shift Clock Period l62.5 2000 20.8 2000 ns
tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV l1000 333 ns
tACQ Acquisition Time l181.5 56 ns
tCONV Conversion Time l818.5 277 ns
tQUIET SDO Hi-Z State to CS↓(Notes 8, 9) l44 ns
t1Minimum Positive or Negative CS Pulse Width (Notes 8) l44 ns
t2SCK↓ Setup Time After CS↓ (Notes 8) l6 2000 6 2000 ns
t3SDO Enabled Time After CS↓ (Notes 9, 11, 12) l44ns
t4SDO Data Valid Access Time After SCK↓ (Notes 8, 9, 11) l15 15 ns
t5SCK Low Time l40% 40% tSCK
t6SCK High Time l40% 40% tSCK
t7SDO Data Valid Hold Time After SCK↓ (Notes 8, 9, 11) l55 ns
t8SDO Into Hi-Z State Time After SCK↓(Notes 9, 12) l5 30 5 14 ns
t9SDO Into Hi-Z State Time After CS↑(Notes 9, 12) l4.2 4.2 ns
tPOWER-UP Power-Up Time from Sleep Mode See Sleep Mode section l1000 333 ns
TIMING CHARACTERISTICS
The l denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at TA = 25°C. (Note 4)
LTC2365/LTC2366
6
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TA = 25°C, VDD = OVDD = VREF (LTC2365, Note 4)
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
Integral and Differential
Nonlinearity vs Supply Voltage
Histogram for 16384 Conversions SNR vs Input Frequency SINAD vs Input Frequency
THD vs Input Frequency THD vs Input Resistance 461kHz Sine Wave 8192 FFT Plot
OUTPUT CODE
0
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
1024 2048
23656 G01
–0.6
0.6
0.8
0.2
3072 4096
VDD = 3V
OUTPUT CODE
0
–1.0
DNL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
1024 2048
23656 G02
–0.6
0.6
0.8
0.2
3072 4096
VDD = 3V
SUPPLY VOLTAGE (V)
2.1
INL AND DNL (LSB)
0.2
0.6
1.0
3.3
23656 G03
–0.2
–0.6
0
0.4
0.8
–0.4
–0.8
–1.0 2.4 2.7 3.0 3.6
MIN DNL MAX DNL
MIN INL
MAX INL
CODE
2045
0
COUNT
2000
4000
6000
8000
10000
2046 2047 2048 2049
23656 G04
2050
VDD = 3V
INPUT FREQUENCY (kHz)
100
SNR (dB)
72.9
73.1
23656 G05
72.7
72.5 1000
73.5
73.3
VDD = 2.35V
VDD = 3.6V
VDD = 3V
INPUT FREQUENCY (kHz)
100
72.0
SINAD (dB)
72.2
72.4
72.6
72.8
73.0
73.2
1000
23656 G06
VDD = 2.35V
VDD = 3.6V
VDD = 3V
INPUT FREQUENCY (kHz)
100
–84
–83
–81
23656 G07
–85
–86
1000
–87
–88
–82
THD (dB)
VDD = 2.35V
VDD = 3.6V
VDD = 3V
RIN = 10Ω
fSMPL = 1Msps
INPUT RESISTANCE (Ω)
0
THD (dB)
–81
–80
100
23656 G08
–82
–83 25 50 75
–78
–79
VDD = 3V
fSMPL = 1Msps
fIN = 1MHz
INPUT FREQUENCY (kHz)
0
–40
–20
0
400
23656 G09
–60
–80
100 200 300 500
–100
–120
–140
MAGNITUDE (dB)
VDD = 3V
fSMPL = 1Msps
fIN = 461kHz
SINAD = 72.8dB
THD = –86.1dB
LTC2365/LTC2366
7
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TA = 25°C, VDD = OVDD = VREF (LTC2366, Note 4)
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity
vs Output Code
Differential Nonlinearity
vs Output Code
Integral and Differential
Nonlinearity vs Supply Voltage
Histogram for 16384 Conversions SNR vs Input Frequency SINAD vs Input Frequency
THD vs Input Frequency THD vs Input Resistance 1MHz Sine Wave 8192 FFT Plot
OUTPUT CODE
0
–1.0
INL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
1024 2048
23656 G10
–0.6
0.6
0.8
0.2
3072 4096
VDD = 3V
OUTPUT CODE
0
–1.0
DNL (LSB)
–0.8
–0.4
–0.2
0
1.0
0.4
1024 2048
23656 G11
–0.6
0.6
0.8
0.2
3072 4096
VDD = 3V
SUPPLY VOLTAGE (V)
2.1
INL AND DNL (LSB)
0.2
0.6
1.0
3.3
23656 G12
–0.2
–0.6
0
0.4
0.8
–0.4
–0.8
–1.0 2.4 2.7 3.0 3.6
MIN INL
MAX DNL
MIN DNL
MAX INL
CODE
2045
0
COUNT
2000
4000
6000
8000
10000
2046 2047 2048 2049
23656 G13
2050
VDD = 3V
INPUT FREQUENCY (kHz)
100
SNR (dB)
72.6
72.8
23656 G14
72.4
72.2 1000 1500
73.2
73.0
VDD = 2.35V
VDD = 3.6V
VDD = 3V
INPUT FREQUENCY (kHz)
100
70.0
SINAD (dB)
70.5
71.0
71.5
72.0
72.5
73.0
1000 1500
23656 G15
VDD = 2.35V
VDD = 3.6V
VDD = 3V
INPUT FREQUENCY (kHz)
100
THD (dB)
–80
–78
-76
1500
23656 G16
–82
–84
–88 1000
–86
–72
–74
VDD = 2.35V
VDD = 3.6V
VDD = 3V
RIN = 10Ω
fSMPL = 3Msps
INPUT RESISTANCE (Ω)
0
–70
–68
–64
75
23656 G17
–72
–74
25 50 100
–76
–78
–66
THD (dB)
VDD = 3V
fSMPL = 3Msps
fIN = 1.5MHz
INPUT FREQUENCY (kHz)
0
0
–20
–40
–60
–80
–100
–120
–140 750 1250
23656 G18
250 500 1000 1500
MAGNITUE (dB)
VDD = 3V
fSMPL = 3Msps
fIN = 994kHz
SINAD = 72dB
THD = –80.3dB
LTC2365/LTC2366
8
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TYPICAL PERFORMANCE CHARACTERISTICS
Supply Current vs SCK Frequency
Input Power Bandwidth
TA = 25°C, VDD = OVDD = VREF
(LTC2365/LTC2366, Note 4)
Reference Current vs SCK
Frequency (TS8 Package)
Integral and Differential
Nonlinearity vs Reference
Voltage (TS8 Package)
Integral and Differential
Nonlinearity vs Reference
Voltage (TS8 Package)
SCK FREQUENCY (MHz)
0
0
IDD (mA)
0.5
1.0
1.5
2.0
2.5
3.0
10 20 30 40
23656 G19
50
VDD = 2.35V
VDD = 3.6V
VDD = 3V
SCK FREQUENCY (MHz)
0
REFERENCE CURRENT (μA)
150
200
250
40
23656 G20
100
50
051015
20 25 30 35 45 50
VDD = 2.35V
VDD = 3.6V
VDD = 3V
16 SCKS PER CONVERSION
REFERENCE VOLTAGE (V)
0.6
NONLINEARITY ERROR (LSB)
0.2
0.6
1.0
3.0
23656 G21
–0.2
–0.6
0
0.4
0.8
–0.4
–0.8
–1.0 1.2 1.8 2.4 3.6
MIN DNL
MAX DNL
MIN INL
MAX INL
LTC2365, VDD = 3.6V
REFERENCE VOLTAGE (V)
0.6
NONLINEARITY ERROR (LSB)
0.2
0.6
1.0
3.0
23656 G22
–0.2
–0.6
0
0.4
0.8
–0.4
–0.8
–1.0 1.2 1.8 2.4 3.6
MIN DNL
MAX DNL
MIN INL
MAX INL
LTC2366, VDD = 3.6V
INPUT FREQUENCY (MHz)
1
–10
MAGNITUDE (dB)
–8
–6
–4
–2
0
2
10 100
23656 G23
VDD = 3V
LTC2366
LTC2365
LTC2365/LTC2366
9
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PIN FUNCTIONS
LTC2365/LTC2366 (S6 Package)
VDD (Pin 1): Positive Supply. The VDD range is 2.35V to
3.6V. VDD also defi nes the input span of the ADC, 0V to
VDD. Bypass to GND and to a solid ground plane with a
10μF ceramic capacitor (or 10μF tantalum in parallel with
0.1μF ceramic).
GND (Pin 2): Ground. The GND pin must be tied directly
to a solid ground plane.
AIN (Pin 3): Analog Input. AIN is a single-ended input with
respect to GND with a range from 0V to VDD.
SCK (Pin 4): Shift Clock Input. The SCK serial clock ad-
vances the conversion process. SDO data transitions on
the falling edge of SCK.
SDO (Pin 5): Three-State Serial Data Output. The A/D
conversion result is shifted out on SDO as a serial data
stream with MSB fi rst. The data stream consists of two
leading zeros followed by 12 bits of conversion data and
two trailing zeros.
CS (Pin 6): Chip Select Input. This active low signal starts
a conversion on the falling edge and frames the serial
data transfer.
LTC2365/LTC2366 (TS8 Package)
VDD (Pin 1): Positive Supply. The VDD range is 2.35V to
3.6V. Bypass to GND and to a solid ground plane with a
10μF ceramic capacitor (or 10μF tantalum in parallel with
0.1μF ceramic).
VREF (Pin 2): Reference Input. VREF defi nes the input
span of the ADC, 0V to VREF and the VREF range is 1.4V
to VDD. Bypass to GND and to a solid ground plane with
a 4.7μF ceramic capacitor (or 4.7μF tantalum in parallel
with 0.1μF ceramic).
GND (Pin 3): Ground. The GND pin must be tied directly
to a solid ground plane.
AIN (Pin 4): Analog Input. AIN is a single-ended input with
respect to GND with a range from 0V to VREF.
OVDD (Pin 5): Output Driver Supply for SDO. The OVDD
range is 1V to VDD. Bypass to GND and to a solid ground
plane with a 4.7μF ceramic capacitor (or 4.7μF tantalum
in parallel with 0.1μF ceramic).
SDO (Pin 6): Three-State Serial Data Output. The A/D
conversion result is shifted out on SDO as a serial data
stream with MSB fi rst. The data stream consists of two
leading zeros followed by 12 bits of conversion data and
two trailing zeros.
SCK (Pin 7): Shift Clock Input. The SCK serial clock ad-
vances the conversion process. SDO data transitions on
the falling edge of SCK.
CS (Pin 8): Chip Select Input. This active low signal starts
a conversion on the falling edge and frames the serial
data transfer.
LTC2365/LTC2366
10
23656fa
BLOCK DIAGRAM
Figure 1. SDO Into Hi-Z State After SCK Falling Edge
Figure 2. SDO Data Valid Hold Time After SCK Falling Edge
Figure 3. SDO Data Valid Access Time After SCK Falling Edge
23656 BD
–
+
4
1
2
S & H
VREF
3
GND
AIN
ANALOG
INPUT RANGE
OV TO VREF 12-BIT ADC
TS8 PACKAGE
10μF
6
7
8
TIMING
LOGIC
VDD
5
4.7μF
4.7μF
OVDD
SDO
SCK
THREE-
STATE
SERIAL
OUTPUT
PORT
CS
+
++
SCK 1.6V
SDO
23656 TD01
Hi-Z
t8
SCK
SDO
23656 TD02
VIH
VIL
1.6V
t7
SCK
SDO
23656 TD03
VOH
VOL
1.6V
t4
TIMING DIAGRAMS
LTC2365/LTC2366
11
23656fa
DC PERFORMANCE
The noise of an ADC can be evaluated in two ways: signal-
to-noise ratio (SNR) in the frequency domain and histogram
in the time domain. The LTC2365/LTC2366 excel in both.
Figures 5 and 6 demonstrate that the LTC2365/LTC2366
have an SNR of over 72dB. The noise in the time domain
histogram is the transition noise associated with a 12-bit
resolution ADC which can be measured with a fi xed DC signal
applied to the input of the ADC. The resulting output codes
are collected over a large number of conversions. The
shape of the distribution of codes will give an indication
of the magnitude of the transition noise. In Figure 4, the
distribution of output codes is shown for a DC input that
has been digitized 16384 times. The distribution is Gaus-
sian and the RMS code transition is about 0.34LSB. This
corresponds to a noise level of 72.7dB relative to a full
scale of 3V.
APPLICATIONS INFORMATION
DYNAMIC PERFORMANCE
The LTC2365/LTC2366 have excellent high speed sampling
capability. Fast fourier transform (FFT) test techniques are
used to test the ADC’s frequency response, distortion and
noise at the rated throughput. By applying a low distortion
sine wave and analyzing the digital output using an FFT
algorithm, the ADC’s spectral content can be examined for
frequencies outside the fundamental. Figures 5 and 6 show
typical LTC2365 and LTC2366 FFT plots respectively.
Figure 5. LTC2365 FFT Plot
Figure 4. Histogram for 16384 Conversions
Figure 6. LTC2366 FFT Plot
CODE
2045
0
COUNT
2000
4000
6000
8000
10000
2046 2047 2048 2049
23656 F04
2050
VDD = 3V
INPUT FREQUENCY (kHz)
0
–40
–20
0
400
23656 F05
–60
–80
100 200 300 500
–100
–120
–140
MAGNITUDE (dB)
VDD = 3V
fSMPL = 1Msps
fIN = 461kHz
SINAD = 72.8dB
THD = –86.1dB
INPUT FREQUENCY (kHz)
0
0
–20
–40
–60
–80
–100
–120
–140 750 1250
23656 F06
250 500 1000 1500
MAGNITUE (dB)
VDD = 3V
fSMPL = 3Msps
fIN = 994kHz
SINAD = 72dB
THD = –80.3dB
LTC2365/LTC2366
12
23656fa
Signal-to-Noise Plus Distortion Ratio
The signal-to-noise plus distortion ratio (SINAD) is the
ratio between the RMS amplitude of the fundamental input
frequency to the RMS amplitude of all other frequency
components at the A/D output. The output is band limited
to frequencies from above DC and below half the sampling
frequency. Figure 6 shows a typical FFT with a 3MHz sam-
pling rate and a 1MHz input. The dynamic performance
is excellent for input frequencies up to and beyond the
Nyquist frequency of 1.5MHz.
Effective Number of Bits
The effective number of bits (ENOB) is a measurement
of the resolution of an ADC and is directly related to
SINAD by the equation:
ENOB = (SINAD – 1.76)/6.02
where ENOB is the effective number of bits of resolu-
tion and SINAD is expressed in dB. At the maximum
sampling rate of 3MHz, the LTC2366 maintains ENOB
above 11 bits up to the Nyquist input frequency of 1.5MHz
(refer to Figure 7).
Total Harmonic Distortion
The total harmonic distortion (THD) is the ratio of the RMS
sum of all harmonics of the input signal to the fundamental
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD
is expressed as:
THD =20log V22+V32+V42+...Vn2
V1
where V1 is the RMS amplitude of the fundamental
frequency and V2 through Vn are the amplitudes of the
second through nth harmonics. THD versus Input Fre-
quency is shown in Figure 8. The LTC2366 has excellent
distortion performance up to the Nyquist frequency and
beyond.
Figure 8. LTC2366 Distortion vs Input Frequency
APPLICATIONS INFORMATION
Figure 7. LTC2366 ENOB and SINAD vs Input Frequency
INPUT FREQUENCY (kHz)
100
70.0
SINAD (dB)
ENOB
70.5
71.0
71.5
72.0
72.5
73.0
11.34
11.50
11.67
11.83
1000 1500
23656 F07
VDD = 2.35V
VDD = 3.6V
VDD = 3V
INPUT FREQUENCY (kHz)
100
THD (dB)
–80
–78
–76
1500
23656 F08
–82
–84
–88 1000
–86
–72
–74
VDD = 2.35V
VDD = 3.6V
VDD = 3V
RIN = 10Ω
LTC2365/LTC2366
13
23656fa
APPLICATIONS INFORMATION
Figure 9b. LTC2366 Intermodulation Distortion Plot
Intermodulation Distortion
If the ADC input signal consists of more than one spectral
component, the ADC transfer function nonlinearity can
produce intermoduation distortion (IMD) in addition to
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.
If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function
can create distortion products at the sum and difference
frequencies of mfa±nfb, where m and n = 0, 1, 2, 3, etc.
For example, the 2nd order IMD terms include (fa ± fb).
If the two input sine waves are equal in magnitude, the
value (in decibels) of the 2nd order IMD products can be
expressed by the following formula:
IMD(fa±fb)=20log Amplitude at (fa±fb)
Amplitude at fa
The LTC2365/LTC2366 have good IMD as shown in
Figure 9a and Figure 9b respectively.
Peak Harmonic or Spurious Noise
The peak harmonic or spurious noise is the largest spectral
component excluding the input signal and DC. This value
is expressed in decibels relative to the RMS value of a
full-scale input signal.
Full-Power and Full-Linear Bandwidth
The full-power bandwidth is that input frequency at which
the amplitude of reconstructed fundamental is reduced by
3dB for full-scale input signal.
The full-linear bandwidth is the input frequency at which
the SINAD has dropped to 68dB (11 effective bits). The
LTC2365/LTC2366 have been designed to optimize input
bandwidth, allowing the ADC to undersample input sig-
nals with frequencies above the converter’s Nyquist Fre-
quency. The noise fl oor stays very low at high frequencies;
SINAD becomes dominated by distortion at frequencies
far beyond Nyquist.
Figure 9a. LTC2365 Intermodulation Distortion Plot
INPUT FREQUENCY (kHz)
0
–140
MAGNITUDE (dB)
–120
–80
–60
–40
0
50 250 350
23656 F09a
–100
–20
200 450 500100 150 300 400
VDD = 3V
fSMPL = 1Msps
fb = 396kHz
fb = 424kHz
IMD = –73.5dB
INPUT FREQUENCY (kHz)
0
0
–20
–40
–60
–80
–100
–120
–140 750 1250
23656 F09b
250 500 1000 1500
MAGNITUE (dB)
VDD = 3V
fSMPL = 3Msps
fa = 935kHz
fb = 1.045kHz
IMD = –71.5dB
LTC2365/LTC2366
14
23656fa
Figure 10. LTC2365/LTC2366 Serial Interface Timing Diagram
APPLICATIONS INFORMATION
OVERVIEW
The LTC2365/LTC2366 use a successive approximation
algorithm and internal sample-and-hold circuit to convert an
analog signal to a 12-bit serial output. Both devices operate
from a single 2.35V to 3.6V supply. The LTC2366 samples
at a rate of 3Msps with a 48MHz clock while the LTC2365
samples at a rate of 1Msps with a 16MHz clock.
The LTC2365/LTC2366 contain a 12-bit, switched-capacitor
ADC, a sample-and-hold, and a serial interface (see Block
Diagram) and are available in tiny 6- and 8-lead TSOT-23
packages. The devices provide sleep mode control through
the serial interface to save power during inactive periods
(see the SLEEP MODE section).
The S6 package of the LTC2365/LTC2366 uses VDD as the
reference and has an analog input range of 0V to VDD. The
ADC samples the analog input with respect to GND and
outputs the result through the serial interface.
The TS8 package provides two additional pins: a reference
input pin, VREF, and an output supply pin, OVDD. The ADC
can operate with reduced spans down to 1.4V and achieve
342μV resolution. OVDD controls the output swing of the
digital output pin, SDO, and allows the device to com-
municate with 1.8V, 2.5V or 3V digital systems.
SERIAL INTERFACE
The LTC2365/LTC2366 communicate with microcontrollers,
DSPs and other external circuitry via a 3-wire interface.
Figure 10 shows the serial interface timing diagram, while
Figures 11 and 12 detail the timing diagrams of conversion
cycles in 14 and 16 SCK cycles respectively.
Data Transfer
A falling CS edge starts a conversion and frames the se-
rial data transfer. SCK provides the conversion clock and
controls the data transfer during the conversion.
CS going low clocks out the fi rst leading zero and sub-
sequent SCK falling edges clock out the remaining data,
beginning with the second leading zero. (Therefore, the
fi rst SCK falling edge captures the fi rst leading zero and
clocks out the second leading zero). The timing diagram
in Figure 12 shows that the fi nal bit in the data transfer is
valid on the 16th falling edge, since it is clocked out on
the previous 15th falling edge.
In applications with a slower SCK, it is possible to capture
data on each SCK rising edge. In such cases, the fi rst fall-
ing edge of SCK clocks out the second leading zero and
can be captured on the fi rst rising edge. However, the fi rst
leading zero clocked out when CS goes low is missed as
shown in Figures 11 and 12. In Figure 12, the 15th falling
edge of SCK clocks out the last bit and can be captured
on the 15th rising SCK edge.
If CS goes low while SCK is low, then CS clocks out the
fi rst leading zero and can be captured on the SCK rising
edge. The next SCK falling edge clocks out the second
leading zero and can be captured on the following rising
edge as shown in in Figure 10.
1SCK
SDO
t2
t3t4t7t5t8
ZERO ZERO B11 B10 B9 B1 B0 ZERO ZERO
234
(MSB) Hi-Z STATE
513141516
t6
tQUIET
tACQ
13tSCK
tTHROUGHPUT
tCONV
CS
t1
23656 F10
LTC2365/LTC2366
15
23656fa
Achieving 3Msps Sample Rate with LTC2366
CS going low places the sample-and-hold into hold mode
and starts a conversion. The LTC2365/LTC2366 require
at least 14 SCK cycles to fi nish the conversion. The
conversion terminates after the 13th falling SCK edge,
which clocks out B0. The 14th falling SCK edge places
the sample-and-hold back into sample mode.
Ignoring the last two trailing zeros, the user can bring CS
high after the 14th falling SCK edge. The user can also
keep the last two trailing zeros by bringing CS high right
after the 16th falling SCK. In both cases, a sample rate
of 3Msps can be achieved by using a 48MHz SCK clock
on the LTC2366, where tTHROUGHPUT is 333ns.
Serial Data Output (SDO)
The SDO output remains in the high impedance state while
CS is high. The falling edge of CS starts the conversion
and enables SDO. The A/D conversion result is shifted out
on the SDO pin as a serial data stream with the MSB fi rst.
The data stream consists of two leading zeros followed
by 12 bits of conversion data and two trailing zeros. The
SDO output returns to the high impedance state at the
16th falling edge of SCK or sooner by bringing CS high
before the 16th falling edge of SCK.
The output swing on the SDO pin is controlled by the VDD
pin voltage in the S6 package and by the OVDD pin voltage
in the TS8 package.
Figure 11. LTC2365/LTC2366 Serial Interface Timing Diagram for 14 SCK Cycles
Figure 12. LTC2365/LTC2366 Serial Interface Timing Diagram for 16 SCK Cycles
APPLICATIONS INFORMATION
1SCK
SDO
t2
t3t4t7t9
t5
Z ZERO B11 B10 B9 B1 B0
234
(MSB) Hi-Z STATE
51314
t6
tACQ
tQUIET
tTHROUGHPUT
tCONV
CS
t1
23656 F11
1SCK
SDO
t2
t3t4t7t8 OR t9
t5
234
(MSB) Hi-Z STATE
513141516
t6
tACQ
tQUIET
tTHROUGHPUT
tCONV
CS
t1
23656 F12
Z ZERO B11 B10 B9 B1 B0 ZERO ZERO
LTC2365/LTC2366
16
23656fa
APPLICATIONS INFORMATION
SLEEP MODE
The LTC2365/LTC2366 provide a sleep mode to conserve
power during inactive periods. Upon power-up, holding
CS high initializes the ADC to sleep mode. In sleep mode,
all bias circuitry is shut down and only leakage currents
remain (0.1μA typ).
Entering Sleep Mode
The ADC achieves the fastest sampling rate in operational
mode (full power-up). The device can also be put into sleep
mode for power savings during inactive periods. To force
the LTC2365/LTC2366 into sleep mode, the user can inter-
rupt the conversion process by bringing CS high between
the 2nd and 10th falling edges of SCK (see Figures 13 and
14). If CS is brought high after the 10th falling edge and
before the 16th falling edge, the device remains powered
up, but the conversion is terminated and SDO returns to
the high impedance state.
Figure 13. LTC2365/LTC2366 Operational Mode
Figure 14. LTC2365/LTC2366 Entering Sleep Mode
12 16141210
VALID DATA
23656 F13
SCK
SDO
CS
SCK
SDO
12 16141210
Hi-Z STATE
CS
23656 F14
LTC2365/LTC2366
17
23656fa
Figure 15. LTC2365/LTC2366 Exiting Sleep Mode
APPLICATIONS INFORMATION
Exiting Sleep Mode and Power-Up Time
To exit sleep mode, pull CS low and perform a dummy
conversion. The LTC2365/LTC2366 device power up com-
pletely after the 16th falling edge of SCK. After powering
up, the ADC can continuously acquire an input signal
and perform conversions as described in the SERIAL
INTERFACE section (see Figure 15). The wake-up time is
333ns for the LTC2366 with a 48MHz SCK and 1μs for the
LTC2365 with a 16MHz SCK.
The sample-and-hold is in hold mode while the device is in
sleep mode. The ADC returns to sample mode after the 1st
falling edge of SCK during power-up (see Figure 15).
POWER VERSUS SAMPLING RATE
Figure 16 shows the power consumption of the LTC2365/
LTC2366 in operational mode. By taking the ADC into sleep
mode when not performing a conversion, the average
power consumption of the ADC decreases as the sampling
rate decreases. Figure 17 shows the power consumption
versus sampling rate with the device in sleep mode when
not performing a conversion.
Figure 16. Power Consumption vs Sample Rate while
the Device Remains Powered Up Continuously
Figure 17. Power Consumption vs Sample Rate while the Device
Enters Sleep Mode when not Performing Conversions
12 16141210 1 2 16141210
INVALID DATA VALID DATA
23656 F15
SCK
SDO
CS
THE DEVICE BEGINS
TO POWER UP
THE DEVICE BEGINS
TO ACQUIRE INPUT
tPOWER-UP
THE DEVICE IS FULLY
POWERED UP AND READY
TO PERFORM CONVERSION
SAMPLE RATE (ksps)
0
3.0
POWER (mW)
3.5
4.5
5.0
5.5
2000
7.5
23656 F16
4.0
1000
500 2500
1500 3000
6.0
6.5
7.0
VDD = 3V
fSCK = VARIABLE
16 SCKS PER CONVERSION
SAMPLE RATE (ksps)
0
POWER (mW)
4
5
6
1000
23656 F17
3
2
0250 500 750
1
8
7
VDD = 3V
fSCK = 48MHz
LTC2365/LTC2366
18
23656fa
SINGLE-ENDED ANALOG INPUT
Driving the Analog Input
The analog input of the LTC2365/LTC2366 is easy to drive.
The input draws only one small current spike while charg-
ing the sample-and-hold capacitor at the end of conver-
sion. During the conversion, the analog input draws only
a small leakage current. If the source impedance of the
driving circuit is low, then the input of the LTC2365/LT2366
can be driven directly. As source impedance increases,
so will acquisition time. For minimum acquisition time
with high source impedance, a buffer amplifi er should be
used. The main requirement is that the amplifi er driving
the analog input must settle after the small current spike
before the next conversion starts (settling time must be
less than 56ns for full throughput rate). While choosing
an input amplifi er, also keep in mind the amount of noise
and harmonic distortion the amplifi er contributes.
Choosing an Input Amplifi er
Choosing an input amplifi er is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by amplifi er from charging the
sampling capacitor, choose an amplifi er that has a low
output impedance (<100Ω) at the closed-loop bandwidth
frequency. For example, if an amplifi er is used in a gain
of 1 and has a unitygain bandwidth of 50MHz, then the
output impedance at 50MHz must be less than 100Ω. The
second requirement is that the closed-loop bandwidth must
be greater than 40MHz to ensure adequate small signal
settling for full throughput rate. If slower op amps are
used, more time for settling can be provided by increas-
ing the time between conversions. The best choice for an
op amp to drive the LTC2365/LTC2366 will depend on the
application. Generally, applications fall into two categories:
AC applications where dynamic specifi cations are most
critical and time domain applications where DC accuracy
and settling time are most critical. The following list is a
summary of the op amps that are suitable for driving the
LTC2365/LTC2366. (More detailed information is available
on the Linear Technology website at www.linear.com.)
APPLICATIONS INFORMATION
LTC2365/LTC2366
19
23656fa
APPLICATIONS INFORMATION
Figure 18. RC Input Filter
LTC1566-1: Low Noise 2.3MHz Continuous Time Lowpass
Filter.
LT
®
1630: Dual 30MHz Rail-to-Rail Voltage Feedback Ampli-
fi er. 2.7V to ±15V supplies. Very high AVOL, 500μV offset
and 520ns settling to 0.5LSB for a 4V swing. THD and noise
are –93dB to 40kHz and below 1LSB to 320kHz (AV = 1,
2VP-P into 1k, VS = 5V), making the part excellent for AC
applications (to 1/3 Nyquist) where rail-to-rail performance
is desired. Quad version is available as LT1631.
LT1632: Dual 45MHz Rail-to-Rail Voltage Feedback Ampli-
fi er. 2.7V to ±15V supplies. Very high AVOL, 1.5mV offset
and 400ns settling to 0.5LSB for a 4V swing. It is suitable
for applications with a single 5V supply. THD and noise
are –93dB to 40kHz and below 1LSB to 800kHz (AV = 1,
2VP-P into 1k, VS = 5V), making the part excellent for AC
applications where rail-to-rail performance is desired.
Quad version is available as LT1633.
LT1813: Dual 100MHz 750V/μs 3mA Voltage Feedback
Amplifi er. 5V to ±5V supplies. Distortion is –86dB to
100kHz and –77dB to 1MHz with ±5V supplies (2VP-P
into 500). Excellent part for fast AC applications with ±5V
supplies.
LT1801: 180MHz GBWP, –75dBc at 500kHz, 2mA/Ampli-
fi er, 8.5nV/√Hz.
LT1806/LT1807: 325MHz GBWP, –80dBc Distortion at
5MHz, Unity-Gain Stable, R-R In and Out, 10mA/Ampli-
fi er, 3.5nV/√Hz.
LT1810: 180MHz GBWP, –90dBc Distortion at 5MHz,
Unity-Gain Stable, R-R In and Out, 15mA/Amplifi er,
16nV/√Hz.
LT1818/LT1819: 400MHz, 2500V/μs, 9mA, Single/Dual
Voltage Mode Operational Amplifi er.
LT6200: 165MHz GBWP, –85dBc Distortion at 1MHz,
Unity-Gain Stable, R-R In and Out, 15mA/Amplifi er,
0.95nV/√Hz.
LT6203: 100MHz GBWP, –80dBc Distortion at 1MHz,
Unity-Gain Stable, R-R In and Out, 3mA/Amplifier,
1.9nV√Hz.
Input Filtering and Source Impedance
The noise and the distortion of the input amplifi er and other
circuitry must be considered since they will add to the
LTC2365/LTC2366 noise and distortion. The small-signal
bandwidth of the sample-and-hold circuit is 50MHz. Any
noise or distortion products that are present at the analog
inputs will be summed over this entire bandwidth. Noisy
input circuitry should be fi ltered prior to the analog inputs
to minimize noise. A simple 1-pole RC fi lter is suffi cient for
many applications. For example, Figure 18 shows a 47pF
capacitor from AIN to ground and a 51Ω source resistor to
limit the input bandwidth to 47MHz. The 47pF capacitor also
acts as a charge reservoir for the input sample-and-hold
and isolates the ADC input from sampling-glitch sensitive
circuitry. High quality capacitors and resistors should be
used since these components can add distortion. NPO
and silvermica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self heating and from damage that may
occur during soldering. Metal fi lm surface mount resistors
are much less susceptible to both problems. When high
amplitude unwanted signals are close in frequency to the
desired signal frequency, a multiple pole fi lter is required.
High external source resistance, combined with the 20pF of
input capacitance, will reduce the rated 50MHz bandwidth
and increase acquisition time beyond 56ns.
VDD
GND
LTC2366
23656 F18
10μF
47pF
51Ω
6
5
4
1
2
3
CS
SD0
SCK
AIN
LTC2365/LTC2366
20
23656fa
APPLICATIONS INFORMATION
Reference Input
On the TS8 package of the LTC2365/LTC2366, the voltage
on the VREF pin defi nes the full-scale range of the ADC. The
reference voltage can range from VDD down to 1.4V.
Input Range
The analog input of the LTC2365/LTC2366 is driven single-
ended with respect to GND from a single supply. The input
may swing up to VDD for the S6 package and to VREF for
the TS8 package. The 0V to 2.5V range is also ideally
suited for single-ended input use with VDD or VREF = 2.5V
for single supply applications. If the difference between
the AIN input and GND exceeds VDD for the S6 package or
VREF for the TS8 package, the output code will stay fi xed
at all ones, and if this difference goes below 0V, the output
code will stay fi xed at all zeros.
Figure 19 shows the ideal input/output characteristics for
the LTC2365/LTC2366. The code transitions occur mid-
way between successive integer LSB values (i.e. 0.5LSB,
1.5LSB, 2.5LSB, …, FS –1.5LSB). The output code is
straight binary with 1LSB = VDD/4096 for the S6 package
and 1LSB = VREF/4096 for the TS8 package.
BOARD LAYOUT AND BYPASSING
Wire wrap boards are not recommended for high resolu-
tion and/or high speed A/D converters. To obtain the best
performance from the LTC2365/LTC2366, a printed circuit
board with ground plane is required. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC. The analog
input should be screened by the ground plane.
Figure 19. LTC2365/LTC2366 Transfer Characteristics
INPUT VOLTAGE (V)
UNIPOLAR OUTPUT CODE
23656 F19
111...111
111...110
000...000
000...001
FS – 1LSB1LSB0
LTC2365/LTC2366
21
23656fa
Figure 20. Power Supply Ground Practice
High quality tantalum and ceramic bypass capacitors
should be used at the VDD and VREF pins as shown in the
Typical Application circuit on the fi rst page of this data
sheet. For optimum performance, a 10μF surface mount
AVX capacitor with a 0.1μF ceramic is recommended for
the VDD pin and a 4.7μF surface mount AVX capacitor
with a 0.1μF ceramic is recommended for the VREF and
OVDD pins. Alternatively, 4.7μF and 10μF ceramic chip
capacitors such as Murata GRM235Y5V106Z016 may
be used. The capacitors must be located as close to the
pins as possible. The traces connecting the pins and the
bypass capacitors must be kept short and should be made
as wide as possible.
APPLICATIONS INFORMATION
Figure 20 shows the recommended system ground con-
nections. All analog circuitry grounds should be terminated
at the LTC2365/LTC2366. The ground return from the
LTC2365/LTC2366 to the power supply should be low
impedance for noise free operation. Digital circuitry grounds
must be connected to the digital supply common.
In applications where the ADC data outputs and control sig-
nals are connected to a continuously active microprocessor
bus, it is possible to get errors in the conversion results.
These errors are due to feedthrough from the micropro-
cessor to the successive approximation comparator. The
problem can be eliminated by forcing the microprocessor
into a Wait state during conversion or by using three-state
buffers to isolate the ADC data bus.
23656 F20
GND
AIN
VDD
CAIN
CS
SDO
SCK
CVDD
PIN 1
VIAS TO GROUND PLANE
+
10μF
LTC2365/LTC2366
22
23656fa
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) S6 TSOT-23 0302 REV B
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
PACKAGE DESCRIPTION
LTC2365/LTC2366
23
23656fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
PACKAGE DESCRIPTION
TS8 Package
8-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1637)
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.22 – 0.36
8 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3) TS8 TSOT-23 0802
2.90 BSC
(NOTE 4)
0.65 BSC
1.95 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
3.85 MAX
0.52
MAX
0.65
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
LTC2365/LTC2366
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2008
LT 0809 REV A • PRINTED IN USA
PART NUMBER DESCRIPTION COMMENTS
ADCs
LTC1402 12-Bit, 2.2Msps Serial ADC 5V or ±5V Supply, 4.096V or ±2.5V Span
LTC1403/LTC1403A 12-/14-Bit, 2.8Msps Serial Sampling ADC 3V, Differential Input, 12mW, MSOP Package
LTC1407/LTC1407A 12-/14-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, 14mW, MSOP Package
LTC1860 12-Bit, 250ksps Serial ADC 5V Supply, 1-Channel, 4.3mW, MSOP-8 Package
LTC1860L 12-Bit, 150ksps Serial ADC 3V Supply, 1-Channel, 1.3mW, MSOP-8 Package
LTC1861 12-Bit, 250ksps Serial ADC 5V Supply, 2-Channel, 4.3mW, MSOP-8 Package
LTC1861L 12-Bit, 150ksps Serial ADC 3V Supply, 2-Channel, 1.3mW, MSOP-8 Package
LTC1863 12-Bit, 200ksps Serial ADC 8-Channel ADC 5V Supply, 6.5mW, SSOP-16 Package, Pin Compatible to LTC1863L, LTC1867
LTC1863L 12-Bit, 250ksps Serial ADC 8-Channel ADC 5V Supply, 2.2mW, SSOP-16 Package, Pin Compatible to LTC1863, LTC1867L
LTC1864/LTC1865 16-Bit, 250ksps Serial ADC 5V Supply, 1 and 2 Channel, 4.3mW, MSOP Package
LTC1867 16-Bit, 200ksps Serial ADC 8-Channel ADC 5V Supply, 6.5mW, SSOP-16 Package, Pin Compatible to LTC1863, LTC1867L
LTC1867L 16-Bit, 175ksps Serial ADC 8-Channel ADC 3V Supply, 2.2mW, SSOP-16 Package, Pin Compatible to LTC1863L, LTC1867
LTC2355/LTC2356 12-/14-Bit, 3.5Msps Serial ADC 3.3V Supply, Differential Input, 18mW, MSOP Package
LTC2360/LTC2361/LTC2362 12-Bit, 100/250/500ksps Serial ADC in TSOT 3V Supply, Pin and Software Compatible to LTC2365/LTC2366
DACs
LTC1592 16-Bit, Serial SoftSpan™ IOUT DAC ±1LSB INL/DNL, Software Selectable Spans
LTC1666/LTC1667/LTC1668 12-/14-/16-Bit, 50Msps DACs 87dB SFDR, 20ns Settling Time
LTC2630 12-/10-/8-Bit Single VOUT DACs SC70 6-Pin Package, Internal Reference, ±1LSB INL (12 Bits)
References
LT1460-2.5 Micropower Series Voltage Reference 0.1% Initial Accuracy, 10ppm Drift
LT1461-2.5 Precision Voltage Reference 0.05% Initial Accuracy, 3ppm Drift
LT1790-2.5 Micropower Series Reference in SOT-23 0.05% Initial Accuracy, 10ppm Drift
LT6660 Ultra-Tiny Micropower Series Reference 2mm × 2mm DFN Package, 0.2% Initial Accuracy, 10ppm Drift
SoftSpan is a trademark of Linear Technology Corporation.
TYPICAL APPLICATION
Low Jitter Clock Timing with RF Sine Generator Using Clock
Squaring/Level Shifting Circuit and Re-Timing Flip-Flop
PRE
VCC
1k
1k50Ω
VCC
NL17SZ74 CONVERT ENABLE
NC7SVU04P5X
MASTER CLOCK
0.1μF
CONV
LTC2366
CONTROL
LOGIC
(FPGA, CPLD,
DSP, ETC.)
DQ
Q
CONV
SCK
SDO
100Ω
NC7SVU04P5X
CLR
2365/2366 TA02
RELATED PARTS
