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MB9B560L Series
32-Bit Arm
®
Cortex
®
-M4F
FM4 Microcontroller
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 002-04922 Rev .*B Revised December 15, 2017
Devices in the MB9B560L Series are highly integrated 32-bit microc ontrollers with high perf ormance and com petitive co st.
This series is based on the Arm® Cortex®-M4F Processor with on-chip Flash memory and SRAM. The series has peripheral
functions suc h as Motor Control Timers, ADCs and Communicat ion Interfaces (USB, CAN, UART, CSIO, I2C, LIN).
The products that are described in this datasheet are placed into TYPE2-M4 product categories in the "FM4 Family Peripheral
Manual Main Par t (002-04856)”.
Features
32-bit Arm® Cortex®-M4F Core
Processor version: r0p1
Up to 160 MHz Frequency Operation
FPU built-in
Support DSP instruction
Memory Protection Unit (MPU): i m proves the reliability of an
embedded system
Integrated Nested Vectored Interrupt Controller (NVIC ): 1
NMI (non-mask able interrupt) and 128 perip heral interrupts
and 16 priority levels
24-bit System timer (Sys Tick): System timer for OS task
management
On-Chip Memories
[Flash Memory]
These series are based on two independent on-chip Flash
memories.
MainFlash memory
Up to 512 Kbytes
Built-in Flash Accelerator System with 16 Kbytes trace
buffer memory
The read access to Flash memory can be achieved without
wait-cycle up to operation frequency of 72 MHz . Even at
the operatio n frequency more than 72 MHz, an equivalent
access to Flash memory can be obtained by Flash
Accelerator System.
Security function for code protection
WorkFlash memory
32 Kbytes
Read cycle:
• 6wait-cycle: the operation frequency more than 120 MHz,
and up to 160 MHz
• 4wait-cycle: the operation frequency more than 72 MHz,
and up to 120 MHz
• 2wait-cycle: the operation frequency more than 40 MHz,
and up to 72 MHz
• 0wait-cycle: the operation frequency up to 40 MHz
Security function is shared with code protection
[SRAM]
This is compos ed of three independent SRA Ms (SRAM0,
SRAM1, and SRAM2). SRAM0 is connected to I-code bus and
D-code bus of Cortex-M4F core. SRAM1 and SRAM2 are
connected to System bus of Cortex-M4F cor e.
SRAM0: Up to 32 Kbytes
SRAM1: Up to 16 Kbytes
SRAM2: Up to 16 Kbytes
USB Interface
USB interface is composed of Device and Host.
USB device
USB2.0 Full-Speed support ed
Max 6 Endpoint supported
• Endpoint 0 is control transfer
• Endpoint 1, 2 can be s elected Bulk-transfer,
Interrupt-t r ansfer or Is oc hronous-transfer
• Endpoint 3 to 5 c an s el ec t Bulk-transfer or
Interrupt-transfer
• Endpoint 1 to 5 c om prise Double Buffer
The size of each endpoint is according to the follows.
• Endpoint 0, 2 to 5: 64 bytes
• Endpoint 1: 256 bytes
USB host
USB2.0 Full/Low-speed supported
Bulk-transfer, interrupt-transfer and Isochronous-transfer
support
USB Device connected/dis-connected automatically detect
IN/OUT token handshake packet aut om atically
Max 256-byte packet-length supported
Wake-up function support ed
CAN Interface (1 Channel)
Compatible with CAN Speci fication 2.0A/B
Maximum transfer rate: 1 Mbps
Built-in 32 message buffer
Document Number: 002-04922 Rev .*B Page 2 of 128
MB9B560L Series
Multi-Function Serial Interface (Max 6 Channels)
64 bytes with FIFO (t he FIFO step numbers are variable
depending on the settings of the communic ation mode or bit
length.)
Operation mode is selec table from the followings for each
channel.
UART
CSIO
LIN
I2C
UART
Full-duplex double buffer
Selection with or without parit y supported
Built-in dedicated baud rate generator
External clock available as a serial clock
Hardware Flow control : Automatically control the
transmission by CTS/RTS (only ch.4)
Various error detect func tions available (parity errors,
framing errors, and overrun errors)
CSIO
Full-duplex double buffer
Built-in dedicated baud rate generator
Overrun error detect function available
Serial chip select function (ch.6 only)
Supports high-speed SPI (ch.0 and ch.6 only)
Data length 5 to 16-bit
LIN
LIN protocol Rev.2.1 supp orted
Full-duplex double buffer
Master/Slave mode supp or ted
LIN break field generation (can change to 13 to 16-bit
length)
LIN break delimiter generation (can change to 1 to 4-bit
length)
Various error detect func tions available (parity errors,
framing error s, and overru n errors)
I2C
Standard mode (Max 100 kbps) / Fast-mode (Max 400
kbps) supported
Fast mode Plus (Fm+) (Max 1000 kbps, only for ch.3=ch.A
and ch.4=ch.B) supported
DMA Controll er (8 Channels)
DMA Controller has an independent bus for CPU, so CPU and
DMA Controller can pr ocess simultaneously.
8 independently configured and op er ated channel s
Transfer can be started by software or request from the
built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand
transfer
Transfer data type: bytes/half-word/word
Transfer block count: 1 to 16
Number of transfers : 1 to 65536
DSTC (Descri ptor Sy stem data Transfer Controller)
(128 Channels)
The DSTC can transfer data at high-speed without going v ia
the CPU. The DSTC adopts the Descri ptor system a nd,
following t he s pecified contents of the Descriptor whic h has
already been constructed o n the memory, ca n ac cess directly
the memory /peripheral devi ce and perform s the data trans fer
operation.
It supports the software activati on, the hardware activation and
the chain activation functions.
A/D Converter (Max 15 Channels)
[12-bit A/D Converter]
Successive Approximation type
Built-in 2 units
Conversion time: 0.5 μs @ 5 V
Priority conver s i on available (priorit y at 2levels)
Scanning conversion mode
Built-in FIFO for conversion data storage (for SC A N
conversion: 16steps, for Priority conversion: 4s teps)
DA Converter (Max 2 Channels)
R-2R type
12-bit resolution
Base T imer (Max 8 Channels)
Operation mode is selectable from the foll owings for eac h
channel.
16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
General Purpose I/O Port
This series c an use its pins as general purpose I/O ports when
they are not used for external bus or peripherals. Moreover , the
port relocate function is b uilt in. It can set which I/O port the
peripheral function can b e allocated.
Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 48 high-speed general-pur pose I/O ports @ 64 pin
Package
Some pin is 5 V tolerant I/O.
See 4. Pin Description and 5. I/O Circuit Type f or the
corresponding pins.
Document Number: 002-04922 Rev .*B Page 3 of 128
MB9B560L Series
Multi-Function T imer (Max 2 Units)
The Multi-f unc tion timer is composed of the following blocks.
Minimum resolution: 6.25 ns
16-bit free-run timer × 3 ch./unit
Input capture × 4 ch./unit
Output compare × 6 ch./unit
A/D activation compare × 6 ch./unit
Waveform generator × 3 ch./unit
16-bit PPG timer × 3 ch./unit
The following function can be used to achieve the motor
control.
PWM signal output function
DC chopper waveform output function
Dead time function
Input capture functi on
A/D convertor acti v ate function
DTIF (Motor emergency stop) interrupt funct i on
Real-Time Clock (RTC)
The Real-time clock can count
Year/Month/Day/Ho ur /Minute/S ec ond/A day of the week from
00 to 99.
Interrupt functi on with specifying date and ti me
(Year/Month/Da y/H our/Minute ) is available. This function is
also available by specifying only Year, Month, Day, Hour or
Minute.
Timer interrupt function after set t i me or each set ti m e.
Capable of rewriti ng the time with c ontinuing the time count.
Leap year automatic count is available.
Quadrature Position/Revolution Counter (QPRC) (1
Channel)
The Quadratur e P osition/Revolution Count er (QPRC) is used
to measure the position of the position enc oder. Moreover, it is
possible to us e up/down cou nter.
The detection edge of the three external event inp ut pins AIN,
BIN, and ZIN is configur able.
16-bit position counter
16-bit revolution c ounter
Two 16-bit compare regis ters
Dual Timer (32-/16-bit Down Counter)
The Dual Timer consists of two programmab le 32-/16-bit down
counters.
Operation mode is selectable from the foll owings for eac h
channel.
Free-running
Periodic (=Reload)
One-shot
Watch Counter
The Watch counter is used for wake up f r om the lo w-power
consumption mode. It is poss ible to select the main clock, sub
clock, built-in high-speed C R clock or built-in low-speed CR
clock as the clock source.
Interval timer: up to 64 s (Max) @ Sub Clock: 32.768 kHz
External Interrupt Control l er Unit
External interrupt input pin: Max 16 pins
Include one non-maskable interrupt (NMI)
Watchdog Timer (2 Channels)
A watch dog timer can ge nerate interrupts or a reset when a
time-out value i s reached.
This series consists of two different watchdogs, a "Hardware"
watchdog and a "Software" watchdog.
"Hardware" watchdog timer is clocked b y low-speed internal
CR oscillator . Therefore, "Hardware" watchdog is active in any
power saving m ode except STOP.
CRC (Cyclic Redundan cy Check) Accelerator
The CRC accel erator helps a verify data transmission or
storage integri ty.
CCITT CRC16 and IEEE-8 02.3 CRC32 are supported.
CCITT CRC16 Generator Polynomial: 0 x1021
IEEE-802.3 CRC32 Generat or Polynomial: 0x04C11DB7
Document Number: 002-04922 Rev .*B Page 4 of 128
MB9B560L Series
Clock and Reset
[Clocks]
Five clock sources (2 external oscillators, 2 internal CR
oscillator, and Main PLL) that are dynamic ally select able.
Main clock: 4 MHz to 48 MHz
Sub Clock: 32.768 kHz
High-speed interna l C R C lock: 4 MHz
Low-speed internal CR Clock: 100 kHz
Main PLL Clock
[Resets]
Reset requests from INITX pin
Power on reset
Software reset
Watchdog timers r eset
Low voltage detector reset
Clock supervisor reset
Clock Super Visor (CSV)
Clocks gener ated by internal CR oscillators are used t o
supervise abnormality of the external clocks.
External OSC clock failure (cl oc k stop) is det ec ted, reset is
asserted.
External OSC frequency anomaly is detected, int errupt or
reset is asserted.
Low-Voltage Detector (LVD)
This Series include 2-stage monitoring of voltage on the V CC
pins. When the voltage falls below the voltage has been set,
Low-Vo ltage Detector generates an interrupt or reset.
LVD1: error reporting via int er rupt
LVD2: auto-res et operation
Low-Power Consumption Mode
Six low-power cons umption modes are suppor ted.
SLEEP
TIMER
RTC
STOP
Deep standby RTC (selectabl e from with/ without RAM
retention)
Deep standby stop (selectable from with/without RAM
retention)
VBAT
The consumption power duri ng the RTC operation ca n be
reduced by supplying the po wer supply independent fr om the
RTC (calendar circuit)/32 kHz oscillatio n c ir c uit. The following
circuits can a l so be used.
RTC
32 kHz oscillation circuit
Power-on circuit
Back up register: 32 bytes
Port circuit
Debug
Serial Wire JTAG Debug Port (SWJ-DP)
Unique ID
Unique value of the device (41-bit) is set.
Power Supply
Three Power Supplies ( when 64 pin Packag e)
Two Power Supplies (when 4 8 pin Package)
Wide range voltage:
VCC = 2.7 V to 5.5 V
Power supply for USB I/O:
USBVCC = 3.0 V to 3.6 V (when USB is used)
= 2.7 V to 5.5 V (when GPIO is used)
Power supply for VBAT (only 64 pin Packag e):
VBAT = 2.7 V to 5. 5 V
Document Number: 002-04922 Rev .*B Page 5 of 128
MB9B560L Series
Contents
Features ................................................................................................................................................................................... 1
1. Product Lineup .................................................................................................................................................................. 7
2. Packages ........................................................................................................................................................................... 8
3. Pin Assignment ................................................................................................................................................................. 9
4. Pin Description ................................................................................................................................................................ 13
4.1 List of P i n Numbers ..................................................................................................................................................... 13
4.2 List of P i n Functions .................................................................................................................................................... 19
5. I/O Circuit Type ............................................................................................................................................................... 28
6. Handling Precautions ..................................................................................................................................................... 35
6.1 Precautions for Pr oduct Design ................................................................................................................................... 35
6.2 Precautions for Pac k age Mounting .............................................................................................................................. 36
6.3 Precautions for Use Environment ................................................................................................................................ 37
7. Handling Devices ............................................................................................................................................................ 38
8. Block Diag ram ................................................................................................................................................................. 41
9. Memory Size .................................................................................................................................................................... 42
10. Memory Map .................................................................................................................................................................... 42
11. Pin Status in Each CPU State ........................................................................................................................................ 45
12. Electrical Characteri st ics ............................................................................................................................................... 52
12.1 Absolute Maximum Rat i ngs ......................................................................................................................................... 52
12.2 Recommended Operat i ng Conditions ......................................................................................................................... 53
12.3 DC Charac teristics ...................................................................................................................................................... 57
12.3.1 Current Rating .............................................................................................................................................................. 57
12.3.2 Pin Characteristics ....................................................................................................................................................... 64
12.4 AC Characteristic s ....................................................................................................................................................... 66
12.4.1 Main Clock Input Characteristics .................................................................................................................................. 66
12.4.2 Sub Clock Input Characteris tics ................................................................................................................................... 67
12.4.3 Built-in CR Oscillation Char acteristic s .......................................................................................................................... 67
12.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL) ...................................... 68
12.4.5 Operating Conditions of USB PLL (In the Case of Using Mai n Cl oc k for Input C lock of PLL) ...................................... 68
12.4.6 Operating Conditions of Main PLL (In t he C ase of Using Built-in High-Speed CR Clock for Input Clock of Main PLL) 68
12.4.7 Reset Input Characteristics .......................................................................................................................................... 69
12.4.8 Power-on Reset Timing ................................................................................................................................................ 69
12.4.9 GPIO Output Charac te risti c s ........................................................................................................................................ 70
12.4.10 Base Timer Input Timing ........................................................................................................................................... 71
12.4.11 CSIO/UART Timing .................................................................................................................................................. 72
12.4.12 External Input Timing ................................................................................................................................................ 97
12.4.13 Quadrature Position/Revolution Counter Timing ...................................................................................................... 98
12.4.14 I2C Timing ............................................................................................................................................................... 100
12.4.15 JTAG Timing ........................................................................................................................................................... 102
12.5 12-bit A /D Converter .................................................................................................................................................. 103
12.6 12-bit D/A Converter .................................................................................................................................................. 106
12.7 USB Characteristics .................................................................................................................................................. 107
12.8 Low-Voltage Detect i on Charact eristics ...................................................................................................................... 111
12.8.1 Low-Voltag e Detection Res et ..................................................................................................................................... 111
12.8.2 Interrupt of Low-Voltage Detection ............................................................................................................................. 111
12.9 MainFlash Memory Write/Erase Characteristics ........................................................................................................ 112
12.10 WorkFlash Memory Write/Erase Characteristics ....................................................................................................... 112
Document Number: 002-04922 Rev .*B Page 6 of 128
MB9B560L Series
12.11 Standby Recovery Ti m e ............................................................................................................................................ 113
12.11.1 Recovery Cause: Interrupt/W K U P .......................................................................................................................... 113
12.11.2 Recovery Cause: Res et .......................................................................................................................................... 115
13. Ordering Information .................................................................................................................................................... 117
14. Package Dimensions .................................................................................................................................................... 118
15. Major Changes .............................................................................................................................................................. 123
Document History ............................................................................................................................................................... 125
Sales, Solutions, and Legal Inf or mation ........................................................................................................................... 128
Document Number: 002-04922 Rev .*B Page 7 of 128
MB9B560L Series
1. Product Lineup
Memory Size
Product Name
MB9BF564K/L
MB9BF565K/L
MB9BF566K/L
MainFlash memory
256 Kbytes
384 Kbytes
512 Kbytes
WorkFlash memory
32 Kbytes
32 Kbytes
32 Kbytes
On-chip SRAM
32 Kbytes
48 Kbytes
64 Kbytes
SRAM0
16 Kbytes
24 Kbytes
32 Kbytes
SRAM1
8 Kbytes
12 Kbytes
16 Kbytes
SRAM1
8 Kbytes
12 Kbytes
16 Kbytes
Function
Product Name MB9BF564K
MB9BF565K
MB9BF566K
MB9BF564L
MB9BF565L
MB9BF566L
Pin count
48
64
CPU
Cortex-M4F, MPU, NVIC 128ch.
Freq.
160 MHz
Power supply voltage range
2.7 V to 5.5 V
USB2.0 (Device/Host)
1ch.
CAN
1ch.
DMAC
8ch.
DSTC
128ch.
Multi-function Serial Interface
(UART/CSIO/LIN/I
2
C)
6ch. (Max)
(In ch.1, only I
2
C is available.)
6ch. (Max)
Base Timer
(PWC/Reload timer/PWM/PPG)
8ch. (Max)
MF T imer
A/D activation compare
6ch.
1 unit 2 units (Max)
Input capture
4ch.
Free-run timer
3ch.
Output compare
6ch.
Waveform generator
3ch.
PPG
3ch.
QPRC
1ch.
Dual T imer
1 unit
Real-Time Clock
1 unit
Watch Counter
1 unit
CRC Accelerator
Yes
Watchdog Timer
1ch. (SW) + 1ch. (HW)
External Interrupts
15 pins (Max) + NMI × 1
16 pins (Max) + NMI × 1
I/O Ports
33 pins (Max)
48 pins (Max)
12-bit A/D Converter 8ch. (2 units) 15ch. (2 units)
12-bit D/A Converter 2 units (Max)
CSV (Clock Super Visor)
Yes
LVD (Low-Voltage Detector)
2ch.
Built-in CR
High-speed
4 MHz
Low-speed
100 kHz
Debug Function
SWJ-DP
Unique ID
Yes
Note:
− All signals of the peripheral function in each product c annot be allocated by limiting the pins of pac k age.
It is necessary to use the port relocate funct i on of the I/O port according to your function use.
− See “12. Electrical Characteristics 12.4. AC Characteristics 12.4.3. Internal CR Oscillation Characteristics” for accuracy of
built-in CR.
−
Document Number: 002-04922 Rev .*B Page 8 of 128
MB9B560L Series
2. Packages
Product Name
Package
MB9BF564K
MB9BF565K
MB9BF566K
MB9BF564L
MB9BF565L
MB9BF566L
LQFP: LQG064 (0.65mm pitch)
-
LQFP: LQD064 (0.5mm pitch)
-
LQFP: LQA048 (0.5mm pitch)
-
QFN: VNC064 (0.5mm pitch)
-
QFN: VNA048 (0.5mm pitch)
-
: Supported
Note:
− See 14. Package Dimensions for detailed information on each package.
Document Number: 002-04922 Rev .*B Page 9 of 128
MB9B560L Series
3. Pin Assignment
LQD064/LQG064
(TOP VIEW)
Note:
− The number after the underscor e ("_") in pin names such as XX X_1 and XXX_2 indicates the r el oc ated port number. For
these pins, t here are multi ple pins that provide the same f unction for the s ame channel. Use the extended port function
register (EPFR) to select t he pin.
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/SCK1_1/NMIX/WKUP0/IC01_2
P61/AN14/ADTG_5/SOT1_1/INT15_1/UHCONX0/IC00_2
P62/AN13/SIN1_1/RX0_0/TIOB3_1/INT14_1
P63/AN12/SIN0_1/TX0_0/TIOA3_1/INT13_1/ADTG_4
P64/AN11/SOT0_1/TIOB2_1/INT12_1
P65/AN10/SCK0_1/TIOA2_1/INT11_1/RTCCO_0/SUBOUT_0
P66/AN09/INT10_1/IC13_0/CROUT_1
P00/TRSTX
P01/TCK/SWCLK
P02/TDI
P03/TMS/SWDIO
P04/TDO/SWO
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VCC 148 P26/AN08/SIN1_0/INT09_1/IC12_0
P50/AIN0_0/INT00_0/TIOA0_0/CTS4_0 247 P25/AN07/SOT1_0/INT08_1/IC11_0/CROUT_0
P51/BIN0_0/INT01_0/TIOB0_0/RTS4_0 346 P24/AN06/SCK1_0/INT07_1/IC10_0
P52/IC00_0/ZIN0_0/INT02_0/TIOA1_0/SIN4_0 445 P23/AN05/SCK0_0/TIOB1_1/INT06_1/DTTI1X_0
P53/IC01_0/INT03_0/TIOB1_0/SOT4_0 544 P22/AN04/SOT0_0/TIOA1_1/INT05_1/FRCK1_0
P54/IC02_0/INT04_0/TIOA2_0/SCK4_0 643 P21/AN03/ADTG_3/SIN0_0/TIOB0_1/INT04_1/RTO15_0
P55/IC03_0/INT05_0/TIOB2_0/SIN3_0 742 AVRH
P56/FRCK0_0/INT06_0/TIOA3_0/SOT3_0 841 AVRL
P57/DTTI0X_0/INT07_0/TIOB3_0/SCK3_0/ADTG_0 940 AVSS
P30/RTO00_0/AIN0_1/INT08_0/TIOA4_0/SIN2_0 10 39 AVCC
P31/RTO01_0/BIN0_1/INT09_0/TIOB4_0/SOT2_0 11 38 P20/AN02/SIN6_0/TIOA0_1/INT03_1/RTO14_0/RTCCO_1/SUBOUT_1/WKUP1
P32/RTO02_0/ZIN0_1/INT10_0/TIOA5_0/SCK2_0 12 37 P13/AN01/SOT6_0/TIOB7_1/RTO13_0/IC00_1/TX0_1
P33/RTO03_0/INT11_0/TIOB5_0/SIN4_1 13 36 P12/AN00/SCK6_0/TIOA7_1/INT02_1/ZIN0_2/RTO12_0/IC01_1/RX0_1
P34/RTO04_0/INT12_0/TIOA6_0/SOT4_1 14 35 P11/DA1/ADTG_2/SCS6_0/TIOB4_1/INT01_1/BIN0_2/RTO11_0/IC02_1
P35/WKUP2/RTO05_0/INT13_0/TIOB6_0/SCK4_1 15 34 P10/DA0/TIOA4_1/INT00_1/AIN0_2/RTO10_0/IC03_1
VSS 16 33 VCC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P46/X0A
P47/X1A
VBAT
P48/VREGCTL
P49/VWAKEUP
INITX
C
VSS
VCC
P40/TIOA7_0/INT14_0
P41/TIOB7_0/INT15_0/ADTG_1/WKUP3
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP -64
Document Number: 002-04922 Rev .*B Page 10 of 128
MB9B560L Series
VNC064
(TOP VIEW)
Note:
− The number after the underscor e ("_") in pin names such as XX X_1 and XXX_2 indicates the r el oc ated port number. For
these pins, t here are multi ple pins that provide the same f unction for the s ame channel. Use the extended port function
register (EPF R) to select the pin.
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/SCK1_1/NMIX/WKUP0/IC01_2
P61/AN14/ADTG_5/SOT1_1/INT15_1/UHCONX0/IC00_2
P62/AN13/SIN1_1/RX0_0/TIOB3_1/INT14_1
P63/AN12/SIN0_1/TX0_0/TIOA3_1/INT13_1/ADTG_4
P64/AN11/SOT0_1/TIOB2_1/INT12_1
P65/AN10/SCK0_1/TIOA2_1/INT11_1/RTCCO_0/SUBOUT_0
P66/AN09/INT10_1/IC13_0/CROUT_1
P00/TRSTX
P01/TCK/SWCLK
P02/TDI
P03/TMS/SWDIO
P04/TDO/SWO
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
VCC 148 P26/AN08/SIN1_0/INT09_1/IC12_0
P50/AIN0_0/INT00_0/TIOA0_0/CTS4_0 247 P25/AN07/SOT1_0/INT08_1/IC11_0/CROUT_0
P51/BIN0_0/INT01_0/TIOB0_0/RTS4_0 346 P24/AN06/SCK1_0/INT07_1/IC10_0
P52/IC00_0/ZIN0_0/INT02_0/TIOA1_0/SIN4_0 445 P23/AN05/SCK0_0/TIOB1_1/INT06_1/DTTI1X_0
P53/IC01_0/INT03_0/TIOB1_0/SOT4_0 544 P22/AN04/SOT0_0/TIOA1_1/INT05_1/FRCK1_0
P54/IC02_0/INT04_0/TIOA2_0/SCK4_0 643 P21/AN03/ADTG_3/SIN0_0/TIOB0_1/INT04_1/RTO15_0
P55/IC03_0/INT05_0/TIOB2_0/SIN3_0 742 AVRH
P56/FRCK0_0/INT06_0/TIOA3_0/SOT3_0 841 AVRL
P57/DTTI0X_0/INT07_0/TIOB3_0/SCK3_0/ADTG_0 940 AVSS
P30/RTO00_0/AIN0_1/INT08_0/TIOA4_0/SIN2_0 10 39 AVCC
P31/RTO01_0/BIN0_1/INT09_0/TIOB4_0/SOT2_0 11 38 P20/AN02/SIN6_0/TIOA0_1/INT03_1/RTO14_0/RTCCO_1/SUBOUT_1/WKUP1
P32/RTO02_0/ZIN0_1/INT10_0/TIOA5_0/SCK2_0 12 37 P13/AN01/SOT6_0/TIOB7_1/RTO13_0/IC00_1/TX0_1
P33/RTO03_0/INT11_0/TIOB5_0/SIN4_1 13 36 P12/AN00/SCK6_0/TIOA7_1/INT02_1/ZIN0_2/RTO12_0/IC01_1/RX0_1
P34/RTO04_0/INT12_0/TIOA6_0/SOT4_1 14 35 P11/DA1/ADTG_2/SCS6_0/TIOB4_1/INT01_1/BIN0_2/RTO11_0/IC02_1
P35/WKUP2/RTO05_0/INT13_0/TIOB6_0/SCK4_1 15 34 P10/DA0/TIOA4_1/INT00_1/AIN0_2/RTO10_0/IC03_1
VSS 16 33 VCC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P46/X0A
P47/X1A
VBAT
P48/VREGCTL
P49/VWAKEUP
INITX
C
VSS
VCC
P40/TIOA7_0/INT14_0
P41/TIOB7_0/INT15_0/ADTG_1/WKUP3
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
QFN -64
Document Number: 002-04922 Rev .*B Page 11 of 128
MB9B560L Series
LQA048
(TOP VIEW)
Note:
− The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number. For these
pins, there are multiple pins that provide the same func tion for the same channel. Us e the extended port function register
(EPFR) to select the pin.
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/SCK1_1/NMIX/WKUP0/IC01_2
P61/AN14/ADTG_5/SOT1_1/INT15_1/UHCONX0/IC00_2
P66/AN09/INT10_1/CROUT_1
P00/TRSTX
P01/TCK/SWCLK
P02/TDI
P03/TMS/SWDIO
P04/TDO/SWO
48
47
46
45
44
43
42
41
40
39
38
37
VCC 136 P23/AN05/SCK0_0/TIOB1_1/INT06_1
P54/IC02_0/INT04_0/TIOA2_0 235 P22/AN04/SOT0_0/TIOA1_1/INT05_1
P55/IC03_0/INT05_0/TIOB2_0/SIN3_0 334 P21/AN03/ADTG_3/SIN0_0/TIOB0_1/INT04_1
P56/FRCK0_0/INT06_0/TIOA3_0/SOT3_0 433 AVRH
P57/DTTI0X_0/INT07_0/TIOB3_0/SCK3_0/ADTG_0 532 AVRL
P30/RTO00_0/AIN0_1/INT08_0/TIOA4_0/SIN2_0 631 AVSS
P31/RTO01_0/BIN0_1/INT09_0/TIOB4_0/SOT2_0 730 AVCC
P32/RTO02_0/ZIN0_1/INT10_0/TIOA5_0/SCK2_0 829 P20/AN02/SIN6_0/TIOA0_1/INT03_1/RTCCO_1/SUBOUT_1/WKUP1
P33/RTO03_0/INT11_0/TIOB5_0/SIN4_1 928 P13/AN01/SOT6_0/TIOB7_1/IC00_1/TX0_1
P34/RTO04_0/INT12_0/TIOA6_0/SOT4_1 10 27 P12/AN00/SCK6_0/TIOA7_1/INT02_1/ZIN0_2/IC01_1/RX0_1
P35/WKUP2/RTO05_0/INT13_0/TIOB6_0/SCK4_1 11 26 P11/DA1/ADTG_2/SCS6_0/TIOB4_1/INT01_1/BIN0_2/IC02_1
VSS 12 25 P10/DA0/TIOA4_1/INIT00_1/AIN0_2/IC03_1
13
14
15
16
17
18
19
20
21
22
23
24
P46/X0A
P47/X1A
VCC
INITX
C
VSS
VCC
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP -48
Document Number: 002-04922 Rev .*B Page 12 of 128
MB9B560L Series
VNA048
(TOP VIEW)
Note:
− The number after the underscor e ("_") in pin names such as XX X_1 and XXX_2 indicates the r el oc ated port number. For
these pins, t here are multi ple pins that provide the same f unction for the s ame channel. Use the extended port function
register (EPF R) to select the pin.
VSS
P81/UDP0
P80/UDM0
USBVCC
P60/SCK1_1/NMIX/WKUP0/IC01_2
P61/AN14/ADTG_5/SOT1_1/INT15_1/UHCONX0/IC00_2
P66/AN09/INT10_1/CROUT_1
P00/TRSTX
P01/TCK/SWCLK
P02/TDI
P03/TMS/SWDIO
P04/TDO/SWO
48
47
46
45
44
43
42
41
40
39
38
37
VCC 136 P23/AN05/SCK0_0/TIOB1_1/INT06_1
P54/IC02_0/INT04_0/TIOA2_0 235 P22/AN04/SOT0_0/TIOA1_1/INT05_1
P55/IC03_0/INT05_0/TIOB2_0/SIN3_0 334 P21/AN03/ADTG_3/SIN0_0/TIOB0_1/INT04_1
P56/FRCK0_0/INT06_0/TIOA3_0/SOT3_0 433 AVRH
P57/DTTI0X_0/INT07_0/TIOB3_0/SCK3_0/ADTG_0 532 AVRL
P30/RTO00_0/AIN0_1/INT08_0/TIOA4_0/SIN2_0 631 AVSS
P31/RTO01_0/BIN0_1/INT09_0/TIOB4_0/SOT2_0 730 AVCC
P32/RTO02_0/ZIN0_1/INT10_0/TIOA5_0/SCK2_0 829 P20/AN02/SIN6_0/TIOA0_1/INT03_1/RTCCO_1/SUBOUT_1/WKUP1
P33/RTO03_0/INT11_0/TIOB5_0/SIN4_1 928 P13/AN01/SOT6_0/TIOB7_1/IC00_1/TX0_1
P34/RTO04_0/INT12_0/TIOA6_0/SOT4_1 10 27 P12/AN00/SCK6_0/TIOA7_1/INT02_1/ZIN0_2/IC01_1/RX0_1
P35/WKUP2/RTO05_0/INT13_0/TIOB6_0/SCK4_1 11 26 P11/DA1/ADTG_2/SCS6_0/TIOB4_1/INT01_1/BIN0_2/IC02_1
VSS 12 25 P10/DA0/TIOA4_1/INIT00_1/AIN0_2/IC03_1
13
14
15
16
17
18
19
20
21
22
23
24
P46/X0A
P47/X1A
VCC
INITX
C
VSS
VCC
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
QFN -48
Document Number: 002-04922 Rev .*B Page 13 of 128
MB9B560L Series
4. Pin Description
4.1 List of Pin Numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number . For these pins,
there are mult iple pins that provide the same function for the same channel. Use the extended port function regist er (EPFR) to
select the pin.
Pin No
Pin Name I/O Circuit
Type Pin State
Type
LQFP64
QFN64
LQFP48
QFN48
1
1
VCC
-
-
2 -
P50
E K
AIN0_0
INT00_0
TIOA0_0
CTS4_0
3 -
P51
E K
BIN0_0
INT01_0
TIOB0_0
RTS4_0
4 -
P52
I K
IC00_0
ZIN0_0
INT02_0
TIOA1_0
SIN4_0
5 -
P53
N K
IC01_0
INT03_0
TIOB1_0
SOT4_0
(SDA4_0)
6 2
P54
N K
IC02_0
INT04_0
TIOA2_0
-
SCK4_0
(SCL4_0)
7 3
P55
I K
IC03_0
INT05_0
TIOB2_0
SIN3_0
8 4
P56
N K
FRCK0_0
INT06_0
TIOA3_0
SOT3_0
(SDA3_0)
Document Number: 002-04922 Rev .*B Page 14 of 128
MB9B560L Series
Pin No
Pin Name I/O Circuit
Type Pin State
Type
LQFP64
QFN64
LQFP48
QFN48
9 5
P57
N K
DTTI0X_0
INT07_0
TIOB3_0
SCK3_0
(SCL3_0)
ADTG_0
10 6
P30
G K
RTO00_0
AIN0_1
INT08_0
TIOA4_0
SIN2_0
11 7
P31
G K
RTO01_0
BIN0_1
INT09_0
TIOB4_0
SOT2_0
(SDA2_0)
12 8
P32
G K
RTO02_0
ZIN0_1
INT10_0
TIOA5_0
SCK2_0
(SCL2_0)
13 9
P33
G K
RTO03_0
INT11_0
TIOB5_0
SIN4_1
14 10
P34
G K
RTO04_0
INT12_0
TIOA6_0
SOT4_1
(SDA4_1)
15 11
P35
G Q
WKUP2
RTO05_0
INT13_0
TIOB6_0
SCK4_1
(SCL4_1)
Document Number: 002-04922 Rev .*B Page 15 of 128
MB9B560L Series
Pin No
Pin Name I/O Circuit
Type Pin State
Type
LQFP64
QFN64
LQFP48
QFN48
16
12
VSS
-
-
17 13
P46
P S
X0A
18 14
P47
Q T
X1A
19
-
VBAT
-
-
-
15
VCC
-
-
20 -
P48
O U
VREGCTL
21 -
P49
O U
VWAKEUP
22
16
INITX
B
C
23
17
C
-
-
24
18
VSS
-
-
25
19
VCC
-
-
26 -
P40
E K
TIOA7_0
INT14_0
27 -
P41
E Q
TIOB7_0
INT15_0
ADTG_1
WKUP3
28 20
PE0
C E
MD1
29
21
MD0
J
D
30 22
PE2
A A
X0
31 23
PE3
A B
X1
32
24
VSS
-
-
33
-
VCC
-
-
34 25
P10
R J
DA0
TIOA4_1
INT00_1
AIN0_2
IC03_1
-
RTO10_0
35 26
P11
R J
DA1
ADTG_2
SCS6_0
TIOB4_1
INT01_1
BIN0_2
IC02_1
-
RTO11_0
Document Number: 002-04922 Rev .*B Page 16 of 128
MB9B560L Series
Pin No
Pin Name I/O Circuit
Type Pin State
Type
LQFP64
QFN64
LQFP48
QFN48
36 27
P12
M M
AN00
SCK6_0
TIOA7_1
INT02_1
ZIN0_2
IC01_1
RX0_1
-
RTO12_0
37 28
P13
M L
AN01
SOT6_0
(SDA6_0)
TIOB7_1
IC00_1
TX0_1
-
RTO13_0
38 29
P20
F O
AN02
SIN6_0
TIOA0_1
INT03_1
RTCCO_1
SUBOUT_1
WKUP1
-
RTO14_0
39
30
AVCC
-
-
40
31
AVSS
-
-
41
32
AVRL
-
-
42
33
AVRH
-
-
43 34
P21
F M
AN03
ADTG_3
SIN0_0
TIOB0_1
INT04_1
-
RTO15_0
44 35
P22
F M
AN04
SOT0_0
(SDA0_0)
TIOA1_1
INT05_1
-
FRCK1_0
45 36
P23
F M
AN05
SCK0_0
(SCL0_0)
TIOB1_1
INT06_1
-
DTTI1X_0
Document Number: 002-04922 Rev .*B Page 17 of 128
MB9B560L Series
Pin No
Pin Name I/O Circuit
Type Pin State
Type
LQFP64
QFN64
LQFP48
QFN48
46 -
P24
F M
AN06
SCK1_0
(SCL1_0)
INT07_1
IC10_0
47 -
P25
F M
AN07
SOT1_0
(SDA1_0)
INT08_1
IC11_0
CROUT_0
48 -
P26
F M
AN08
SIN1_0
INT09_1
IC12_0
49 37
P04
E G
TDO
SWO
50 38
P03
E G
TMS
SWDIO
51 39
P02
E G
TDI
52 40
P01
E G
TCK
SWCLK
53 41
P00
E G
TRSTX
54 42
P66
F M
AN09
INT10_1
CROUT_1
-
IC13_0
55 -
P65
L M
AN10
SCK0_1
(SCL0_1)
TIOA2_1
INT11_1
RTCCO_0
SUBOUT_0
56 -
P64
L M
AN11
SOT0_1
(SDA0_1)
TIOB2_1
INT12_1
Document Number: 002-04922 Rev .*B Page 18 of 128
MB9B560L Series
Pin No
Pin Name I/O Circuit
Type Pin State
Type
LQFP64
QFN64
LQFP48
QFN48
57 -
P63
F M
AN12
SIN0_1
TX0_0
TIOA3_1
INT13_1
ADTG_4
58 -
P62
F M
AN13
SIN1_1
RX0_0
TIOB3_1
INT14_1
59 43
P61
F M
AN14
ADTG_5
SOT1_1
(SDA1_1)
INT15_1
UHCONX0
IC00_2
60 44
P60
I F
SCK1_1
(SCK1_1)
NMIX
WKUP0
IC01_2
61
45
USBVCC
-
-
62 46
P80
H R
UDM0
63 47
P81
H R
UDP0
64
48
VSS
-
-
Document Number: 002-04922 Rev .*B Page 19 of 128
MB9B560L Series
4.2 List of Pin Functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated port number . For these pins,
there are mult iple pins that provide the same function for the same channel. Use the extended port function regist er (EPFR) to
select the pin.
Pin
Function Pin Name Function Description
Pin No
LQFP64
QFN64
LQFP48
QFN48
ADC
ADTG_0
A/D converter external trigger input pin
9
5
ADTG_1
27
-
ADTG_2
35
26
ADTG_3
43
34
ADTG_4
57
-
ADTG_5
59
43
AN00
A/D converter analog input pin.
ANxx describes ADC ch.xx.
36
27
AN01
37
28
AN02
38
29
AN03
43
34
AN04
44
35
AN05
45
36
AN06
46
-
AN07
47
-
AN08
48
-
AN09
54
42
AN10
55
-
AN11
56
-
AN12
57
-
AN13
58
-
AN14
59
43
Base Timer
0
TIOA0_0
Base timer ch.0 TIOA pin
2
-
TIOA0_1
38
29
TIOB0_0
Base timer ch.0 TIOB pin
3
-
TIOB0_1
43
34
Base Timer
1
TIOA1_0
Base timer ch.1 TIOA pin
4
-
TIOA1_1
44
35
TIOB1_0
Base timer ch.1 TIOB pin
5
-
TIOB1_1
45
36
Base Timer
2
TIOA2_0
Base timer ch.2 TIOA pin
6
2
TIOA2_1
55
-
TIOB2_0
Base timer ch.2 TIOB pin
7
3
TIOB2_1
56
-
Base Timer
3
TIOA3_0
Base timer ch.3 TIOA pin
8
4
TIOA3_1
57
-
TIOB3_0
Base timer ch.3 TIOB pin
9
5
TIOB3_1
58
-
Base Timer
4
TIOA4_0
Base timer ch.4 TIOA pin
10
6
TIOA4_1
34
25
TIOB4_0
Base timer ch.4 TIOB pin
11
7
TIOB4_1
35
26
Base Timer
5
TIOA5_0
Base timer ch.5 TIOA pin
12
8
TIOB5_0
Base timer ch.5 TIOB pin
13
9
Document Number: 002-04922 Rev .*B Page 20 of 128
MB9B560L Series
Pin
Function Pin Name Function Description
Pin No
LQFP64
QFN64
LQFP48
QFN48
Base Timer
6
TIOA6_0
Base timer ch.6 TIOA pin
14
10
TIOB6_0
Base timer ch.6 TIOB pin
15
11
Base Timer
7
TIOA7_0
Base timer ch.7 TIOA pin
26
-
TIOA7_1
36
27
TIOB7_0
Base timer ch.7 TIOB pin
27
-
TIOB7_1
37
28
CAN 0
TX0_0
CAN interface ch.0 TX output pin
57
-
TX0_1
37
28
RX0_0
CAN interface ch.0 RX output pin
58
-
RX0_1
36
27
Debugger
SWCLK
Serial wire debug interface clock input pin
52
40
SWDIO
Serial wire debug interface data input / output pin
50
38
SWO
Serial wire viewer output pin
49
37
TCK
JTAG test clock input pin
52
40
TDI
JTAG test data input pin
51
39
TDO
JTAG debug data output pin
49
37
TMS
JTAG test mode state input/output pin
50
38
TRSTX
JTAG test reset Input pin
53
41
External
Interrupt
INT00_0
External interrupt request 00 input pin
2
-
INT00_1
34
25
INT01_0
External interrupt request 01 input pin
3
-
INT01_1
35
26
INT02_0
External interrupt request 02 input pin
4
-
INT02_1
36
27
INT03_0
External interrupt request 03 input pin
5
-
INT03_1
38
29
INT04_0
External interrupt request 04 input pin
6
2
INT04_1
43
34
INT05_0
External interrupt request 05 input pin
7
3
INT05_1
44
35
Document Number: 002-04922 Rev .*B Page 21 of 128
MB9B560L Series
Pin
Function Pin Name Function Description
Pin No
LQFP64
QFN64
LQFP48
QFN48
External
Interrupt
INT06_0
External interrupt request 06 input pin
8
4
INT06_1
45
36
INT07_0
External interrupt request 07 input pin
9
5
INT07_1
46
-
INT08_0
External interrupt request 08 input pin
10
6
INT08_1
47
-
INT09_0
External interrupt request 09 input pin
11
7
INT09_1
48
-
INT10_0
External interrupt request 10 input pin
12
8
INT10_1
54
42
INT11_0
External interrupt request 11 i nput pin
13
9
INT11_1
55
-
INT12_0
External interrupt request 12 input pin
14
10
INT12_1
56
-
INT13_0
External interrupt request 13 input pin
15
11
INT13_1
57
-
INT14_0
External interrupt request 14 input pin
26
-
INT14_1
58
-
INT15_0
External interrupt request 15 input pin
27
-
INT15_1
59
43
NMIX
Non-Maskable Interrupt input pin
60
44
GPIO
P00
General-purpose I/O port 0
53
41
P01
52
40
P02
51
39
P03
50
38
P04
49
37
P10
General-purpose I/O port 1
34
25
P11
35
26
P12
36
27
P13
37
28
P20
General-purpose I/O port 2
38
29
P21
43
34
P22
44
35
P23
45
36
P24
46
-
P25
47
-
P26
48
-
P30
General-purpose I/O port 3
10
6
P31
11
7
P32
12
8
P33
13
9
P34
14
10
P35
15
11
Document Number: 002-04922 Rev .*B Page 22 of 128
MB9B560L Series
Pin
Function Pin Name Function Description
Pin No
LQFP64
QFN64
LQFP48
QFN48
GPIO
P40
General-purpose I/O port 4
26
-
P41
27
-
P46
17
13
P47
18
14
P48
20
-
P49
21
-
P50
General-purpose I/O port 5
2
-
P51
3
-
P52
4
-
P53
5
-
P54
6
2
P55
7
3
P56
8
4
P57
9
5
P60
General-purpose I/O port 6
60
44
P61
59
43
P62
58
-
P63
57
-
P64
56
-
P65
55
-
P66
54
42
P80
General-purpose I/O port 8
62
46
P81
63
47
PE0
General-purpose I/O port E
28
20
PE2
30
22
PE3
31
23
Document Number: 002-04922 Rev .*B Page 23 of 128
MB9B560L Series
Pin
Function Pin Name Function Description
Pin No
LQFP64
QFN64
LQFP48
QFN48
Multi-
function
Serial
0
SIN0_0 Multi-function serial interface ch.0 input pin 43 34
SIN0_1
57
-
SOT0_0
(SDA0_0) Multi-function serial interface ch.0 output pin.
This pin operates as SOT0 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as SDA0
when it is used in an I2C (operation mode 4).
44 35
SOT0_1
(SDA0_1) 56 -
SCK0_0
(SCL0_0) Multi-function serial interface ch.0 clock I/O pin.
This pin operates as SCK0 when it is used in a CSIO
(operation modes 2) and as SCL0 when it is used in an I2C
(operation mode 4).
45 36
SCK0_1
(SCL0_1) 55 -
Multi-
function
Serial
1
SIN1_0
Multi-function serial interface ch.1 input pin
48
-
SIN1_1
58
-
SOT1_0
(SDA1_0) Multi-function serial interface ch.1 output pin.
This pin operates as SOT1 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as SDA1
when it is used in an I2C (operation mode 4).
47 -
SOT1_1
(SDA1_1) 59 43
SCK1_0
(SCL1_0) Multi-function serial interface ch.1 clock I/O pin.
This pin operates as SCK1 when it is used in a CSIO
(operation modes 2) and as SCL1 when it is used in an I2C
(operation mode 4).
46 -
SCK1_1
(SCL1_1) 60 44
Multi-
function
Serial
2
SIN2_0 Multi-function serial interface ch.2 input pin 10 6
SOT2_0
(SDA2_0)
Multi-function serial interface ch.2 output pin.
This pin operates as SOT2 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as SDA2
when it is used in an I
2
C (operation mode 4).
11 7
SCK2_0
(SCL2_0)
Multi-function serial interface ch.2 clock I/O pin.
This pin operates as SCK2 when it is used in a CSIO
(operation modes 2) and as SCL2 when it is used in an I2C
(operation mode 4).
12 8
Document Number: 002-04922 Rev .*B Page 24 of 128
MB9B560L Series
Pin Function
Pin Name Function Description
Pin No
LQFP64
QFN64
LQFP48
QFN48
Multi-
function
Serial
3
SIN3_0
Multi-function serial interface ch.3 input pin
7
3
SOT3_0
(SDA3_0)
Multi-function serial interface ch.3 output pin.
This pin operates as SOT3 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as SDA3
when it is used in an I
2
C (operation mode 4).
8 4
SCK3_0
(SCL3_0)
Multi-function serial interface ch.3 clock I/O pin.
This pin operates as SCK3 when it is used in a CSIO
(operation modes 2) and as SCL3 when it is used in an I2C
(operation mode 4).
9 5
Multi-
function
Serial
4
SIN4_0
Multi-function serial interface ch.4 input pin
4
-
SIN4_1 13 9
SOT4_0
(SDA4_0)
Multi-function serial interface ch.4 output pin.
This pin operates as SOT4 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as SDA4
when it is used in an I
2
C (operation mode 4).
5 -
SOT4_1
(SDA4_1)
14 10
SCK4_0
(SCL4_0)
Multi-function serial interface ch.4 clock I/O pin.
This pin operates as SCK4 when it is used in a CSIO
(operation modes 2) and as SCL4 when it is used in an I2C
(operation mode 4).
6 -
SCK4_1
(SCL4_1)
15 11
CTS4_0
Multi-function serial interface ch.4 CTS input pin
2
-
RTS4_0
Multi-function serial interface ch.4 RTS output pin
3
-
Multi-
function
Serial
6
SIN6_0
Multi-function serial interface ch.6 input pin
38
29
SOT6_0
(SDA6_0)
This pin operates as SOT6 when it is used in a
UART/CSIO/LIN (operation modes 0 to 3) and as SDA6
when it is used in an I
2
C (operation mode 4).
37 28
SCK6_0
(SCL6_0)
Multi-function serial interface ch.6 clock I/O pin.
This pin operates as SCK6 when it is used in a CSIO
(operation modes 2) and as SCL6 when it is used in an I2C
(operation mode 4).
36 27
SCS6_0
Multi-function serial interface ch.6 serial chip select pin
35
26
Document Number: 002-04922 Rev .*B Page 25 of 128
MB9B560L Series
Pin Function
Pin Name Function Description
Pin No
LQFP64
QFN64
LQFP48
QFN48
Multi-
function
Timer
0
DTTI0X_0 Input signal controlling wave form generator outputs
RTO00 to RTO05 of Multi-function timer 0. 9 5
FRCK0_0 16-bit free-run timer ch.0 external clock input pin 8 4
IC00_0
16-bit input capture ch.0 input pin of Multi-function timer 0.
ICxx describes channel number.
4
-
IC00_1 37 28
IC00_2 59 43
IC01_0 5 -
IC01_1 36 27
IC01_2 60 44
IC02_0 6 2
IC02_1
35
26
IC03_0 7 3
IC03_1 34 25
RTO00_0
(PPG00_0)
Wave form generator output pin of Multi-function timer 0.
This pin operates as PPG00 when it is used in PPG0 output
modes.
10 6
RTO01_0
(PPG00_0)
Wave form generator output pin of Multi-function timer 0.
This pin operates as PPG00 when it is used in PPG0 output
modes.
11 7
RTO02_0
(PPG02_0)
Wave form generator output pin of Multi-function timer 0.
This pin operates as PPG02 when it is used in PPG0 output
modes.
12 8
RTO03_0
(PPG02_0)
Wave form generator output pin of Multi-function timer 0.
This pin operates as PPG02 when it is used in PPG0 output
modes.
13 9
RTO04_0
(PPG04_0)
Wave form generator output pin of Multi-function timer 0.
This pin operates as PPG04 when it is used in PPG0 output
modes.
14 10
RTO05_0
(PPG04_0)
Wave form generator output pin of Multi-function timer 0.
This pin operates as PPG04 when it is used in PPG0 output
modes.
15 11
Document Number: 002-04922 Rev .*B Page 26 of 128
MB9B560L Series
Pin Function
Pin Name Function Description
Pin No
LQFP64
QFN64
LQFP48
QFN48
Multi-
function
Timer
1
DTTI1X_0
Input signal controlling wave form generator outputs
RTO10 to RTO15 of Multi-function timer 1.
45 -
FRCK1_0 16-bit free-run timer ch.1 external clock input pin 44 -
IC10_0
16-bit input capture ch.1 input pin of Multi-function timer 1.
ICxx describes channel number.
46
-
IC11_0
47
-
IC12_0
48
-
IC13_0
54
-
RTO10_0
(PPG10_0)
Wave form generator output pin of Multi-function timer 1.
This pin operates as PPG10 when it is used in PPG1 output
modes.
34 -
RTO11_0
(PPG10_0)
Wave form generator output pin of Multi-function timer 1.
This pin operates as PPG10 when it is used in PPG1 output
modes.
35 -
RTO12_0
(PPG12_0)
Wave form generator output pin of Multi-function timer 1.
This pin operates as PPG12 when it is used in PPG1 output
modes.
36 -
RTO13_0
(PPG12_0)
Wave form generator output pin of Multi-function timer 1.
This pin operates as PPG12 when it is used in PPG1 output
modes.
37 -
RTO14_0
(PPG14_0)
Wave form generator output pin of Multi-function timer 1.
This pin operates as PPG14 when it is used in PPG1 output
modes.
38 -
RTO15_0
(PPG14_0)
Wave form generator output pin of Multi-function timer 1.
This pin operates as PPG14 when it is used in PPG1 output
modes.
43 -
Quadrature
Position/
Revolution
Counter
0
AIN0_0
QPRC ch.0 AIN input pin
2
-
AIN0_1
10
6
AIN0_2
34
25
BIN0_0
QPRC ch.0 BIN input pin
3
-
BIN0_1
11
7
BIN0_2
35
26
ZIN0_0
QPRC ch.0 ZIN input pin
4
-
ZIN0_1
12
8
ZIN0_2
36
36
Document Number: 002-04922 Rev .*B Page 27 of 128
MB9B560L Series
Pin Function
Pin Name Function Description
Pin No
LQFP64
QFN64
LQFP48
QFN48
Real-time
clock
RTCCO_0
0.5 seconds pulse output pin of Real-time clock
Sub clock output pin
55
-
RTCCO_1
38
29
SUBOUT_0
Sub clock output pin
55
-
SUBOUT_1
38
29
USB
UDM0
USB device/host D – pin
62
46
UDP0
USB device/host D + pin
63
47
UHCONX0
USB external pull-up control pin
59
43
Low-Power
Consumpti
on
Mode
WKUP0
Deep standby mode return signal input pin 0
60
44
WKUP1
Deep standby mode return signal input pin 1
38
29
WKUP2
Deep standby mode return signal input pin 2
15
11
WKUP3
Deep standby mode return signal input pin 3
27
-
DAC
DA0
D/A converter ch.0 analog output pin
34
25
DA1
D/A converter ch.1 analog output pin
35
26
VBAT
VREGCTL
On-board regulator control pin
20
-
VWAKEUP
The return signal input pin from a hibernation state
21
-
Reset INITX
External Reset Input pin.
A reset is valid when INITX="L".
22 16
Mode
MD1
Mode 1 pin.
During serial programming to Flash memory, MD1="L" must
be input.
28 20
MD0
Mode 0 pin.
During normal operation, MD0="L" must be input. During
serial programming to Flash memory, MD0="H" must be
input.
29 21
Power VCC Power supply Pin
1
1
-
15
25
19
33
-
USBVCC
3.3V Power supply port for USB I/O
61
45
GND VSS GND Pin
16
12
24
18
32
24
64
48
Clock
X0
Main clock (oscillation) input pin
30
22
X1
Main clock (oscillation) I/O pin
31
23
X0A
Sub clock (oscillation) input pin
17
13
X1A
Sub clock (oscillation) I/O pin
18
14
CROUT_0
Built-in high-speed CR-osc clock output port
47
-
CROUT_1
54
42
Analog
Power
AVCC
A/D converter and D/A converter analog power supply pin
39
30
AVRH
A/D converter analog reference voltage input pin
42
33
VBAT
Power VBAT
VBAT power supply pin.
Backup power supply (battery etc.) and system power
supply.
19 -
Analog
GND AVSS A/D converter and D/A converter
GND pin
40 31
AVRL
A/D converter analog reference voltage input pin
41
32
C pin
C
Power supply stabilization capacity pin
23
17
Note:
− While this device contains a Test Access Port (TAP) based on the IEEE 1149.1-2001 JTAG standard, it is not fully compliant to
all requirements of that standard. This devi ce may contai n a 32-bit device ID that is the same as the 32-bit device ID in other
devices with different func tionality. The TAP pins may also be configur able for purposes other than ac cess to the TAP
controller.
Document Number: 002-04922 Rev .*B Page 28 of 128
MB9B560L Series
5. I/O Circuit Type
Type Circuit Remarks
A
It is possible to select the main
oscillatio n / GPIO function
When the main os cillation is
selected.
− Oscillation feedback resistor
: Approximately 1 MΩ
− With Standby mode control
When the GPIO is selected.
− CMOS level output.
− CMOS level hysteresis input
− With pull-up resistor control
− With standby mode control
− Pull-up resistor
: Approximately 50 kΩ
− IOH = -4 mA, IOL = 4 mA
B
− CMOS level hysteresis input
− Pull-up resistor
: Approximately 50 kΩ
P-chP-ch
N-ch
R
R
P-chP-ch
N-ch
X0
X1
Standby mode control
Digital input
Standby mode control
Digital output
Digital output
Clock input
Digital input
Standby mode control
Pull-up resistor control
Pull-up resistor control
Digital output
Digital output
Pull-up resistor
Digital input
Document Number: 002-04922 Rev .*B Page 29 of 128
MB9B560L Series
Type
Circuit
Remarks
C
− Open drain output
− CMOS level hysteresis input
E
− CMOS level output
− CMOS level hysteresis input
− With pull-up resistor control
− With standby mode control
− Pull-up resistor
: Approximately 50 kΩ
− IOH = -4 mA, IOL = 4 mA
F
− CMOS level output
− CMOS level hysteresis input
− With input control
− Analog input
− With pull-up resistor control
− With standby mode control
− Pull-up resistor
: Approximately 50 kΩ
− IOH = -4 mA, IOL = 4 mA
− When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
N-ch
P-chP-ch
N-ch
R
P-chP-ch
N-ch
R
Digital input
Digital output
Digital output
Digital output
Pull-up resistor control
Digital input
Standby mode control
Digital output
Digital output
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
Document Number: 002-04922 Rev .*B Page 30 of 128
MB9B560L Series
Type Circuit Remarks
G
− CMOS level output
− CMOS level hysteresis input
− With pull-up resistor control
− With standby mode control
− Pull-up resistor
: Approximately 50 kΩ
− IOH = -12 mA, IOL = 12 mA
− When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
H
It is possible to select the USB
I/O / GPIO function.
When the USB I/O is selected.
− Full-speed, Low-speed control
When the GPIO is selected.
− CMOS level output
− CMOS level hysteresis input
− With standby mode control
− IOH = -20.5 mA, IOL = 18.5 mA
P-chP-ch
N-ch
R
UDP/Pxx
UDM/Pxx
Differential
Standby mode
control
Pull-up resistor
control
Digital input
Digital output
Digital output
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
UDP output
USB Full-speed/Low-speed control
UDP input
Differential input
USB/GPIO select
UDM input
UDM output
USB Digital input/output direction
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
Document Number: 002-04922 Rev .*B Page 31 of 128
MB9B560L Series
Type Circuit Remarks
I
− CMOS level output
− CMOS level hysteresis input
− With pull-up resistor control
− 5 V tolerant
− With standby mode control
− Pull-up resistor
: Approximately 50 kΩ
− IOH = -4 mA, IOL = 4 mA
− Available to control of PZR
registers.
− When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
J
CMOS level hysteresis input
L
− CMOS level output
− CMOS level hysteresis input
− With pull-up resistor control
− With standby mode control
− Pull-up resistor
: Approximately 50 kΩ
− IOH = -8 mA, IOL = 8 mA
− When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
P-ch
P-ch
N-ch
R
P-chP-ch
N-ch
R
Standby mode control
Pull-up resistor
control
Digital input
Digital output
Digital output
Mode input
Digital output
Digital output
Pull-up resistor
control
Digital input
Standby mode
control
Document Number: 002-04922 Rev .*B Page 32 of 128
MB9B560L Series
Type Circuit Remarks
M
− CMOS level output
− CMOS level hysteresis input
− With input control
− Analog input
− With pull-up resistor control
− With standby mode control
− Pull-up resistor
: Approximately 50 kΩ
− IOH = -8 mA, IOL = 8 mA
− When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
N
− CMOS level output
− CMOS level hysteresis input
− With pull-up resistor control
− With standby mode control
− Pull-up resistor
: Approximately 50 kΩ
− IOH = -4 mA, IOL = 4 mA
(GPIO)
− IOL = 20 mA
(Fast Mode Plus)
− When this pin is used as an I2C
pin, the digital output P-ch
transistor is always off
P-chP-ch
N-ch
R
P-ch
N-ch
R
P-ch
N-ch
Digital output
Digital output
Pull-up resistor
control
Digital input
Standby mode
control
Analog input
Input control
Digital output
Digital output
Pull-up resistor
control
Digital input
Standby mode
control
Fast mode control
Document Number: 002-04922 Rev .*B Page 33 of 128
MB9B560L Series
Type Circuit Remarks
O
− CMOS level output
− CMOS level hysteresis input
− 5 V tolerant
− With pull-up resistor control
− With standby mode control
− Pull-up resistor
: Approximately 50 kΩ
− IOH = -4 mA, IOL = 4 mA
− For I/O setting, refer to VBAT
Domain in the Peripheral
Manual
P
− CMOS level output
− CMOS level hysteresis input
− With pull-up resistor control
− With standby mode control
− Pull-up resistor
: Approximately 50 kΩ
− IOH = -4 mA, IOL = 4 mA
− For I/O setting, refer to VBAT
Domain in the Peripheral
Manual
P-ch
P-ch
N-ch
R
P-ch
P-ch
N-ch
R
Digital output
Digital output
Digital input
Pull-up resistor
control
Standby mode
control
Digital output
Digital output
Digital input
Pull-up resistor
control
Standby mode
control
OSC
X0A
Document Number: 002-04922 Rev .*B Page 34 of 128
MB9B560L Series
Type Circuit Remarks
Q
It is possible to select the sub
oscillatio n / GPIO function
When the sub oscillation is selected.
− Oscillation feedback resistor
: Approximately 10 MΩ
− With Standby mode control
When the GPIO is selected.
− CMOS level output.
− CMOS level hysteresis input
− With pull-up resistor control
− With standby mode control
− Pull-up resistor
: Approximately 50 kΩ
− IOH = -4 mA, IOL = 4 mA
− For I/O setting, refer to VBAT
Domain in the Peripheral
Manual
R
− CMOS level output
− CMOS level hysteresis input
− With input control
− Analog output
− With pull-up resistor control
− With standby mode control
− Pull-up resistor
: Approximately 50 kΩ
− IOH = -12 mA, IOL = 12 mA
(4.5 V to 5.5 V)
− IOH = -8 mA, IOL = 8 mA
(2.7 V to 4.5 V)
P-ch
P-ch
N-ch
R
RX
P-chP-ch
N-ch
R
X1A
Digital output
Digital output
Digital input
Pull-up resistor
control
Standby mode
control
OSC
Standby mode
control
Clock input
Pull-up resistor
control
Digital input
Standby mode
control
Analog output
Digital output
Digital output
Document Number: 002-04922 Rev .*B Page 35 of 128
MB9B560L Series
6. Handling Precautions
Any semiconductor devices have inherently a certain r ate of fai lure. The possibility of failure is gre atly affected by the conditions in
which they are used (circuit conditions , environmental conditions, etc.). This page describes precautions that must be observed to
minimize the chance of failure and to obtain higher reliability from your Cypress semiconductor dev i c es.
6.1 Precautions for Product Design
This secti on describes precautions when designing el ectronic equipment using s emiconduc tor devices.
Absolute Maximum Ratings
Semiconductor devices can be permanently damaged b y application of stress (voltage, current, temperat ure, etc.) in excess of
certain establ ished limits , called absolute maximum ratings. Do not exceed these ratings.
Recommended Op erating Conditions
Recommended operating co nditions are normal operating ranges for the semiconduct or device. All the device's electrical
characteris tics are warranted when oper ated within these ranges.
Always use semiconductor devices withi n the recomme nded operati ng conditi ons . Operation outside these ranges may adversely
affect reliability and could result i n device failur e.
No warranty is made with resp ect to uses, op erating conditions, or combi nations not r epresented on the data she et. Users
considering application outside the li s ted conditions are advi sed to contact thei r sales repr es entative beforehand.
Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/output
functions.
1. Preventing Over-Voltage and Over-Curr ent Con dit io ns
Exposure to vol tage or current levels in excess of maximum rat ings at any pin is likely to caus e deterioration within t he device,
and in extreme cases leads to permanent damage of the device. Try to prevent such overvoltage or over-current conditions at the
design stage.
2. Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows.
Such conditions if present for extended p eriods of time c an damage the de v i c e.
Therefore, av oid this type of c onnection.
3. Handling of U nused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation. Such pins should be
connected through an appropriate resistance to a power supply pin or gr ound pin.
Latch-Up
Semiconductor devices are c onstructed by the formati on of P-type and N-type areas on a substrate. When subjected to abnormall y
high voltages, internal parasitic PNPN junctions (called thyristor structures) may be formed, causing large current levels in excess of
several hundred mA to flow continuously at the power sup ply pin. This conditi on is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconduct or device, but c an c ause injury or
damage from h i gh heat, smoke or flame. To prevent this from happening, do the following:
1. Be sure that voltages app li ed to pins do not exceed the absolute maximum ratings. This should include attenti on to abnormal
noise, surge l evels, etc.
2. Be sure that abnormal current flo ws do not occur during the power-on sequence.
Observance of Safety Regulations and Standards
Most countries in the world h ave establis hed standar ds and regulations regardi ng s afety, protect i on from electr omagnetic
interference, etc. Customers are requested to obs er ve applicable regulations and standar ds in the design of products.
Fail-Safe Design
Any semiconductor devices have inherently a certain r ate of fai lure. You must protect against injury, damage or loss from such
failures by incorporating s afety desig n m easures into your facility and equipment s uc h as redundancy, fire protection, and
prevention of over-current levels and other abnormal operating conditions.
Document Number: 002-04922 Rev .*B Page 36 of 128
MB9B560L Series
Precautions Related to Usage of Devices
Cypress semiconductor devices are intended for us e in standard applications (computer s, office automation a nd other office
equipment, industrial, communicati ons , and measurement equipment, personal or household devices, etc.).
CAUTION: Customers consi dering the use of our products in special applications where failure or abnormal operation may directly
affect human lives or c ause physical injury or proper ty damage, or where extrem ely high levels of reliabil ity are demanded (such as
aerospace systems, atomi c energy controls, sea floor repeaters, vehicle operat i ng controls, medical devi c es for life support, etc.)
are requested to consult with sales representat ives before such use. The company will not be responsible for damages arising fr o m
such use witho ut prior approval.
6.2 Precautions for Package Mounting
Package mounting may be either lead insertion type or sur face mount type. In either c ase, for heat r esistance during soldering, you
should only mount under Cypress's recommended conditions. For detailed infor m ation about mount conditions, contact your sales
representative.
Lead Insertion Type
Mounting of le ad i ns ertion typ e packages onto pr i nted circuit boar ds may be done by two methods: direct sol der i ng on the board, or
mounting by us i ng a s ocket.
Direct mount ing onto boards normally involves processes for insert ing leads into through-holes on the board and using the flow
soldering (wave soldering) method of applying liquid solder. In this case, the soldering process usually causes leads to be subjected
to thermal str ess in excess of the absolut e ratings for storage temperature. Mounting processes should conform to Cypress
recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can lead to contact
deterioration after long periods. For this reason it i s recommended that the surface treatm ent of socket contacts and IC leads be
verified befor e mounting.
Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are more easily deformed
or bent. The use of packages with higher pin counts and narrower pin pit ch results in increased susceptibil ity to open co nnections
caused by defo r med pins, or shorting due to solder bridges.
You must use appropriat e mounting techniques. Cypress rec ommends the s ol der reflow method, and have established a ranking of
mounting conditions for each product. Users are advised t o mount packages in accordance with Cypress rank i ng of recommen ded
conditions.
Lead-Free Packagi ng
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic soldering, junction strength
may be reduced under some conditions of use.
Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of
moisture. During mounting, the application of heat to a package that has absorb ed m oi s ture can caus e surfaces to peel, r educing
moisture res i s tance and causing packages to crack. To prevent, do the fol lowing:
1. Avoid exposure to r api d temperat ur e changes, which cause moisture to co ndense inside the product. S tore products i n
locations where temperature changes are slight.
2. Use dry boxes for product storage. Products should be stored belo w 70% r el ative humidity, and at temperatures between 5°C
and 30°C.
When you open Dry Package t hat recommends humidity 40% t o 70% r elative humidity.
3. When necessary, Cypress packages semiconductor devices in hi ghly moisture-resistant aluminum laminate bags, with a silica
gel desiccant. Devices should be sealed in their aluminum laminate b ags for stor age.
4. Avoid storing packages where t hey are exposed t o corrosive gases or high levels of dust.
Baking
Packages that hav e absorbed m oi s ture may be de-moisturized by baking (heat drying). Follow the Cypress recommended
conditions for baking.
Condition: 125°C/24 h
Document Number: 002-04922 Rev .*B Page 37 of 128
MB9B560L Series
Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions:
1. Maintain relative humidity in the working environment between 40% and 70%. U s e of an apparatus for ion generat ion may be
needed to remov e electricity.
2. Electrically ground all conveyors, solder vessels , soldering ir ons and peripheral equipment.
3. Eliminate s tatic body electricit y by the use of rings or bracelets c onnected to grou nd through high resistance (on the level of
1 MΩ).
Wearing of conductive clothing and sh oes, use of conductive floor mats and other m easures to m i nimize shock lo ads is
recommended.
4. Ground all fixtures and i ns truments, or protect with anti-stat ic measures.
5. Avoid the use of Styrof oam or other hig hly static-pr one materials for storage of c om pleted boar d as semblies.
6.3 Precautions for Use Environment
Reliability of semicon duc tor devices depends on ambi ent temperature and other conditions as described above.
For reliable p erformance, do the following:
1. Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high humidity levels are
anticipate d, consider anti -h u midi t y proces si ng.
2. Discharge of Static Electricity
When high-volt age charges exist close to semiconductor devices, discharges can cause abnormal operation. In such cases, use
anti-static measures or processing to prevent discharges.
3. Corrosive Gases, Dust , or Oil
Exposure to corrosive gases or c ontact with dust or oil m ay lead to chemical react i ons that will advers ely affect the device. If you
use devices in such conditi ons, consider ways to prevent such exposure or to protect the devices.
4. Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation. Users should provide
shielding as a ppropriat e.
5. Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible substances. If devices
begin to smoke or burn, there is danger of the r el ease of toxic gases.
Customers co nsidering the use of Cypress products in other special environmental conditions should consult with sales
representatives.
Document Number: 002-04922 Rev .*B Page 38 of 128
MB9B560L Series
7. Handling Devices
Power Supply Pins
In products with multiple VCC and VSS pins, respective pins at the same potential are in terconnected within the device in order to
prevent malfunctions such as latch-up. However, all of these pins s hould be connected externally to the p ower supply or gr ound
lines in order to reduce electromagnetic em ission levels, to prevent abnormal operation of strobe signals caused by the rise i n the
ground level, and to conform to the total outp ut current rating.
Moreover, connect the current supply sour ce with each POWER pins and GND pins of t his device at low impedance. It is also
advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass capacitor between VCC and V S S near this
device.
Power Supply Pins
A malf unction may occur when the power supply vol tage fluctuates rapidl y even though the fluctuation is within the guaranteed
operating range of the VCC power supply voltage. As a rule of voltage st abilization, suppress vol tage fluctuation so that the
fluctuation i n VCC ripple (peak-to-peak value) at the commer cial frequency (50 Hz/60 Hz) does not exc eed 10% of the standard
VCC value, and the transient fluctuation rate does not exceed 0.1 V/μs at a momentary fluctuation such as switching the power
supply.
Crystal Oscillator Circuit
Noise near the X0/X1 and X0A /X1A pins may caus e the device t o malfunction. Design the printed circuit board so that X0/X1,
X0A/X1A pins, the crystal os c illator (or ceramic osci llator), a nd the bypass c apacitor to ground are locat ed as close to the device as
possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins are surrounded by
ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillat or by your m ount board.
Sub Crystal Oscillator
This series s ub oscillator circuit is low gain to keep the low current consumption.
The crystal oscillator to f i ll the following conditi ons i s recommended for sub crystal oscillator to stabilize the oscillat ion.
• Surface mount type
Size: More than 3.2 mm × 1.5 mm
Load capacitance: Approximately 6 pF to 7 pF
• Lead type
Load capacitance: Approximately 6 pF to 7 pF
Using an External Clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input the clock to X0. X1 (PE3)
can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0 A /X1A to t he external cl oc k input, and input the clock to
X0A. X1A ( P 47) can be use d as a general -purpose I/ O port.
Example of Using an External Clock
Device
X0(X0A)
X1(PE3), X1A (P47)
Can be used as
general-purpose
I/O ports.
Set as External
clock input
Document Number: 002-04922 Rev .*B Page 39 of 128
MB9B560L Series
Handling when Using Multi-Function Serial Pin as I2C Pin
If it is using t he multi-function serial pin as I 2C pins, P-ch transis tor of digital output is always disable d.
However, I2C pins need to kee p the electrical character istic like other pins and not t o connect t o the external I2C bus system with
power OFF.
C Pin
This series c ontains the regulator. Be sure to connect a sm oothing capacitor (CS) for the regulat or between the C pin and the GND
pin. Please us e a ceramic capacitor or a capacit or of equivale nt frequenc y characteristi cs as a smoothing capacitor.
However, some laminated c eramic capac itors have the characteri s tics of capac itance variation due to th er mal fluctuat i on (F
characteristics and Y5V characteristics). Plea s e select the capacitor that m eets the specifications i n the operating c onditions to us e
by evaluating the temperatur e characteristics of a capac itor.
A smoothing capacit or of about 4.7 μF would be recommended for this series.
Mode Pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the pull-up/down resistance stays
low, as well as the distance between the mode pins and VCC pins or VSS pins is as short as possible and the connection
impedance is low, when the pins are pulled-up/down such as for switching the pin l evel and rewrit i ng the Flash memory data. It is
because of pre v enting the device erroneously switchin g to test mode due to noise.
Notes on Power-on
Turn power on/off in the following order or at the same time. The device oper ates normally af ter all po wer on.
In the case of 64p in package, VB AT only Power-on is possible when turns all power on and Hiber nation control is setting and then
except for VBAT turns power off. About Hibernation control, see Chapter 7-2: VBAT Domain (A) in FM4 Family Perip heral Manual
(002-04856).
If not using the A/D converter and D/A converter, connect AV CC = VCC and AVSS = VSS.
Turning on:
VBAT → VCC → USBVCC
VCC → AVCC → AVRH
Turning off:
AVRH → AVCC → VCC
USBVCC → VCC → VBAT
Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial c ommunicatio n.
Therefore, des ign a printed circuit board s o as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a checksum of data at the end.
If an error is detected, retransmit t he data.
Differences in Features among the Products with Different Memory Sizes and between Flash Products and
MASK Products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and oscillation characteristics among
the products with different memory sizes and between Flash pr oducts and MA SK products ar e different because chi p layout and
memory structures are different.
If you are switc hi ng to use a different prod uct of the same series, please make sure to evaluate the electric characteristics.
Pull-Up Function of 5 V Tolerant I/O
Please do not input the signal m ore than VCC voltage at the time of pull-up function use of 5V tolerant I/O.
Device
C
VSS
CS
GND
Document Number: 002-04922 Rev .*B Page 40 of 128
MB9B560L Series
Handling when Using Debug Pins
When debug pins (TDO/T MS/TDI/TCK /TRSTX or SWO/SWDIO/SWCLK ) are set to GPI O or other peripheral functions, only set
them as output , do not set them as i nput.
Document Number: 002-04922 Rev .*B Page 41 of 128
MB9B560L Series
8. Block Diagram
Cortex-M4F Core
@160 MHz(Max)
MainFlash I/F
Clock Reset
Generator
Dual-Timer
Watchdog Timer
(Hardware)
DMAC
8ch.
Watch Counter
Unit 0
CSV
External Interrupt
Controller
16pin + NMI
Power-On
Reset
SRAM0
16/24/32 Kbytes
A
H
B
-
A
P
B
B
r
i
d
g
e
:
A
P
B
1
(
M
a
x
1
6
0
M
H
z
)
SRAM1
8/12/16 Kbytes
A
H
B
-
A
P
B
B
r
i
d
g
e
:
A
P
B
0
(
M
a
x
8
0
M
H
z
)
I
D
Sys
CLK
MB9BF564K/L, F565K/L, F566K/L
A
H
B
-
A
P
B
B
r
i
d
g
e
:
A
P
B
2
(
M
a
x
8
0
M
H
z
)
NVIC
Watchdog Timer
(Software)
Security
Unit 1
TRSTX,TCK,
TDI,TMS
X0
AVCC,
AVSS,
AVRH
ANxx
TIOAx
TIOBx C
TDO
X1
X0A
X1A
SCKx
SINx
SOTx
INTxx
NMIX
P0x,
P1x,
.
.
.
PEx
INITX
MODE-Ctrl
IRQ-Monitor
MD0,
MD1
Regulator
CRC Accelerator
A
H
B
-
A
H
B
B
r
i
d
g
e
ADTGx
RTS4
CTS4
MainFlash
512 Kbytes/
384 Kbytes/
256 Kbytes
Multi-function Serial I/F
6ch.
HW flow control(ch.4)
GPIO
PIN-Function-
Ctrl
LVD
M
u
l
t
i
-
l
a
y
e
r
A
H
B
(
M
a
x
1
6
0
M
H
z
)
ROM
Table
SWJ-DP
Main
Osc PLL CR
100 kHz
LVD Ctrl
Base Timer
16-bit 16ch./
32-bit 8ch.
Peripheral Clock Gating
Low-speed CR Prescaler
RTCCO,
SUBOUT
Deep Standby Ctrl
WKUPx
16-bit Free-run Timer
3ch.
16-bit Output Compare
6ch.
16-bit Input Capture
4ch.
A/D Activation Compare
6ch.
16-bit PPG
3ch.
DTTIxX
FRCKx
QPRC
1ch.
BINx
ZINx
ICxx
RTOxx
AINx
12-bit A/D Converter
Multi-function Timer
× 2
Waveform Generator
3ch.
MPU
FPU
12-bit D/A Converter
2units
SRAM2
8/12/16 Kbytes
WorkFlash
32 Kbytes
WorkFlash I/F
Trace Buffer
(16 Kbytes)
DSTC
CAN
USB2.0
(Host/
Device)
PHY
USBVCC
UDP0,UDM0
UHCONX0
TX0,
RX0
CAN Prescaler
USB Clock Ctrl PLL
VREGCTL
VWAKEUP
DAx
Real-Time Clock
Port Ctrl.
Sub
Osc
VBAT Domain
VBAT Domain CR
4 MHz
CROUT
Source Clock
Document Number: 002-04922 Rev .*B Page 42 of 128
MB9B560L Series
9. Memory Size
See Memory siz e i n 1. Product Lineup to confirm the memory size.
10. Memory Map
Memory Map (1)
Peripherals Area
0x41FF_FFFF
0x4007_0000
0x4006_F000
GPIO
0xFFFF_FFFF 0x4006_3000
0x4006_2000
CAN ch.0
0xE010_0000 0x4006_1000
DSTC
0x4006_0000
DMAC
0xE000_0000 0x4005_0000
0x4004_0000
USB ch.0
0x4003_C800
0x4003_C100 Peripheral Clock Gating
0x4003_C000 Low Speed CR Prescaler
0x6000_0000 0x4003_B000
RTC/Port Ctrl
0x4003_A000
Watch Counter
0x4003_9000
CRC
0x4400_0000 0x4003_8000
MFS
0x4003_7000
CAN prescaler
0x4200_0000 0x4003_6000
USB Clock c trl
0x4003_5000
LVD/DS mode
0x4003_4000
Reserved
0x4000_0000 0x4003_3000
D/AC
0x4003_2000
Reserved
0x4003_1000
Int-Req.Read
0x2400_0000 0x4003_0000
EXTI
0x4002_F000
Reserved
0x2200_0000 0x4002_E000
CR Trim
0x4002_8000
0x2010_0000 0x4002_7000
A/DC
0x200E_0000
WorkFlash I/F
0x4002_6000
QPRC
0x200C_0000
WorkFlash
0x4002_5000
Base Timer
0x4002_4000
PPG
0x2004_4000
0x2004_0000
SRAM2
0x4002_2000
0x2003_C000
SRAM1
0x4002_1000
MFT Unit1
0x2000_0000
Reserved
0x4002_0000
MFT Unit0
0x1FFF_8000
SRAM0
0x0050_0000
Reserved
0x4001_6000
0x0040_0000
Security/CR Trim
0x4001_5000
Dual Timer
0x4001_3000
0x4001_2000
SW WDT
0x0000_0000 0x4001_1000
HW WDT
0x4001_0000
Clock/Reset
0x4000_1000
0x4000_0000
MainFlash I/F
Reserved
Reserved
Reserved
Reserved
Reserved
32 Mbytes
Bit band alias
Reserved
See "Memory Map (2)"
for the memory size
details.
MainFlash
Reserved
Reserved
32 Mbytes
Bit band alias
Reserved
Peripherals
Reserved
Reserved
Reserved
Cortex-M4F Private
Peripherals
Reserved
Reserved
External Device
Area
Document Number: 002-04922 Rev .*B Page 43 of 128
MB9B560L Series
Memory Map (2)
MB9BF566K/L MB9BF565K/L MB9BF564K/L
0x2008_0000 0x2008_0000 0x2008_0000
0x200C_8000 0x200C_8000 0x200C_8000
0x200C_0000 0x200C_0000 0x200C_0000
0x2004_4000 0x2004_3000 0x2004_2000
0x2004_0000 0x2004_0000 0x2004_0000
0x2003_E000
0x2003_D000
0x2003_C000
0x2000_0000 0x2000_0000 0x2000_0000
0x1FFF_C000
0x1FFF_A000
0x1FFF_8000
0x0050_0000 0x0050_0000 0x0050_0000
0x0040_2000
CR trimming 0x0040_2000 CR trimming 0x0040_2000 CR trimming
0x0040_0000
Security 0x0040_0000 Security 0x0040_0000 Security
0x0008_0000
0x0006_0000
0x0004_0000
0x0000_0000 0x0000_0000 0x0000_0000
SRAM2
8 Kbytes
Reserved
SRAM0
16 Kbytes
Reserved
Reserved
SRAM1
12 Kbytes
Reserved
SRAM1
8 Kbytes
Reserved
Reserved
MainFlash
256 Kbytes
Reserved
MainFlash
384 Kbytes
Reserved
Reserved
Reserved
SRAM0
24 Kbytes
Reserved
WorkFlash
32 Kbytes
WorkFlash
32 Kbytes
Reserved
Reserved
WorkFlash
32 Kbytes
SRAM2
12 Kbytes
MainFlash
512 Kbytes
Reserved
Reserved
SRAM0
32 Kbytes
SRAM1
16 Kbytes
SRAM2
16 Kbytes
Document Number: 002-04922 Rev .*B Page 44 of 128
MB9B560L Series
Peripheral Address Map
Start Address End Address Bus Peripherals
0x4000_0000
0x4000_0FFF
AHB
MainFlash I/F register
0x4000_1000
0x4000_FFFF
Reserved
0x4001_0000
0x4001_0FFF
APB0
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog timer
0x4001_2000
0x4001_2FFF
Software Watchdog timer
0x4001_3000
0x4001_4FFF
Reserved
0x4001_5000
0x4001_5FFF
Dual-Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_0FFF
APB1
Multi-function timer unit0
0x4002_1000
0x4002_1FFF
Multi-function timer unit1
0x4002_2000
0x4003_FFFF
Reserved
0x4002_4000
0x4002_4FFF
PPG
0x4002_5000
0x4002_5FFF
Base T imer
0x4002_6000
0x4002_6FFF
Quadrature Position/Revolution Counter
0x4002_7000
0x4002_7FFF
A/D Converter
0x4002_8000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Internal CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
APB2
External Interrupt Controller
0x4003_1000
0x4003_1FFF
Interrupt Request Batch-Read Func tion
0x4003_2000
0x4003_4FFF
Reserved
0x4003_3000
0x4003_3FFF
D/A Converter
0x4003_4000
0x4003_4FFF
Reserved
0x4003_5000
0x4003_57FF
Low Voltage Detector
0x4003_5800
0x4003_5FFF
Deep standby mode Controller
0x4003_6000
0x4003_6FFF
USB clock generator
0x4003_7000
0x4003_7FFF
CAN prescaler
0x4003_8000
0x4003_8FFF
Multi-function serial Interface
0x4003_9000
0x4003_9FFF
CRC
0x4003_A000
0x4003_AFFF
Watch Counter
0x4003_B000
0x4003_BFFF
RTC/Port Ctrl
0x4003_C000
0x4003_C0FF
Low-speed CR Prescaler
0x4003_C100
0x4003_C7FF
Peripheral Clock Gating
0x4003_C800
0x4003_FFFF
Reserved
0x4004_0000
0x4004_FFFF
AHB
USB ch.0
0x4005_0000
0x4005_FFFF
Reserved
0x4006_0000
0x4006_0FFF
DMAC register
0x4006_1000
0x4006_1FFF
DSTC register
0x4006_2000
0x4006_2FFF
CAN ch.0
0x4006_3000
0x4006_EFFF
Reserved
0x4006_F000
0x4006_FFFF
GPIO
0x4006_7000
0x41FF_FFFF
Reserved
0x200E_0000
0x200E_FFFF
WorkFlash I/F register
Document Number: 002-04922 Rev .*B Page 45 of 128
MB9B560L Series
11. Pi n St atus in Each CPU State
The terms us ed for pin status have the following meanin gs.
INITX=0
This is the per iod when the INITX pin is the L level.
INITX=1
This is the per iod when the INITX pin is the H level.
SPL=0
This is the s tatus that the standby pin level setting bit (SPL) in the stand by mode control register ( S TB_CTL) i s set to 0.
SPL=1
This is the s tatus that the standby pin level setting bit (SPL) in the stand by mode control register ( S TB_CTL) i s set to 1.
Input enabled
Indicates th at the input func tion can be used.
Internal input fixe d at 0
This is the s tatus that the input function cannot be used. Internal input is fixed at L.
Hi-Z
Indicates th at the pin drive t r ansistor is disabled and the pin is put in t he Hi-Z st ate.
Setting disabled
Indicates th at the setting is disabled.
Maintain previous state
Maintains the state that was immediatel y pr ior to entering the current mode.
If a built-in per ipheral funct ion is operating, the output follows the per ipheral f unction.
If the pin is being used as a port, that output is maintained.
Analog input is enabl ed
Indicates th at the analog input is enabled.
Trace output
Indicates th at the trace function can be used.
GPIO selected
In Deep standb y mode, pins switch to the general-purpos e I/O port.
Setting prohibition
Prohibition of a setting by specificati on limitati on.
Document Number: 002-04922 Rev .*B Page 46 of 128
MB9B560L Series
List of Pin Status
Pin Status Type
Function
Group
Power-on
Reset or
Low-Voltage
Detection
State
INITX
Input
State
Device
Internal
Reset
State
Run
Mode
or Sleep
Mode
State
Timer Mode,
RTC Mode, or
Stop Mode State
Deep Standby RTC
Mode or Deep Standby
Stop Mode State
Return from
Deep
Standby
Mode State
Power
Supply
Unstable
Power Supply
Stable
Power
Supply
Stable
Power Supply
Stable Power Supply
Stable
Power
Supply
Stable
‐
INITX=0
INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
‐
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
A
GPIO
selected Setting
disabled Setting
disabled Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Main
crystal
oscillator
input pin/
External
main clock
input
selected
Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled
B
GPIO
selected Setting
disabled Setting
disabled Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
External
main clock
input
selected
Setting
disabled Setting
disabled Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Main
crystal
oscillator
output pin
Hi-Z /
Internal input
fixed at "0"/
or Input
enabled
Hi-Z /
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Maintain previous state /
When oscillation stops*1, Hi-Z /
Internal input fixed at 0
C
INITX
input pin
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
D
Mode
input pin Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled
Document Number: 002-04922 Rev .*B Page 47 of 128
MB9B560L Series
Pin Status Type
Function
Group
Power-on
Reset or
Low-Voltage
Detection
State
INITX
Input
State
Device
Internal
Reset
State
Run Mode
or SLEEP
Mode
State
TIMER Mode,
RTC Mode, or
STOP Mode State
Deep Standby RTC
Mode or Deep Standby
STOP Mode State
Return
from
Deep
Standby
Mode
State
Power
Supply
Unstable
Power Supply
Stable
Power
Supply
Stable
Power Supply
Stable Power Supply
Stable
Power
Supply
Stable
‐
INITX=0
INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
‐
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
E
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
GPIO
selected Setting
disabled Setting
disabled Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Input
enabled
GPIO
selected
Hi-Z /
Input
enabled
GPIO
selected
F
NMIX
selected Setting
disabled Setting
disabled Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
Hi-Z /
WKUP
input
enabled
GPIO
selected
Resource
other than
above
selected
Hi-Z Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Maintain
previous
state
G
JTAG
selected Hi-Z Pull-up /
Input
enabled
Pull-up /
Input
enabled Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
selected Setting
disabled Setting
disabled Setting
disabled
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
J
Analog
output
selected
Setting
disabled Setting
disabled Setting
disabled
Maintain
previous
state
*2 *3
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Resource
other than
above
selected
Hi-Z Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
K
External
interrupt
enabled
selected
Setting
disabled Setting
disabled Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Resource
other than
above
selected
Hi-Z Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Document Number: 002-04922 Rev .*B Page 48 of 128
MB9B560L Series
Pin Status Type
Function
Group
Power-on
Reset or
Low-Voltage
Detection
State
INITX
Input
State
Device
Internal
Reset
State
Run Mode
or Sleep
Mode
State
Timer Mode,
RTC Mode, or
Stop Mode State
Deep Standby RTC
Mode or Deep Standby
Stop Mode State
Return
from
Deep
Standby
Mode
State
Power
Supply
Unstable
Power Supply
Stable
Power
Supply
Stable
Power Supply
Stable Power Supply
Stable
Power
Supply
Stable
‐
INITX=0
INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
‐
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
L
Analog
input
selected Hi-Z
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Resource
other than
above
selected Setting
disabled Setting
disabled Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
GPIO
selected
M
Analog
input
selected Hi-Z
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
External
interrupt
enabled
selected
Setting
disabled Setting
disabled Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Resource
other than
above
selected
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Document Number: 002-04922 Rev .*B Page 49 of 128
MB9B560L Series
Pin Status Type
Function
Group
Power-on
Reset or
Low-Voltage
Detection
State
INITX
Input
State
Device
Internal
Reset
State
Run Mode
or Sleep
Mode
State
Timer Mode,
RTC Mode, or
Stop Mode State
Deep Standby RTC
Mode or Deep Standby
Stop Mode State
Return
from
Deep
Standby
Mode
State
Power
Supply
Unstable
Power Supply
Stable
Power
Supply
Stable
Power Supply
Stable Power Supply
Stable
Power
Supply
Stable
‐
INITX=0
INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
‐
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
O
Analog
input
selected Hi-Z
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
WKUP
enabled Setting
disabled Setting
disabled Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
WKUP
input
enabled
GPIO
selected
External
interrupt
enabled
selected
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Resource
other than
above
selected Hi-Z Hi-Z
Input
enabled
Hi-Z
Input
enabled
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
P
Analog
input
selected Hi-Z
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
WKUP
enabled
Setting
disabled Setting
disabled Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
Hi-Z /
WKUP
input
enabled
GPIO
selected
Resource
other than
above
selected
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Document Number: 002-04922 Rev .*B Page 50 of 128
MB9B560L Series
Pin Status Type
Function
Group
Power-on
Reset or
Low-Voltage
Detection
State
INITX
Input
State
Device
Internal
Reset
State
Run Mode
or Sleep
Mode
State
Timer Mode,
RTC Mode, or
Stop Mode State
Deep Standby RTC
Mode or Deep Standby
Stop Mode State
Return
from
Deep
Standby
Mode
State
Power
Supply
Unstable
Power Supply
Stable
Power
Supply
Stable
Power Supply
Stable Power Supply
Stable
Power
Supply
Stable
‐
INITX=0
INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
‐
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
Q
WKUP
enabled Setting
disabled Setting
disabled Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
Hi-Z /
WKUP
input
enabled
GPIO
selected
External
interrupt
enabled
selected
GPIO
selected
Internal
input fixed
at 0
Hi-Z /
Internal
input fixed
at 0
Resource
other than
above
selected
Hi-Z Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
R
GPIO
selected Hi-Z Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
GPIO
selected
Internal
input fixed
at "0"
Hi-Z /
Input
enabled
Hi-Z /
Internal
input fixed
at "0"
Hi-Z /
Input
enabled
GPIO
selected
USB I/O pin Setting
disabled Setting
disabled Setting
disabled
Hi-Z at
trans-
mission/
Input
enabled/
Internal
input fixed
at 0 at
reception
Hi-Z at
trans-
mission/
Input
enabled/
Internal
input fixed
at 0 at
reception
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
*1: Oscillation is stopped at Sub timer mode, sub CR timer mode, RTC mode, Stop mode, D eep Standby RTC mode, and Deep
Standby Stop mode.
*2: Maintain prev i ous state at timer mode. GPIO selected Int er nal input fix ed at 0 at RTC mode, Stop mode.
*3: Maintain pr ev i ous state at timer mode. Hi -Z/Internal input fixed at 0 at RTC mode, Stop mode.
Document Number: 002-04922 Rev .*B Page 51 of 128
MB9B560L Series
List of VBAT Domain Pin Status
VBAT Pin Status Type
Function
Group
Power-on
Reset*1
INITX
Input
State
Device
Internal
Reset
State
Run
Mode or
Sleep
Mode
State
Timer Mode,
RTC Mode, or
Stop Mode State
Deep Standby
RTC Mode or Deep
Standby Stop Mode State
Return
from
Deep
Standby
Mode
State
VBAT
RTC
Mode
State
Return
from
VBAT
RTC
Mode
State
Power
Supply
Unstable
Power Supply Stable Power
Supply
Stable
Power Supply Stable Power Supply Stable Power
Supply
Stable
Power
Supply
Stable
Power
Supply
Stable
‐
INITX=0
INITX=1
INITX=1
INITX=1
INITX=1
INITX=1
-
-
‐
‐
‐
‐
SPL=0
SPL=1
SPL=0
SPL=1
-
-
-
S
GPIO
selected Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Setting
prohibition -
Sub
crystal
oscillator
input pin /
External
sub clock
input
selected
Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled Input
enabled
Maintain
previous
state
Maintain
previous
state
T
GPIO
selected Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Setting
prohibition -
External
sub clock
input
selected
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Sub
crystal
oscillator
output pin
Hi-Z /
Internal
input
fixed at 0
or Input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state/When
oscillation
stops, Hi-Z
*2
Maintain
previous
state/When
oscillation
stops, Hi-Z
*2
Maintain
previous
state/When
oscillation
stops, Hi-Z
*2
Maintain
previous
state/When
oscillation
stops, Hi-Z
*2
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
U
Resource
selected
Hi-Z Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
selected
*1: When VBAT and VCC po we r on.
*2: When The SOSCNTL bit in the WTOSCCNT Register is “0”, Sub c rystal oscill ator output pin is m aintain pr evious state.
When The SOSCNTL bit in the WTOSCCNT Register is “1”, Osc il lation is stopped at STOP mode and Deep standby S TOP mode.
Document Number: 002-04922 Rev .*B Page 52 of 128
MB9B560L Series
12. Electrical Characteristics
12.1 Absolute Maximum Ratings
Parameter Symbol
Rating
Unit Remarks
Min
Max
Power supply voltage *1, *2 VCC VSS - 0.5 VSS + 6.5 V
Power supply voltage (for USB)*1, * 3 USBVCC VSS - 0.5 VSS + 6.5 V
Power supply voltage (VBAT) *1 ,*4 VBAT VSS - 0.5 VSS + 6.5 V
Analog power supply voltage *
1 ,
*
5
AVCC
VSS - 0.5
VSS + 6.5
V
Analog reference voltage *1 ,*5
AVRH
VSS - 0.5
VSS + 6.5
V
Input voltage *1 VI
VSS - 0.5 VCC + 0.5
(≤ 6.5V)
V Except for USB pin
VSS - 0.5
USBV
CC
+ 0.5
(≤ 6.5V)
V USB pin
VSS - 0.5 VSS + 6.5 V 5 V tolerant
Analog pin input voltage *1 VIA VSS - 0.5
AV
CC
+ 0.5
(≤ 6.5V)
V
Output voltage *1 VO VSS - 0.5
V
CC
+ 0.5
(≤ 6.5V)
V
"L" level maximum output current *6 IOL -
10
mA
4 mA type
20
mA
8 mA type
20
mA
12 mA type
22.4
mA
I2C Fm+
"L" level average output current *7 IOLAV -
4
mA
4 mA type
8
mA
8 mA type
12
mA
12 mA type
20
mA
I2C Fm+
"L" level total maximum output current
∑IOL
-
100
mA
"L" level total average output current *8
∑IOLAV
-
50
mA
"H" level maximum output current *6 IOH - - 10 mA 4 mA type
- 20 mA 8 mA type
- 20
mA
12 mA type
"H" level average output current *7 IOHAV -
- 4
mA
4 mA type
- 8
mA
8 mA type
- 12
mA
12 mA type
"H" level total maximum output current
∑IOH
-
- 100
mA
"H" level total average output current *8
∑IOHAV
-
- 50
mA
Storage temperature
TSTG
- 55
+ 150
°C
*1: These parameters are based on the condi tion that VSS = AVSS = 0.0 V.
*2: VCC must not drop bel ow VSS - 0.5 V.
*3: USBVCC must not drop below VSS - 0.5 V.
*4: VBAT mus t not drop below VSS - 0.5 V.
*5: Ensure that the voltage does not exceed VCC + 0.5 V, for example, when the power is tur ned on.
*6: The maximum output current is defined as the value of the peak curre nt flowing through any one of the
corresponding pins.
*7: The average output current is defined as the average current val ue flowing through any one of the
corresponding pins for a 100ms period.
*8: The total average outp ut current is defined as the average curre nt value flowing through all of
corresponding pins for a per iod of 100 ms.
WARNING:
− Semiconductor devices may be permanently damaged by application of s tress (incl uding, without limitation, v ol tage, cur r ent
or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
Document Number: 002-04922 Rev .*B Page 53 of 128
MB9B560L Series
12.2 Recommended Operating Conditions
Parameter Symbol Conditions
Value
Unit Remarks
Min
Max
Power supply voltage
VCC
-
2.7 *5
5.5
V
Power supply voltage (for USB) USBVCC - 3.0
3.6
(≤ VCC)
V *1
2.7
5.5
(≤ VCC)
*2
Power supply voltage (VBAT)
VBAT
-
2.7
5.5
V
Analog power supply voltage
AVCC
-
2.7
5.5
V
AVCC=VCC
Analog reference voltage
AVRH
-
*3
AVCC
V
Smoothing capacitor
CS
-
1
10
μF
for built-in regulator *6
Operating
temperature
Junction temperature
Tj
-
- 40
+ 125
°C
Ambient temperature
TA
-
- 40
*4
°C
*1: When P81/UDP0 and P80/UDM 0 pins are used as USB (UDP0, U DM0).
*2: When P81/UDP0 and P80/UDM 0 pins are used as GPI O (P81, P80).
*3: The minimum value of Analog reference voltag e depends on t he v alue of compare clock cycle (Tcck).
See "5. 12-bit A/D Converter" for the details.
*4: The maximum temperature of the ambient temperature (TA) can guarantee a range that does not exceed
the junction temperature (Tj).
The calculation formula of the ambient temperature (TA) is shown below.
TA(Max) = Tj(Max) - Pd(Max) × θja
Pd: Power diss i pation (W)
θja: Package thermal resistance (°C/W)
Pd (Max) = V CC × ICC (Max) + Σ (IOL×VOL) + Σ ((VCC-VOH) × (- IOH))
IOL: L level output current
IOH: H level output current
VOL: L level output voltage
VOH: H level out put voltage
*5: In bet ween less than the minimum power supply voltage and low voltage reset/int er rupt detec tion voltage or more, inst ruction
execution and low voltage d etection function by built-in High-speed CR (includi ng Main PLL is used) or built-in Lo w-spe ed C R i s
possible to operate only.
*6: See "C pin" in "Handling Devices" for the connection of the smoothin g c apacitor.
Package thermal resista nc e and maximum permissible power for eac h package are shown below.
The operatio n is guaranteed maximum perm i s sible power or l es s for semiconductor devices.
Table for Package Thermal Resistance and Maximum Permissible Power
Package Printed Circuit Board
Thermal
resistance θja
(°C/W)
Maximum perm issible Power (mW)
TA=+85°C
TA=+105°C
LQA048
(0.5mm pitch)
Single-layered both sides
87
460
230
4 layers
53
755
377
VNA048
(0.5mm pitch)
Single-layered both sides
30
1333
667
4 layers
24
1667
833
LQD064
(0.5mm pitch)
Single-layered both sides
70
571
286
4 layers
45
889
444
LQG064
(0.65mm pitch)
Single-layered both sides
61
656
328
4 layers
40
1000
500
VNC064
(0.5mm pitch)
Single-layered both sides
24
1667
833
4 layers
21
1905
952
Document Number: 002-04922 Rev .*B Page 54 of 128
MB9B560L Series
WARNING:
− The recommen ded operating c onditions are required to ensure the nor mal operation of the semiconductor device. All of the
device's electrical characterist ics are warranted when the devi c e i s operated under these conditions.
Any use of semiconductor devices will be under their recommended o perating condition.
Operation und er any conditions other than these con di tions may adversely affect reliability of dev i c e and could result in device
failure.
No warranty is made with resp ect to any use, operating conditions or combinations not represented on t his data sheet . If you
are consideri ng applicati on under any con ditions other than listed h erein, please c ontact sales r epresent atives beforehand.
Document Number: 002-04922 Rev .*B Page 55 of 128
MB9B560L Series
Calculation Method of Power Dissipation (Pd)
The power dissipation is sh own in the following formula.
Pd = VCC × ICC + Σ (IOL × VOL) + Σ ((VCC-VOH) × (-IOH))
IOL: "L" level output current
IOH: "H" level output current
VOL: "L" level output voltage
VOH: "H" level output voltage
ICC is a current consumed in device.
It can be analyzed as follows.
ICC = ICC(INT) + ΣICC(IO)
ICC(INT): Current c onsumed in inter nal logic and memory, etc. t hr ough regulator
ΣICC(IO): Sum of current (I/O switching current) consume d in output pin
For ICC (INT), it can be anticipated by "12.3.1 Current Rating" in "12.3 DC Characteristics" (This rating value does not include ICC (IO)
for a value at pin fixed).
For Icc (IO) , it depends on system used by customers.
The calculation formula is s hown belo w.
ICC(IO) = (CINT + CEXT) × VCC × fsw
CINT: Pin internal load capacitance
CEXT: External load capacit ance of output pin
fSW: Pin switching f requency
Parameter
Symbol
Conditions
Capacitance Value
Pin internal load capacitance CINT
4 mA type 1.93 pF
8 mA type 3.45 pF
12 mA type 3.42 pF
Calculate ICC (Max) as follows when the power dissipation can be evaluated.
1. Measure current value ICC (Typ) at normal temperature ( +25°C).
2. Add maximum leak current value ICC (leak_max) at operating on a value in (1) .
ICC(Max) = ICC(Typ) + ICC(leak_max)
Parameter
Symbol
Conditions
Current Value
Maximum leak current at operating ICC(leak_max)
Tj = +125 °C
28 mA
Tj = +105 °C
17 mA
Tj = +85 °C
13 mA
Document Number: 002-04922 Rev .*B Page 56 of 128
MB9B560L Series
Current Explanation Diagram
A
V
・・・
・・・
・・・
V A
A
Regulator
Logic
Flash
RAM
I
CC
I
CC
(INT)
ΣICC(IO)
I
OL
VOL
VOH
IOH
ICC(IO)
Chip
V
CC
CEXT
Pd = VCC×ICC + Σ(IOL×VOL)＋Σ((VCC-VOH)×(－IOH))
ICC = ICC(INT)＋ΣICC(IO)
Document Number: 002-04922 Rev .*B Page 57 of 128
MB9B560L Series
12.3 DC Character istics
12.3.1 Current Rating
Parameter Symbol
Pin
Name
Conditions Frequency*4
Value
Unit Remarks
Typ*1
Max*2
Power
supply
current ICC VCC Normal
operation
(PLL) *5, *6
160 MHz
44
72
mA *3
When all peripheral
clocks are ON
144 MHz
40
67
120 MHz
34
60
100 MHz
29
55
80 MHz
23
48
60 MHz
18
42
40 MHz
13
37
20 MHz
7.7
31
8 MHz
4.6
27
4 MHz
3.6
26
160 MHz
30
58
mA *3
When all peripheral
clocks are OFF
144 MHz 27 54
120 MHz
23
49
100 MHz
20
46
80 MHz
16
41
60 MHz
13
38
40 MHz
9
33
20 MHz
5.7
30
8 MHz
3.7
27
4 MHz
3
26
Parameter Symbol
Pin
Name
Conditions Frequency*7
Value
Unit Remarks
Typ*1
Max*2
Power
supply
current ICC VCC Normal
operation
(PLL) *8
160 MHz
64
101
mA *3
When all peripheral
clocks are ON
144 MHz 60 96
120 MHz
52
88
100 MHz
46
81
80 MHz
39
73
60 MHz
32
65
40 MHz
25
58
20 MHz
15
47
8 MHz
7.8
39
4 MHz
5.2
36
160 MHz
47
80
mA *3
When all peripheral
clocks are OFF
144 MHz
43
75
120 MHz
39
71
100 MHz
35
66
80 MHz
30
61
60 MHz
25
55
40 MHz
20
50
20 MHz
13
42
8 MHz
6.7
36
4MHz
4.6
34
*1: TA=+25 °C, VCC=3.3 V
*2: Tj=+125 °C, VCC=5.5 V
*3: When all ports are input and are fixed at " 0".
*4: Frequency is a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK/2
*5: When oper ating flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 1)
*6: Data access is nothing to MainFlash memory
*7: Frequency i s a value of HCLK. PCLK0=PCLK2=HCLK/2, PC LK 1=HCLK
*8: When stoppin g flash accelerator mode and trace buffer function (FRWTR.RWT = 10, FBFCR.BE = 0)
Document Number: 002-04922 Rev .*B Page 58 of 128
MB9B560L Series
Parameter Symbol Pin
Name Conditions Frequency*4
(MHz)
Value
Unit Remarks
Typ*1
Max*2
Power
supply
current ICC VCC Normal
operation
(PLL) *5
72 MHz
41
75
mA *3
When all peripheral
clocks are ON
60 MHz 36 69
48 MHz 31 64
36 MHz 25 57
24 MHz
18
50
12 MHz
11
42
8 MHz
8.1
39
4 MHz
5.4
37
72 MHz
32
63
mA *3
When all peripheral
clocks are OFF
60 MHz
28
58
48 MHz
24
54
36 MHz
20
50
24 MHz
15
45
12 MHz
9.1
38
8 MHz
6.9
36
4 MHz
4.6
34
*1: TA=+25 °C, VCC=3.3 V
*2: Tj=+125 °C, VCC=5.5 V
*3: When all ports are input and are fixed at " 0".
*4: Frequency i s a value of HCLK. PCLK0=PCLK1=PCLK2=HCLK
*5: When 0 wait-cycle mode (FRWTR.RWT = 00, FSYNDN.SD = 00)
Parameter Symbol Pin
Name Conditions Frequency*4
Value
Unit Remarks
Typ*1
Max*2
Power
supply
current ICC VCC
Normal
operation
(built-in
high-speed CR)
*5 4 MHz
3.3 29 mA *3
When all peripheral
clocks are ON
2.8 29 mA
*3
When all peripheral
clocks are OFF
Normal
operation
(sub oscillation) *5 32 kHz
0.51 27 mA *3
When all peripheral
clocks are ON
0.50 27 mA
*3
When all peripheral
clocks are OFF
Normal
operation
(built-in
low-speed CR)
*5 100 kHz
0.54 27 mA *3
When all peripheral
clocks are ON
0.52 27 mA
*3
When all peripheral
clocks are OFF
*1: TA=+25 °C, VCC=3.3 V
*2: Tj=+125 °C, VCC=5.5 V
*3: When all ports are input and are fixed at "0".
*4: Frequency is a value of HCLK. PCLK0=PC LK 1=PCLK2= H CLK/2
*5: When 0 wait-cycle mode ( FRWTR.RWT = 00, FSYNDN.SD = 000)
Document Number: 002-04922 Rev .*B Page 59 of 128
MB9B560L Series
Parameter Symbol Pin
Name Conditions Frequency*4
Value
Unit Remarks
Typ*1 Max*2
Power
supply
current ICCS VCC SLEEP
operation
(PLL)
160 MHz
28
58
mA *3
When all peripheral
clocks are ON
144 MHz
25
55
120 MHz
21
50
100 MHz
18
46
80 MHz
15
43
60 MHz
12
39
40 MHz
8.8
36
20 MHz
5.6
32
8 MHz
3.8
30
4 MHz
3.2
29
160 MHz
14
44
mA *3
When all peripheral
clocks are OFF
144 MHz 13 43
120 MHz
11
40
100 MHz
9.7
38
80 MHz
8.1
36
60 MHz
6.7
34
40 MHz 5.2 32
20 MHz
3.7
30
8 MHz
2.9
29
4 MHz
2.6
29
Parameter Symbol Pin
Name Conditions Frequency*5
Value
Unit Remarks
Typ*
1
Max*
2
Power
supply
current ICCS VCC SLEEP
operation
(PLL)
72 MHz
19
47
mA *3
When all peripheral
clocks are ON
60 MHz 16 43
48 MHz 13 40
36 MHz 10 37
24 MHz 7.8 34
12 MHz
5.2
31
8 MHz
4.3
30
4 MHz
3.5
29
72 MHz
8.8
36
mA *3
When all peripheral
clocks are OFF
60 MHz
7.7
35
48 MHz
6.6
34
36 MHz
5.5
32
24 MHz
4.4
31
12 MHz
3.4
30
8 MHz
3
29
4 MHz
2.7
29
*1: TA=+25 °C, VCC=3.3 V
*2: Tj=+125 °C, VCC=5.5 V
*3: When all ports are input and are fixed at " 0".
*4: Frequency is a value of HCLK. PCLK0=PC LK 1=PCLK2= H CLK/2
*5: Frequency i s a value of HCLK. PCLK0=PCLK1=P CLK2=HCLK
Document Number: 002-04922 Rev .*B Page 60 of 128
MB9B560L Series
Parameter Symbol Pin
Name Conditions Frequency*4
Value
Unit Remarks
Typ*1 Max*2
Power
supply
current ICCS VCC
SLEEP
operation
(built-in
high-speed CR)
4 MHz
1.3 27 mA *3
When all peripheral
clocks are ON
0.91 27 mA *3
When all peripheral
clocks are OFF
SLEEP
operation
(sub oscillation) 32 kHz
0.49 27 mA
*3
When all peripheral
clocks are ON
0.48 27 mA
*3
When all peripheral
clocks are OFF
SLEEP
operation
(built-in
low-speed CR)
100 kHz
0.51 27 mA *3
When all peripheral
clocks are ON
0.49 27 mA *3
When all peripheral
clocks are OFF
*1: TA=+25 °C, VCC=3.3 V
*2: Tj=+125 °C, VCC=5.5 V
*3: When all ports are input and are fixed at " 0".
*4: Frequency is a value of HCLK. PCLK0=PC LK 1=PCLK2= H CLK/2
Document Number: 002-04922 Rev .*B Page 61 of 128
MB9B560L Series
Parameter Symbol Pin
Name Conditions Frequency
Value
Unit Remarks
Typ*
1
Max*
2
Power supply
current
ICCH
VCC
STOP mode -
0.25 1.0 mA *3, *4
TA=+25°C
- 11 mA
*3, *4
TA =+85°C
- 14 mA
*3, *4
TA =+105°C
ICCT
TIMER mode
(built-in
high-speed CR) 4 MHz
0.54 1.54 mA
*3, *4
TA =+25°C
- 12 mA
*3, *4
TA =+85°C
- 15 mA
*3, *4
TA =+105°C
TIMER mode
(sub oscillation) 32 kHz
0.25 1.0 mA *3, *4
TA =+25°C
- 11 mA *3, *4
TA =+85°C
- 14 mA
*3, *4
TA =+105°C
TIMER mode
(built-in
low-speed CR) 100 kHz
0.26 1.0 mA
*3, *4
TA =+25°C
- 11 mA
*3, *4
TA =+85°C
- 14 mA
*3, *4
TA =+105°C
ICCR RTC mode
(sub oscillation) 32 kHz
0.25 1.0 mA
*3, *4
TA =+25°C
- 11 mA
*3, *4
TA =+85°C
- 14 mA
*3, *4
TA =+105°C
*1: VCC=3.3 V
*2: VCC=5.5 V
*3: When all ports are input and are fixed at " 0".
*4: When LVD is OFF
Document Number: 002-04922 Rev .*B Page 62 of 128
MB9B560L Series
Parameter Symbol Pin
Name Conditions Frequency
Value
Unit Remarks
Typ*1
Max*2
Power
supply
current
ICCHD
VCC
Deep standby
STOP mode
(When RAM is
OFF)*6
-
27 140 µA
*3, *4
TA=+25°C
- 590 µA
*3, *4
TA =+85°C
- 770 µA
*3, *4
TA =+105°C
Deep standby
STOP mode
(When RAM is
ON)*6
32 180 µA
*3, *4
TA =+25°C
- 870 µA
*3, *4
TA =+85°C
- 1200 µA
*3, *4
TA =+105°C
ICCRD
Deep standby
RTC mode
(When RAM is
OFF)*7
32 kHz
27 140 µA
*3, *4
TA =+25°C
- 590 µA
*3, *4
TA =+85°C
- 770 µA
*3, *4
TA =+105°C
Deep standby
RTC mode
(When RAM is
ON)*7
32 180 µA
*3, *4
TA =+25°C
- 870 µA
*3, *4
TA =+85°C
- 1200 µA
*3, *4
TA =+105°C
ICCVBAT VBAT
RTC stop*9 -
0.015 0.14 µA
*3, *4, *5
TA =+25°C
- 4.0 µA
*3, *4, *5
TA =+85°C
- 9.4 µA
*3, *4, *5
TA =+105°C
RTC
operation*8, *9 32 kHz
1.3 2.4 µA
*3, *4
TA =+25°C
- 6.2 µA
*3, *4
TA =+85°C
- 12 µA
*3, *4
TA =+105°C
*1: VCC=3.3 V
*2: VCC=5.5 V
*3: When all ports are input and are fixed at " 0".
*4: When LVD is OFF
*5: When sub osci llation is OFF
*6: When 48 pin Pack age, add supply current of RTC stop.
*7: When 48 pin Package, add supply current of RTC operation.
*8: When using t he c rystal oscillat or of 32 kHz (i nc l uding the current consumption of the oscil lation circ uit).
*9: In the case of setting RTC after VCC power on.
Document Number: 002-04922 Rev .*B Page 63 of 128
MB9B560L Series
Parameter Symbol Pin
Name Conditions
Value
Unit Remarks
Min Typ Max
Low-voltage
detection circuit
(LVD) power
supply current
ICCLVD
VCC
At operation - 4 7 μA For occurrence of
interrupt
Main flash
memory
write/erase
current
ICCFLASH At Write/Erase - 13.4 15.9 mA
Work flash
memory
write/erase
current
ICCWFLASH At Write/Erase - 11.5 13.6 mA
Peripheral Current Dissipation
Clock
System Peripheral Unit
Frequency (MHz)
Unit Remarks
40
80
160
HCLK
GPIO All ports 0.21 0.43 0.92
mA
DMAC - 0.71 1.43 2.74
DSTC - 0.36 0.72 1.46
CAN 1ch. 0.03 0.06 0.11
USB 1ch. 0.42 0.80 1.60
PCLK1
Base timer 4ch. 0.18 0.36 0.70
mA
Multi-functional
timer/PPG
1 unit/4ch. 0.57 1.13 2.24
Quadrature
position/Revolution
counter
1 unit 0.04 0.08 0.16
A/DC 1 unit 0.21 0.40 0.79
PCLK2 Multi-function serial 1ch. 0.33 0.67 - mA
Document Number: 002-04922 Rev .*B Page 64 of 128
MB9B560L Series
12.3.2 Pin Characterist ics (VCC = USBVCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V)
Parameter Symbol Pin Name Conditions Value Unit Remarks
Min Typ Max
"H" level input
voltage
(hysteresis
input)
VIHS
CMOS
hysteresis
input pin,
MD0, MD1
- VCC×0.8 - VCC + 0.3 V
5V tolerant
input pin
- VCC×0.8 - VSS + 5.5 V
Input pin
doubled as I2C
Fm+
- VCC×0.7 - VSS + 5.5 V
"L" level input
voltage
(hysteresis
input)
VILS
CMOS
hysteresis
input pin,
MD0, MD1
- VSS - 0.3 - VCC×0.2 V
5V tolerant
input pin
- VSS - 0.3 - VCC×0.2 V
Input pin
doubled as I2C
Fm+
- VSS - VCC×0.3 V
"H" level output
voltage VOH
4mA type
VCC ≥ 4.5 V,
IOH = - 4 mA VCC - 0.5 - VCC V
V
CC
< 4.5 V,
IOH = - 2 mA
8mA type
VCC ≥ 4.5 V,
IOH = - 8 mA
VCC - 0.5 - VCC V
V
CC
< 4.5 V,
IOH = - 4 mA
12mA type
VCC ≥ 4.5 V,
IOH = - 12 mA
VCC - 0.5 - VCC V
VCC < 4.5 V,
IOH = - 8 mA
The pin
doubled as
USB I/O
USBVCC ≥ 4.5 V,
IOH = - 20.5 mA
USBVCC - 0.4 - USBVCC V
USBV
CC
< 4.5 V,
IOH = - 13.0 mA
The pin
doubled as I2C
Fm+
V
CC
≥ 4.5 V,
IOH = - 4 mA
VCC - 0.5 - VCC V At GPIO
V
CC
< 4.5 V,
IOH = - 3 mA
Document Number: 002-04922 Rev .*B Page 65 of 128
MB9B560L Series
Parameter Symbol Pin Name Conditions
Value
Unit Remarks
Min Typ Max
"L" level output
voltage VOL
4 mA type
VCC ≥ 4.5 V,
IOL = 4 mA VSS - 0.4 V
VCC < 4.5 V,
IOL = 2 mA
8 mA type
VCC ≥ 4.5 V,
IOH = 8 mA VSS - 0.4 V
VCC < 4.5 V,
IOH = 4 mA
12 mA type
VCC ≥ 4.5 V,
IOL = 12 mA VSS - 0.4 V
VCC < 4.5 V,
IOL = 8 mA
The pin
doubled as
USB I/O
USBVCC ≥ 4.5 V,
IOL = 18.5 mA VSS - 0.4 V
USBVCC < 4.5 V,
IOL = 10.5 mA
The pin
doubled as
I2C Fm+
VCC ≥ 4.5 V,
IOH = 4 mA
VSS - 0.4 V At GPIO
VCC < 4.5 V,
IOH = 3 mA
VCC ≤ 5.5 V,
IOH = 20 mA At I2C Fm+
Input leak
current
IIL - - - 5 - + 5 μA
Pull-up resistor
value RPU Pull-up pin VCC ≥ 4.5 V 25 50 100 kΩ
VCC < 4.5 V
30
80
200
Input
capacitance CIN
Other than
VCC,
USBVCC,
VBAT,
VSS,
AVCC,
AVSS,
AVRH
- - 5 15 pF
Document Number: 002-04922 Rev .*B Page 66 of 128
MB9B560L Series
12.4 AC Character istics
12.4.1 Main Clock Inpu t Characteristics (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter Symbol Pin
Name Conditions
Value
Unit Remarks
Min
Max
Input frequency fCH
X0,
X1
VCC ≥ 4.5 V
4
48
MHz When crystal oscillator is connected
VCC < 4.5 V
4
20
VCC ≥ 4.5 V
4
48
MHz When using external clock
VCC < 4.5 V
4
20
Input clock cycle tCYLH
VCC ≥ 4.5 V
20.83
250
ns When using external clock
VCC < 4.5 V
50
250
Input clock pulse
width
- PWH/tCYLH,
PWL/tCYLH
45 55 % When using external clock
Input clock rising time
and falling time
t
CF
,
tCR
- - 5 ns When using external clock
Internal operating
clock*1 frequency
fCC - - - 160 MHz Base clock (HCLK/FCLK)
fCP0
-
-
-
80
MHz
APB0 bus clock*2
fCP1
-
-
-
160
MHz
APB1 bus clock*2
fCP2 - - - 80 MHz APB2 bus clock*2
Internal operating
clock*1 cycle time
tCYCC - - 6.25 - ns Base clock (HCLK/FCLK)
tCYCP0
-
-
12.5
-
ns
APB0 bus clock*2
tCYCP1
-
-
6.25
-
ns
APB1 bus clock*2
tCYCP2 - - 12.5 - ns APB2 bus clock*2
*1: For more information about each internal operating clock, see CHAPTER 2-1: Clock in FM4 Family Peripheral Manual Main
part (002-04856).
*2: For about each APB bus which each peripheral is connected to, see 8. Block Diagram in this dat a s heet.
0.8 × Vcc
tCYLH
0.8 × Vcc
0.2 × Vcc 0.2 × Vcc
0.8 × Vcc
PWLPWH tCF tCR
X0
Document Number: 002-04922 Rev .*B Page 67 of 128
MB9B560L Series
12.4.2 Sub Clock Input Characterist ics (VBAT = 2.7V to 5. 5V, VSS = 0V)
Parameter Symbol Pin
Name Conditions
Value
Unit Remarks
Min
Typ
Max
Input frequency 1/ tCYLL X0A,
X1A
- - 32.768 - kHz When crystal oscillator is
connected
-
32
-
100
kHz
When using external clock
Input clock cycle tCYLL - 10 - 31.25 μs When using external clock
Input clock pulse width -
P
WH
/t
CYLL
,
PWL/tCYLL
45 - 55 % When using external clock
In the case of 48 pi n P ackage, VBAT is VCC.
12.4.3 Built-in CR Osci llation Characteristics
Built-in High-Speed CR (VCC = 2.7V to 5.5V, V SS = 0V)
Parameter Symbol Conditions
Value
Unit Remarks
Min
Typ
Max
Clock frequency fCRH
TJ = -20°C to +105°C 3.92 4 4.08
MHz When trimming *1
TJ = - 40°C to +125°C 3.88 4 4.12
TJ = - 40°C to +125°C 3 4 5 When not trimming
Frequency
stabilization time
tCRWT - - - 30 μS *2
*1: In the case of us i ng the values in CR trimming area of Flash memory at shipment for frequenc y/temperature trimmin g.
*2: This is the time to s tabilize the fr equency of high-speed CR clock after setting trimmin g v al ue.
This period is able to use high-speed CR clock as source clock.
Built-in Low-Speed CR (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter Symbol Condition Value Unit Remarks
Min Typ Max
Clock frequency fCRL - 50 100 150 kHz
0.8 × Vcc
t
CYLL
0.8 × Vcc
0.2 × Vcc 0.2 × Vcc
0.8 × Vcc
P
WL
P
WH
X0A
V
BAT
V
BAT
V
BAT
VBAT
0.8 × VBAT
Document Number: 002-04922 Rev .*B Page 68 of 128
MB9B560L Series
12.4.4 Operating Conditions of Main PLL (In the Case of Using Main Clock for Input Clock of PLL)
(VCC = 2.7V to 5.5V, V SS = 0V)
Parameter Symbol Value Unit Remarks
Min Typ Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK 200 - - μs
PLL input clock frequency fPLLI 4 - 16 MHz
PLL multiplication rate - 13 - 80 multiplier
PLL macro oscillation clock frequency fPLLO 200 - 320 MHz
Main PLL clock frequency*2 fCLKPLL - - 160 MHz
*1: Tim e from when the PLL starts operatin g until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see CHPATER 2-1: Clock in FM4 Fam ily Peripheral Manual Main part
(002-04856).
12.4.5 Operating Conditions of USB PLL (In the Case of Using Main Clock for Input Clock of PLL)
(VCC = 2.7V to 5.5V, VSS = 0V)
Parameter Symbol Value Unit Remarks
Min Typ Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK 100 - - μs
PLL input clock frequency fPLLI 4 - 16 MHz
PLL multiplication rate - 13 - 80 multiplier
PLL macro oscillation clock frequency fPLLO 200 - 320 MHz
USB clock frequency*2 fCLKSPLL - - 48 MHz After the M frequency division
*1: Tim e from when the PLL starts operating until the os cillation stabilizes.
*2: For more information about USB clock, see CHAPTER 2-2: USB Clock Generation in FM4 F amily Peripheral Manual
Communication Macro part (002-04862).
12.4.6 Operating Conditi o ns of Main PLL (In the Case of Using Built-in High-Speed CR Clock for Input Clock of Main PLL)
(VCC = 2.7V to 5.5V, V SS = 0V)
Parameter Symbol Value Unit Remarks
Min Typ Max
PLL oscillation stabilization wait time*1
(LOCK UP time)
tLOCK 200 - - μs
PLL input clock frequency
fPLLI
3.8
4
4.2
MHz
PLL multiplication rate
-
50
-
75
multiplier
PLL macro oscillation clock frequency
fPLLO
190
-
320
MHz
Main PLL clock frequency*2
fCLKPLL
-
-
160
MHz
*1: Tim e from when the PLL starts operatin g until the oscillation stabilizes.
*2: For more inf ormation about Main PLL clock (CLKPLL), see CHAPTER 2-1: Clock in FM4 Family Peripheral Manual Main part
(002-04856).
Note:
− Make sure to input to the main PLL source c lock, the high-speed CR clock (CLKHC) that the frequency and temperature has
been trimmed.
Document Number: 002-04922 Rev .*B Page 69 of 128
MB9B560L Series
12.4.7 Reset Input Characteristics (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter Symbol Pin
Name Condition Value Unit Remarks
Min
Max
Reset input time tINITX INITX - 500 - ns
12.4.8 Power-on Reset Timing (VSS = 0V)
Parameter Symbol Pin
Name Conditions Value Unit Remarks
Min Typ Max
Power supply shut down time tOFF
VCC
- 50 - - ms *1
Power ramp rate dV/dt VCC: 0.2V to 2.70V 1.3 - 1000 mV/µs *2
Time until releasing Power-on reset tPRT - 0.33 - 0.60 ms
*1: VCC must be held below 0.2V for a minimum period of tOFF. Im pr oper initialization may occur if this condit ion is not met .
*2: This dV/dt characteristic is app l ied at the power-on of cold start (tOFF>50ms).
Note:
− tOFF must be satisfi ed. When tOFF cannot be s atisfied, assert externa l reset (INIT X) at power-up and at any brownout event.
Glossary
VDH: detection voltage of Low-Volt age detection r eset. See 12.8 Low-Voltage Detection Characteristics.
Document Number: 002-04922 Rev .*B Page 70 of 128
MB9B560L Series
12.4.9 GPIO Output Characterist ics (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter Symbol Pin Name Conditions
Value
Unit
Min
Max
Output frequency tPCYCLE Pxx*
VCC ≥ 4.5 V
-
50
MHz
VCC < 4.5 V - 32 MHz
*: GPIO is a target.
Pxx
tPCYCLE
Document Number: 002-04922 Rev .*B Page 71 of 128
MB9B560L Series
12.4.10 Base Timer Input Timing
Timer Input Timing (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter Symbol Pin Name Conditions
Value
Unit Remarks
Min Max
Input pulse width tTIWH,
tTIWL
TIOAn/TIOBn
(when using as
ECK, TIN)
- 2tCYCP - ns
Trigger Input Timing (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter Symbol Pin Name Conditions
Value
Unit Remarks
Min Max
Input pulse width tTRGH,
tTRGL
TIOAn/TIOBn
(when using as
TGIN)
- 2tCYCP - ns
Note:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see 8. Block Diagram in this data sheet.
tTIWH
VIHS VIHS VILS VILS
tTIWL
tTRGH
VIHS VIHS VILS VILS
tTRGL
ECK
TIN
TGIN
Document Number: 002-04922 Rev .*B Page 72 of 128
MB9B560L Series
12.4.11 CSIO/UART Timing
Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, VSS = 0V )
Parameter Symbol Pin
Name Conditions
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Min Max Min Max
Baud rate - - - - 8 - 8 Mbps
Serial clock cycle time
tSCYC
SCKx
Internal shift
clock operation
4tCYCP
-
4tCYCP
-
ns
SCK↓→SOT delay time tSLOVI
SCKx,
SOTx
- 30 + 30 - 20 + 20 ns
SIN→SCK↑
setup time
tIVSHI SCKx,
SINx
50 - 30 - ns
SCK↑→SIN hold time tSHIXI
SCKx,
SINx
0 - 0 - ns
Serial clock "L" pulse width
tSLSH
SCKx
External shift
clock
operation
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock "H" pulse width
tSHSL
SCKx
tCYCP + 10
-
tCYCP + 10
-
ns
SCK↓→SOT delay time tSLOVE
SCKx,
SOTx
- 50 - 30 ns
SIN→SCK↑
setup time
tIVSHE
SCKx,
SINx
10 - 10 - ns
SCK↑→SIN hold time tSHIXE SCKx,
SINx
20 - 20 - ns
SCK falling time
tF
SCKx
-
5
-
5
ns
SCK rising time
tR
SCKx
-
5
-
5
ns
Notes:
− The above charac teristics ap ply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connec ted to, see 8. Block Diagram in this data sheet.
− These character i s tics only gu ar antee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
− When the external load capacitance CL = 30 pF.
Document Number: 002-04922 Rev .*B Page 73 of 128
MB9B560L Series
MS bit = 0
MS bit = 1
t
SCYC
V
OH
V
OH
V
OL
V
OL
V
OL
V
IH
V
IL
V
IH
V
IL
t
SLOVI
t
IVSHI
t
SHIXI
tSLSH tSHSL
VIH
t
F
tR
VIH
VOH
VIH
VIL VIL
VOL
VIH
VIL VIH
VIL
t
SLOVE
tIVSHE tSHIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-04922 Rev .*B Page 74 of 128
MB9B560L Series
Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, V SS = 0V)
Parameter Symbol Pin
Name Conditions
VCC < 4.5 V
VCC ≥ 4.5 V
Unit
Min Max Min Max
Baud rate - - - - 8 - 8 Mbps
Serial clock cycle time tSCYC SCKx
Internal shift
clock operation
4tCYCP - 4tCYCP - ns
SCK↑→SOT delay time tSHOVI SCKx,
SOTx - 30 + 30 - 20 + 20 ns
SIN→SCK↓
setup time
tIVSLI
SCKx,
SINx
50 - 30 - ns
SCK↓→SIN hold time tSLIXI SCKx,
SINx
0 - 0 - ns
Serial clock "L" pulse width
tSLSH
SCKx
External shift
clock operation
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns
SCK↑→SOT delay time tSHOVE
SCKx,
SOTx
- 50 - 30 ns
SIN→SCK↓
setup time
tIVSLE SCKx,
SINx
10 - 10 - ns
SCK↓→SIN hold time tSLIXE
SCKx,
SINx
20 - 20 - ns
SCK falling time tF SCKx - 5 - 5 ns
SCK rising time tR SCKx - 5 - 5 ns
Notes:
− The above charac teristics ap ply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connec ted to, see 8. Block Diagram in this data sheet.
− These character i s tics only gu ar antee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
− When the external load capacitance CL = 30 pF.
Document Number: 002-04922 Rev .*B Page 75 of 128
MB9B560L Series
MS bit = 0
MS bit = 1
t
SCYC
V
OH
V
OH
V
OH
V
OL
V
OL
V
IH
V
IL
V
IH
V
IL
t
SHOVI
t
IVSLI
t
SLIXI
tSHSL tSLSH
VIH
tF
tR
VIH
VOH
VIL
VIL VIL
VOL
VIH
VIL VIH
VIL
tSHOVE
tIVSLE tSLIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-04922 Rev .*B Page 76 of 128
MB9B560L Series
Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, V SS = 0V)
Parameter Symbol Pin
Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit
Min Max Min Max
Baud rate - - - - 8 - 8 Mbps
Serial clock cycle time tSCYC SCKx
Internal shift
clock
operation
4tCYCP - 4tCYCP - ns
SCK↑→SOT delay time tSHOVI SCKx,
SOTx - 30 + 30 - 20 + 20 ns
SIN→SCK↓
setup time
tIVSLI
SCKx,
SINx
50 - 30 - ns
SCK↓→SIN hold time tSLIXI
SCKx,
SINx
0 - 0 - ns
SOT→SCK↓ delay time tSOVLI
SCKx,
SOTx
2tCYCP - 30 - 2tCYCP - 30 - ns
Serial clock "L" pulse width
tSLSH
SCKx
External shift
clock
operation
2tCYCP - 10
-
2tCYCP - 10
-
ns
Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns
SCK↑→SOT delay time tSHOVE SCKx,
SOTx
- 50 - 30 ns
SIN→SCK↓
setup time
tIVSLE
SCKx,
SINx
10 - 10 - ns
SCK↓→SIN hold time tSLIXE SCKx,
SINx
20 - 20 - ns
SCK falling time tF SCKx - 5 - 5 ns
SCK rising time tR SCKx - 5 - 5 ns
Notes:
− The above charac teristics ap ply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connec ted to, see 8. Block Diagram in this data sheet.
− These character i s tics only gu ar antee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
− When the external load capacitance CL = 30 pF.
Document Number: 002-04922 Rev .*B Page 77 of 128
MB9B560L Series
MS bit = 0
MS bit = 1
*: Changes when writing to TDR register
t
SOVLI
t
SCYC
t
SHOVI
V
OL
V
OL
V
OH
V
OH
V
OL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
t
IVSLI
t
SLIXI
tF tR
tSLSH tSHSL
tSHOVE
VIL VIL
VIH VIH VIH
VOH
*VOL VOH
VOL
VIH
VIL VIH
VIL
tIVSLE tSLIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-04922 Rev .*B Page 78 of 128
MB9B560L Series
Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, V SS = 0V)
Parameter Symbol Pin
Name Conditions VCC < 4.5 V VCC
≥
4.5 V Unit
Min Max Min Max
Baud rate - - - - 8 - 8 Mbps
Serial clock cycle time tSCYC SCKx
Internal shift
clock
operation
4tCYCP - 4tCYCP - ns
SCK↓→SOT delay time tSLOVI
SCKx,
SOTx
- 30 + 30 - 20 + 20 ns
SIN→SCK↑
setup time
tIVSHI
SCKx,
SINx
50 - 30 - ns
SCK↑→SIN hold time tSHIXI
SCKx,
SINx
0 - 0 - ns
SOT→SCK↑ delay time tSOVHI
SCKx,
SOTx
2tCYCP - 30 - 2tCYCP - 30 - ns
Serial clock "L" pulse width tSLSH SCKx
External shift
clock
operation
2tCYCP - 10 - 2tCYCP - 10 - ns
Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns
SCK↓→SOT delay time tSLOVE SCKx,
SOTx
- 50 - 30 ns
SIN→SCK↑
setup time
tIVSHE
SCKx,
SINx
10 - 10 - ns
SCK↑→SIN hold time tSHIXE SCKx,
SINx
20 - 20 - ns
SCK falling time tF SCKx - 5 - 5 ns
SCK rising time tR SCKx - 5 - 5 ns
Notes:
− The above charac teristics ap ply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connec ted to, see 8. Block Diagram in this data sheet.
− These character i s tics only gu ar antee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
− When the external load capacitance CL = 30 pF.
Document Number: 002-04922 Rev .*B Page 79 of 128
MB9B560L Series
MS bit = 0
MS bit = 1
tSCYC
tSLOVI
VOL
VOH VOH
VOH
VOL VOH
VOL
VIH
VIL VIH
VIL
tIVSHI tSHIXI
tSOVHI
tSHSL
tR tSLSH tF
tSLOVE
VIL VIL
VIL VIH VIH
VIH
VOH
VOL VOH
VOL
VIH
VIL VIH
VIL
tIVSHE tSHIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-04922 Rev .*B Page 80 of 128
MB9B560L Series
High-Speed Synchronous Serial (SPI = 0, SCINV = 0) (VCC = 2.7V to 5.5V, V SS = 0V)
Parameter Symbol Pin
Name Conditions VCC < 4.5V VCC ≥ 4.5V Unit
Min Max Min Max
Serial clock cycle time tSCYC SCKx
Internal shift
clock operation
4tCYCP - 4tCYCP - ns
SCK↓→SOT delay time tSLOVI SCKx,
SOTx -10 +10 -10 +10 ns
SIN→SCK↑
setup time tIVSHI SCKx,
SINx 14 - 12.5 - ns
12.5*
SCK↑→SIN hold time tSHIXI SCKx,
SINx 5 - 5 - ns
Serial clock "L" pulse width tSLSH SCKx
External shift
clock operation
2tCYCP – 5 - 2tCYCP – 5 - ns
Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns
SCK↓→SOT delay time tSLOVE SCKx,
SOTx - 15 - 15 ns
SIN→SCK↑
setup time tIVSHE SCKx,
SINx 5 - 5 - ns
SCK↑→SIN hold time tSHIXE SCKx, 5 - 5 - ns
SINx
SCK falling time tF SCKx - 5 - 5 ns
SCK rising time tR SCKx - 5 - 5 ns
Notes:
− The above charac teristics ap ply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connec ted to, see 8. Block Diagram in this data sheet.
− These character i s tics only gu ar antee the foll owing pins.
− No chip select: SIN0_1, SOT0_1, SCK0_1
− Chip select: SIN6_0, SOT6_0, SCK6_0, SCS6_0
− When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 002-04922 Rev .*B Page 81 of 128
MB9B560L Series
MS bit = 0
MS bit = 1
tSCYC
VOH
VOH
VOL
VOL
VOL
VIH
VIL
VIH
VIL
tSLOVI
tIVSHI tSHIXI
tSLSH tSHSL
VIH
t
F
tR
VIH
VOH
VIH
VIL VIL
VOL
VIH
VIL VIH
VIL
t
SLOVE
tIVSHE tSHIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-04922 Rev .*B Page 82 of 128
MB9B560L Series
High-Speed Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, V SS = 0V)
Parameter Symbol Pin
Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit
Min Max Min Max
Serial clock cycle time tSCYC SCKx
Internal shift
clock operation
4tCYCP - 4tCYCP - ns
SCK↑→SOT delay time tSHOVI SCKx,
SOTx -10 +10 -10 +10 ns
SIN→SCK↓
setup time tIVSLI SCKx,
SINx 14 - 12.5 - ns
12.5*
SCK↓→SIN hold time tSLIXI SCKx,
SINx 5 - 5 - ns
Serial clock "L" pulse width tSLSH SCKx
External shift
clock operation
2tCYCP – 5 - 2tCYCP – 5 - ns
Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns
SCK↑→SOT delay time tSHOVE SCKx,
SOTx - 15 - 15 ns
SIN→SCK↓
setup time tIVSLE SCKx,
SINx 5 - 5 - ns
SCK↓→SIN hold time tSLIXE SCKx,
SINx 5 - 5 - ns
SCK falling time tF SCKx - 5 - 5 ns
SCK rising time tR SCKx - 5 - 5 ns
Notes:
− The above charac teristics ap ply to CLK sync hron ous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connec ted to, see 8. Block Diagram in this data sheet.
− These character i s tics only gu ar antee the foll owing pins.
− No chip select: SIN0_1, SOT0_1, SCK0_1
− Chip select: SIN6_0, SOT6_0, SCK6_0, SCS6_0
− When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 002-04922 Rev .*B Page 83 of 128
MB9B560L Series
MS bit = 0
MS bit = 1
tSCYC
VOH VOH
VOH
VOL
VOL
VIH
VIL
VIH
VIL
tSHOVI
tIVSLI tSLIXI
t
SHSL
t
SLSH
V
IH
tF
tR
V
IH
V
OH
V
IL
V
IL
V
IL
V
OL
V
IH
V
IL
V
IH
V
IL
t
SHOVE
t
IVSLE
t
SLIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-04922 Rev .*B Page 84 of 128
MB9B560L Series
High-Speed Synchronous Serial (SPI = 1, SCINV = 0) (VCC = 2.7V to 5.5V, V SS = 0V)
Parameter Symbol Pin
Name Conditions VCC < 4.5 V VCC
≥
4.5 V Unit
Min Max Min Max
Serial clock cycle time tSCYC SCKx
Internal shift
clock operation
4tCYCP - 4tCYCP - ns
SCK↑→SOT delay time tSHOVI SCKx,
SOTx -10 +10 -10 +10 ns
SIN→SCK↓
setup time tIVSLI SCKx,
SINx 14 - 12.5 - ns
12.5*
SCK↓→SIN hold time tSLIXI SCKx,
SINx 5 - 5 - ns
SOT→SCK↓ delay time tSOVLI SCKx,
SOTx 2tCYCP – 10 - 2tCYCP – 10 - ns
Serial clock "L" pulse width tSLSH SCKx
External shift
clock operation
2tCYCP – 5 - 2tCYCP – 5 - ns
Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns
SCK↑→SOT delay time tSHOVE SCKx,
SOTx - 15 - 15 ns
SIN→SCK↓
setup time tIVSLE SCKx,
SINx 5 - 5 - ns
SCK↓→SIN hold time tSLIXE SCKx,
SINx 5 - 5 - ns
SCK falling time tF SCKx - 5 - 5 ns
SCK rising time tR SCKx - 5 - 5 ns
Notes:
− The above charac teristics ap ply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connec ted to, see 8. Block Diagram in this data sheet.
− These character i s tics only gu ar antee the foll owing pins.
− No chip select: SIN0_1, SOT0_1, SCK0_1
− Chip select: SIN6_0, SOT6_0, SCK6_0, SCS6_0
− When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 002-04922 Rev .*B Page 85 of 128
MB9B560L Series
MS bit = 0
MS bit = 1
*: Changes when writing to TDR register
t
SOVLI
t
SCYC
t
SHOVI
V
OL
V
OL
V
OH
V
OH
V
OL
V
OH
V
OL
V
IH
V
IL
V
IH
V
IL
t
IVSLI
t
SLIXI
tF tR
tSLSH tSHSL
tSHOVE
VIL VIL
VIH VIH VIH
VOH
*VOL VOH
VOL
VIH
VIL VIH
VIL
tIVSLE tSLIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-04922 Rev .*B Page 86 of 128
MB9B560L Series
High-Speed Synchronous Serial (SPI = 1, SCINV = 1) (VCC = 2.7V to 5.5V, V SS = 0V)
Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit
Min Max Min Max
Internal shift clock operation tSCYC SCKx
Internal shift
clock
operation
4tCYCP - 4tCYCP - ns
SCK↓→SOT delay time tSLOVI SCKx,
SOTx -10 +10 -10 +10 ns
SIN→SCK↑
setup time tIVSHI SCKx,
SINx 14 - 12.5 - ns
12.5*
SCK↑→SIN hold time tSHIXI SCKx,
SINx 5 - 5 - ns
SOT→SCK↑ delay time tSOVHI SCKx,
SOTx 2tCYCP – 10 - 2tCYCP – 10 - ns
Serial clock "L" pulse width tSLSH SCKx
External shift
clock
operation
2tCYCP – 5 - 2tCYCP – 5 - ns
Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns
SCK↓→SOT delay time tSLOVE SCKx,
SOTx - 15 - 15 ns
SIN→SCK↑
setup time tIVSHE SCKx,
SINx 5 - 5 - ns
SCK↑→SIN hold time tSHIXE SCKx,
SINx 5 - 5 - ns
SCK falling time tF SCKx - 5 - 5 ns
SCK rising time tR SCKx - 5 - 5 ns
Notes:
− The above charac teristics ap ply to CLK synchronous mode.
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connec ted to, see 8. Block Diagram in this data sheet.
− These character i s tics only gu ar antee the foll owing pins.
− No chip select: SIN0_1, SOT0_1, SCK0_1
− Chip select: SIN6_0, SOT6_0, SCK6_0, SCS6_0
− When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF)
Document Number: 002-04922 Rev .*B Page 87 of 128
MB9B560L Series
MS bit = 0
MS bit = 1
tSCYC
tSLOVI
VOL
VOH VOH
VOH
VOL VOH
VOL
VIH
VIL VIH
VIL
tIVSHI tSHIXI
tSOVHI
tSHSL
tR tSLSH tF
tSLOVE
VIL VIL
VIL VIH VIH
VIH
VOH
VOL VOH
VOL
VIH
VIL VIH
VIL
tIVSHE tSHIXE
SCK
SOT
SIN
SCK
SOT
SIN
Document Number: 002-04922 Rev .*B Page 88 of 128
MB9B560L Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL=1) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit
Min
Max
Min
Max
SCS↓→SCK↓setup time tCSSI Internal shift
clock operation
(*1)-20 (*1)+0 (*1)-20 (*1)+0 ns
SCK↑→SCS↑ hold time tCSHI (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns
SCS deselect time tCSDI (*3)-20+5tCYCP (*3)+20+5tCYCP (*3)-20+5tCYCP (*3)+20+5tCYCP ns
SCS↓→SCK↓setup time tCSSE
External shift
clock operation
3tCYCP+15 - 3tCYCP+15 - ns
SCK↑→SCS↑ hold time tCSHE 0 - 0 - ns
SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns
SCS↓→SOT delay time tDSE - 25 - 25 ns
SCS↑→SOT delay time tDEE 0 - 0 - ns
(*1): CSSU bit v al ue×serial c hip select t i m i ng operating clock cycle [ns]
(*2): CSHD bit value×serial chip select t i m i ng operating clock cycle [ns]
(*3): CSDS bit v al ue×serial c hip select t i m i ng operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connec ted to, see 8. Block Diagram in this data sheet.
− About CSSU, CSHD, CSDS, serial c hip select t i ming operating cl oc k, see FM4 Family Peripheral Manual.
− When the external load capacitance CL = 30 pF.
Document Number: 002-04922 Rev .*B Page 89 of 128
MB9B560L Series
MS bit = 0
MS bit = 1
tCSSItCSHI
tCSDI
tCSSE
t
CSHE
tCSDE
tDEE
tDSE
SCS
output
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
SCK
input
SOT
(SPI=0)
SOT
(SPI=1)
Document Number: 002-04922 Rev .*B Page 90 of 128
MB9B560L Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL=1) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit
Min
Max
Min
Max
SCS↓→SCK↑setup time tCSSI Internal shift
clock
operation
(*1)-20 (*1)+0 (*1)-20 (*1)+0 ns
SCK↓→SCS↑ hold time tCSHI (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns
SCS deselect time tCSDI (*3)-20+5tCYCP (*3)+20+5tCYCP (*3)-20+5tCYCP (*3)+20+5tCYCP ns
SCS↓→SCK↑setup time tCSSE
External shift
clock
operation
3tCYCP+15 - 3tCYCP+15 - ns
SCK↓→SCS↑ hold time tCSHE 0 - 0 - ns
SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns
SCS↓→SOT delay time tDSE - 25 - 25 ns
SCS↑→SOT delay time tDEE 0 - 0 - ns
(*1): CSSU bit value×serial chip select timing operating clock cycle [ns]
(*2): CSHD bit v al ue×serial c hip select t i ming operating c lock cycle [ns ]
(*3): CSDS bit v al ue×serial c hip select t i m i ng operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connec ted to, see 8. Block Diagram in this data sheet.
− About CSSU, CSH D, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main p art
(002-04856).
− When the external load capacitance CL = 30 pF.
Document Number: 002-04922 Rev .*B Page 91 of 128
MB9B560L Series
MS bit = 0
MS bit = 1
t
CSSI
t
CSHI
t
CSDI
tCSSE
tCSHE
tCSDE
tDEE
tDSE
SCS
output
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
SCK
input
SOT
(SPI=0)
SOT
(SPI=1)
Document Number: 002-04922 Rev .*B Page 92 of 128
MB9B560L Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 0, CSLVL=0) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit
Min Max Min Max
SCS↑→SCK↓setup time tCSSI Internal shift
clock
operation
(*1)-20 (*1)+0 (*1)-20 (*1)+0 ns
SCK↑→SCS↓ hold time tCSHI (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns
SCS deselect time tCSDI (*3)-20+5tCYCP (*3)+20+5tCYCP (*3)-20+5tCYCP (*3)+20+5tCYCP ns
SCS↑→SCK↓setup time tCSSE
External shift
clock
operation
3tCYCP+15 - 3tCYCP+15 - ns
SCK↑→SCS↓ hold time tCSHE 0 - 0 - ns
SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns
SCS↑→SOT delay time tDSE - 25 - 25 ns
SCS↓→SOT delay time tDEE 0 - 0 - ns
(*1): CSSU bit v al ue×serial c hip select t i m i ng operating clock cycle [ns]
(*2): CSHD bit v al ue×serial c hip select t i ming operating c lock cycle [ns ]
(*3): CSDS bit v al ue×serial c hip select t i m i ng operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connec ted to, see 8. Block Diagram in this data sheet.
− About CSSU, CSHD, CSDS, s er ial chip select t iming operating cloc k , see FM4 Family Peripheral Manual Main part
(002-04856).
− When the external load capacitance CL = 30 pF.
Document Number: 002-04922 Rev .*B Page 93 of 128
MB9B560L Series
MS bit = 0
MS bit = 1
t
CSSI
t
CSHI
t
CSDI
t
CSSE
t
CSHE
t
CSDE
t
DEE
t
DSE
SCS
output
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
SCK
input
SOT
(SPI=0)
SOT
(SPI=1)
Document Number: 002-04922 Rev .*B Page 94 of 128
MB9B560L Series
When Using High-Speed Synchronous Serial Chip Select (SCINV = 1, CSLVL=0) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter Symbol Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit
Min Max Min Max
SCS↑→SCK↑setup time tCSSI Internal shift
clock
operation
(*1)-20 (*1)+0 (*1)-20 (*1)+0 ns
SCK↓→SCS↓ hold time tCSHI (*2)+0 (*2)+20 (*2)+0 (*2)+20 ns
SCS deselect time tCSDI (*3)-20+5tCYCP (*3)+20+5tCYCP (*3)-20+5tCYCP (*3)+20+5tCYCP ns
SCS↑→SCK↑setup time tCSSE
External shift
clock
operation
3tCYCP+15 - 3tCYCP+15 - ns
SCK↓→SCS↓ hold time tCSHE 0 - 0 - ns
SCS deselect time tCSDE 3tCYCP+15 - 3tCYCP+15 - ns
SCS↑→SOT delay time tDSE - 25 - 25 ns
SCS↓→SOT delay time tDEE 0 - 0 - ns
(*1): CSSU bit v al ue×serial c hip select t i m i ng operating cloc k cycle [ns]
(*2): CSHD bit v al ue×serial c hip select t i ming operating c lock cycle [ns ]
(*3): CSDS bit v al ue×serial c hip select t i m i ng operating clock cycle [ns]
Notes:
− tCYCP indicates the APB bus clock cycle time.
About the APB bus number which UART is connec ted to, see 8. Block Diagram in this data sheet.
− About CSSU, CSH D, CSDS, serial chip select timing operating clock, see FM4 Family Peripheral Manual Main p art
(002-04856).
− When the external load capacitance CL = 30 pF.
Document Number: 002-04922 Rev .*B Page 95 of 128
MB9B560L Series
MS bit = 0
MS bit = 1
tCSSItCSHI
tCSDI
t
CSSE
t
CSHE
t
CSDE
t
DEE
t
DSE
SCS
output
SCK
output
SOT
(SPI=0)
SOT
(SPI=1)
SCS
input
SCK
input
SOT
(SPI=0)
SOT
(SPI=1)
Document Number: 002-04922 Rev .*B Page 96 of 128
MB9B560L Series
External Clock (EXT = 1): when in Asynchronous Mode Only (VCC = 2.7V to 5.5V, V SS = 0V)
Parameter Symbol Condition
Value
Unit Remarks
Min Max
Serial clock "L" pulse width
tSLSH
CL = 30 pF
tCYCP + 10
-
ns
Serial clock "H" pulse width
tSHSL
tCYCP + 10
-
ns
SCK falling time
tF
-
5
ns
SCK rising time
tR
-
5
ns
t
SHSL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
tR tF
t
SLSH
SCK
Document Number: 002-04922 Rev .*B Page 97 of 128
MB9B560L Series
12.4.12 External Input Timing (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter Symbol Pin Name Conditions
Value
Unit Remarks
Min Max
Input pulse
width tINH,
tINL
ADTG - 2tCYCP*1 - ns A/D converter trigger input
FRCKx
Free-run timer input clock
ICxx
Input capture
DTTIxX
-
2tCYCP*1
-
ns
Waveform generator
INT00 to INT31,
NMIX
-
2tCYCP + 100*1
-
ns
External interrupt,
NMI
500*2
-
ns
WKUPx
-
500*3
-
ns
Deep standby wake up
*1: tCYCP indicates the APB bus clock c ycle time except stop when in Stop m ode, in timer mode.
About the APB bus number which t he A/D converter, multi-function timer, external interrupt are connec ted to, see 8. Block
Diagram in this data sheet.
*2: When in Stop mode, in timer mode.
*3: When in deep st andby RTC mode, in Deep Standby Stop mode.
t
INH
t
INL
V
ILS
V
ILS
V
IHS
V
IHS
Document Number: 002-04922 Rev .*B Page 98 of 128
MB9B560L Series
12.4.13 Quadrature Position/Revolution Counter Timing (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter Symbol Conditions
Value
Unit
Min
Max
AIN pin H width
tAHL
-
2tCYCP* - ns
AIN pin L width
tALL
-
BIN pin H width
tBHL
-
BIN pin L width
tBLL
-
BIN rising time from
AIN pin H level
tAUBU PC_Mode2 or PC_Mode3
AIN falling time from
BIN pin H level
tBUAD PC_Mode2 or PC_Mode3
BIN falling time from
AIN pin L level
tADBD PC_Mode2 or PC_Mode3
AIN rising time from
BIN pin L level
tBDAU PC_Mode2 or PC_Mode3
AIN rising time from
BIN pin H level
tBUAU PC_Mode2 or PC_Mode3
BIN falling time from
AIN pin H level
tAUBD PC_Mode2 or PC_Mode3
AIN falling time from
BIN pin L level
tBDAD PC_Mode2 or PC_Mode3
BIN rising time from
AIN pin L level
tADBU PC_Mode2 or PC_Mode3
ZIN pin H width
tZHL
QCR:CGSC = 0
ZIN pin L width
tZLL
QCR:CGSC = 0
AIN/BIN rising and falling time from
determined ZIN level
tZABE QCR:CGSC = 1
Determined ZIN level from AIN/BIN rising
and falling time
tABEZ QCR:CGSC = 1
*: tCYCP indicates the AP B bus clock cycle time except st op when in Stop m ode, in timer mode.
About the APB bus number which Q uadrature Pos ition/Revol ution Counter is connected to, see 8. Block D iagram in this data
sheet.
AIN
BIN
t
AUBU
t
BUAD
t
ADBD
t
BDAU
t
AHL
t
ALL
t
BHL
t
BLL
Document Number: 002-04922 Rev .*B Page 99 of 128
MB9B560L Series
BIN
t
BUAU
t
AUBD
t
BDAD
t
ADBU
t
BHL
t
BLL
t
AHL
t
ALL
AIN
tZHL
t
ZLL
t
ZABE
t
ABEZ
ZIN
ZIN
AIN/BIN
Document Number: 002-04922 Rev .*B Page 100 of 128
MB9B560L Series
12.4.14 I2C Timing
Standard-Mode, Fast-Mode (VCC = 2. 7V to 5.5V, VSS = 0V)
Parameter Symbol Conditions
Standard-Mode
Fast-Mode
Unit Remarks
Min Max Min Max
SCL clock frequency
FSCL
CL = 30 pF,
R = (Vp/IOL)*1
0
100
0
400
kHz
(Repeated) START condition
hold time
SDA ↓ → SCL ↓
tHDSTA 4.0 - 0.6 - μs
SCL clock "L" width tLOW 4.7 - 1.3 - μs
SCL clock "H" width tHIGH 4.0 - 0.6 - μs
(Repeated) START condition
setup time
SCL ↑ → SDA ↓
tSUSTA 4.7 - 0.6 - μs
Data hold time
SCL ↓ → SDA ↓ ↑
tHDDAT 0 3.45*2 0 0.9*3 μs
Data setup time
SDA ↓ ↑ → SCL ↑
tSUDAT 250 - 100 - ns
STOP condition setup time
SCL ↑ → SDA ↑
tSUSTO 4.0 - 0.6 - μs
Bus free time between
"STOP condition" and
"START condition"
tBUF 4.7 - 1.3 - μs
Noise filter tSP
2 MHz ≤
tCYCP<40 MHz
2tCYCP*4 - 2tCYCP*4 - ns
*5
40 MHz ≤
tCYCP<60 MHz
4tCYCP*4 - 4tCYCP*4 - ns
60 MHz ≤
tCYCP<80 MHz
6tCYCP*4 - 6tCYCP*4 - ns
80 MHz ≤
tCYCP<100 MHz
8tCYCP*4 - 8tCYCP*4 - ns
100 MHz ≤
tCYCP<120 MHz
10tCYCP*4 - 10tCYCP*4 - ns
120 MHz ≤
tCYCP<140 MHz
12tCYCP*4 - 12tCYCP*4 - ns
140 MHz ≤
tCYCP<160 MHz
14tCYCP*4 - 14tCYCP*4 - ns
160 MHz ≤
tCYCP<180 MHz
16tCYCP*4 - 16tCYCP*4 - ns
*1: R and CL represent the pull-up r es i s tance and load capacitance of the SCL and SDA lines , respectively. Vp indicates the power
supply voltage of the pull-up resistance and IOL indicates V OL guaranteed current.
*2: The maximum tHDDAT must sati s fy that it does not extend at leas t "L" period ( tLOW) of devic e's SCL signal.
*3: A Fast-mode I2C bus devi ce can be used on a Standard-mode I2C bus system as long as the device satisfies t he requirement of
tSUDAT ≥ 250 ns.
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C i s connected to, see "8. Block Diagram" in this data sheet.
*5: The noise filter time can be change d by register sett i ngs.
Change the number of the noi se filter steps according to APB bus clock frequency.
Document Number: 002-04922 Rev .*B Page 101 of 128
MB9B560L Series
Fast Mode Plus (Fm+) (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter Symbol Conditions
Fast Mode Plus
(Fm+)*
6
Unit Remarks
Min Max
SCL clock frequency
FSCL
CL = 30 pF,
R = (Vp/IOL)*1
0
1000
kHz
(Repeated) START condition hold time
SDA ↓ → SCL ↓
tHDSTA 0.26 - μs
SCL clock "L" width
tLOW
0.5
-
μs
SCL clock "H" width
tHIGH
0.26
-
μs
SCL clock frequency
tSUSTA
0.26
-
μs
(Repeated) START condition hold time
SDA ↓ → SCL ↓
tHDDAT 0 0.45*2, *3 μs
Data setup time
SDA ↓ ↑ → SCL ↑
tSUDAT 50 - ns
STOP condition setup time
SCL ↑ → SDA ↑
tSUSTO 0.26 - μs
Bus free time between
"STOP condition" and
"START condition"
tBUF 0.5 - μs
Noise filter tSP
60 MHz ≤
tCYCP<80 MHz
6 tCYCP*4 - ns
*5
80 MHz ≤
tCYCP<100 MHz
8 tCYCP*4 - ns
100 MHz ≤
tCYCP<120 MHz
10 tCYCP*4 - ns
120 MHz ≤
tCYCP<140 MHz
12 tCYCP*4 - ns
140 MHz ≤
tCYCP<160 MHz
14 tCYCP*4 - ns
160 MHz ≤
tCYCP<180 MHz
16 tCYCP*4 - ns
*1: R and CL represent the pull-up r es i s tance and load capacitance of the SCL and SDA lines , respectively. Vp indicates the power
supply voltage of the pull-up resistance and IOL indicates V OL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of dev i c e's SCL signal.
*3: A Fast-mode I2C bus devi ce can be used on a Standard-mode I2C bus system as long as the device satisfies t he requirement of
"tSUDAT ≥ 250 ns".
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see 8. Block Diagram in this dat a sheet.
To use fast mode plus (Fm+), set t he per i pheral bus cl ock at 64 MHz or more.
*5: The noise filter time can be change d by register sett i ngs.
Change the number of the noi se filter steps according to APB bus clock frequency.
*6: When using fast mode plus (F m+), set the I/O pin to the mode corres ponding to I2C Fm+ in the EPFR register. See CHAPTER
12: I/O Port in FM4 Family Peripheral Manual Main part (002-04856) for the details.
t
LOW
t
HDSTA
t
HDDAT
t
HIGH
t
SUDAT
t
SUSTA
t
HDSTA
t
SP
t
SUSTO
t
BUF
SDA
SCL
Document Number: 002-04922 Rev .*B Page 102 of 128
MB9B560L Series
12.4.15 JTAG Timing (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter Symbol Pin Name Conditions Value Unit Remarks
Min Max
TMS, TDI setup time tJTAGS TCK,
TMS, TDI VCC ≥ 4.5 V 15 - ns
VCC < 4.5 V
TMS, TDI hold time tJTAGH TCK,
TMS, TDI VCC ≥ 4.5 V 15 - ns
VCC < 4.5 V
TDO delay time tJTAGD TCK,
TDO
VCC ≥ 4.5 V
-
25
ns
VCC < 4.5 V - 45
Note:
− When the external load capacitance CL= 30 pF.
VOH
VOH
VOL
VOL
VOH
VOL
VOH
VOL
tJTAGS
tJTAGD
tJTAGH
TCK
TMS/TDI
TDO
Document Number: 002-04922 Rev .*B Page 103 of 128
MB9B560L Series
12.5 12-bit A/D Converter
Electrical Characteristic s for the A/D Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = AVRL = 0V)
Parameter Symbol Pin Name Value Unit Remarks
Min
Typ
Max
Resolution
-
-
-
-
12
bit
Integral Nonlinearity
-
-
-4.5
-
+4.5
LSB
AVRH =
2.7 V to 5.5 V
Differential Nonlinearity
-
-
-2.5
-
+2.5
LSB
Zero transition voltage
VZT
AN00 to AN14
-15
-
+15
mV
Full-scale transition voltage
VFST
AN00 to AN14
AVRH - 15
-
AVRH + 15
mV
Conversion time - - 0.5*1 - - μs AVCC ≥ 4.5V
Sampling time Ts - *2 - 10 μs AVCC ≥ 4.5V
*2 - AVCC < 4.5V
Compare clock cycle*3 Tcck - 25 - 1000 ns AVCC ≥ 4.5V
50 - 1000 AVCC < 4.5V
State transition time to
operation permission Tstt - - - 1.0 μs
Power supply current (analog
+ digital)
- AVCC
-
0.69
0.92
mA
A/D 1 unit operation
-
0.3
12
μA
When A/D stop
Reference power supply
current
(AVRH) - AVRH - 1.1 1.97 mA
A/D 1unit operation
AVRH=5.5 V
0.2 4.2 μA When A/D stop
Analog input capacity CAIN - - - 10 pF
Analog input resistance RAIN - - -
1.2
kΩ
AVCC ≥ 4.5 V
1.8
AVCC < 4.5 V
Interchannel disparity
-
-
-
-
4
LSB
Analog port input leak current
-
AN00 to AN14
-
-
5
μA
Analog input voltage
-
AN00 to AN14
AVSS
-
AVRH
V
Reference voltage - AVRH
4.5
-
AVCC
V
Tcck < 50 ns
2.7
-
AVCC
Tcck ≥ 50 ns
*1: The conversion tim e i s the value of sampling time (Ts ) + compare time ( Tc).
The conditio n of the minimum conversion time is when the value of sampl ing time: 150 ns, the value of compare time: 350 ns
(AVCC ≥ 4.5 V). Ensure that it satisfies the value of sampling t i m e (Ts) and compare clock cycle (Tcck). For setting*4 of s ampling
time and comp are clock cycl e, see CHAPTER 1-1: A/D Converter in FM 4 Family Peripheral Manual Analog macro part
(002-04860). The register set ting of the A/D Converter is reflected by the peripheral clock timing. The sampling and com pare
clock are set at Base clock (HCLK).
*2: A necessary sampling tim e c hanges by external impedance. Ensure that it set the sam pl ing time to sati s fy (Equation 1) .
*3: The compare time ( Tc) is the value of ( E quation 2).
*4: The register setting of the A /D Converter is reflected by the timing of t he APB bus clock. The sampling clock and compare clock
are set in base clock (HCLK). About the APB bus number which t he A/D Converter is connec ted to, see 8. Block Diagram in this
data sheet.
Document Number: 002-04922 Rev .*B Page 104 of 128
MB9B560L Series
(Equation 1) Ts ≥ (RAIN + Rext ) × CAIN × 9
Ts: Sampling time
RAIN: Input resistance of A/D = 1.2 kΩ at 4.5 V < AVCC < 5.5 V
Input resistance of A/D = 1.8 kΩ at 2.7 V < AVCC < 4.5 V
CAIN: Input capacity of A/D = 10 pF at 2.7 V < AVCC < 5.5 V
Rext: O utput impedanc e of external circuit
(Equation 2) Tc = Tcck × 14
Tc: Compare time
Tcck: Compare clock cycle
CAIN
Analog signa l
source
AN00 to AN14
Analog input pin Comparator
Rext
RAIN
Document Number: 002-04922 Rev .*B Page 105 of 128
MB9B560L Series
Definition of 12-bit A/D Converter Terms
• Resolution: Analog variat i on that is recognized by an A/D converter.
• Integral Nonl inearity: Deviation of the lin e between the zer o-transition p oi nt (0b000000000000 ←→ 0b000000000001)
and the full-scale transiti on point (0b111111111110 ←→ 0b111111111111) from the actual conversion
characteristics.
• Differential Nonlinearity: Deviation from the ide al value of the input voltage that i s required to change the out put code by
1 LSB.
Integral Nonlinearity of digital output N =
VNT - {1LSB × (N - 1) + V ZT}
[LSB]
1LSB
Differential Nonlinearity of digital output N =
V(N + 1) T - VNT
- 1 [LSB]
1LSB
1LSB =
VFST - VZT
4094
N: A/D converter digital output v alue.
VZT: Voltage at which the digital output changes f rom 0x000 to 0x001.
VFST: Voltage at whic h the digital out put changes from 0xFFE to 0 xFFF.
VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN.
Integral Nonlinearity
Differential Nonlinearity
Digital outp ut
Digital outp ut
Actual conversion
characteristics
Actual conversion
characteristics
Ideal characteristics
(Actually-
measured
value)
Actual conversion
characteristics
Actual conversion characteristics
(Actually-measured
value)
(Actually-measured value)
Ideal characteristics
(Actually-measured
value)
Analog input
Analog input
(Actually-measured
value)
0x001
0x002
0x003
0x004
0x
FFD
0xFFE
0xFFF
AVss
AVRH
AVss
AVRH
0x(N
-2)
0x(N
-1)
0x(N+1)
0xN
{1 LSB(N
-1) + VZT}
V
NT
V
FST
V
ZT
V
NT
V
(N+1)T
Document Number: 002-04922 Rev .*B Page 106 of 128
MB9B560L Series
12.6 12-bit D/A Converter
Electrical Characteristics for the D/A Converter (VCC = AVCC = 2.7V to 5.5V, VSS = AVSS = 0V)
Parameter Symbol Pin Name
Value
Unit Remarks
Min
Typ
Max
Resolution
-
DAx
-
-
12
bit
Conversion time
tc20
0.56
0.69
0.81
μs
Load 20pF
tc100
2.79
3.42
4.06
μs
Load 100pF
Integral Nonlinearity*
INL
-16
-
+16
LSB
Differential Nonlinearity*
DNL
-0.98
-
+1.5
LSB
Output voltage offset VOFF
-
-
10.0
mV
When setting 0x000
-20.0
-
+1.4
mV
When setting 0xFFF
Analog output impedance RO
3.10
3.80
4.50
kΩ
D/A operation
2.0
-
-
MΩ
When D/A stop
Power supply current* IDDA AVCC
260
330
410
μA
D/A 1unit operation AVCC=3.3 V
400
519
620
μA
D/A 1unit operation AVCC=5.0 V
IDSA - - 14 μA When D/A stop
*: During no load
Document Number: 002-04922 Rev .*B Page 107 of 128
MB9B560L Series
12.7 USB Characteristics
(VCC = 2.7V to 5.5V, US B VCC = 3.0V to 3.6V, VSS = 0V)
Parameter Symbol Pin Name Conditions
Value
Unit Remarks
Min Max
Input
character
-istics
Input H level voltage VIH
UDP0,UDM0
- 2.0 USBVCC + 0.3 V *1
Input L level voltage VIL - VSS - 0.3 0.8 V *1
Differential input
sensitivity
VDI - 0.2 - V *2
Different common mode
range
VCM - 0.8 2.5 V *2
Output
character
-istics
Output "H" level voltage VOH
External pull-down
resistance = 15 kΩ
2.8 3.6 V *3
Output "L" level voltage VOL
External pull-up
resistance = 1.5 kΩ
0.0 0.3 V *3
Crossover voltage
VCRS
-
1.3
2.0
V
*4
Rising time
tFR
Full-Speed
4
20
ns
*5
Falling time
tFF
Full-Speed
4
20
ns
*5
Rising/falling time
matching
tFRFM Full-Speed 90 111.11 % *5
Output impedance
ZDRV
Full-Speed
28
44
Ω
*6
Rising time
tLR
Low-Speed
75
300
ns
*7
Falling time
tLF
Low-Speed
75
300
ns
*7
Rising/falling time
matching
tLRFM Low-Speed 80 125 % *7
*1: The switching thr eshold voltage of Single-End-Receiver of USB I/O buffer is set as within VIL (Max) = 0.8 V, VIH (Min) = 2.0 V
(TTL input standard).
There are some hysteresises to lower noise s ensitivity.
*2: Use differential-Receiver t o r eceive USB differential data signa l.
Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is within 0.8 V to 2.5 V to the local
ground refer ence level.
Above voltag e range is the common mode input v ol tage range.
Common mode input voltage [V]
0.2
0.8
1.0
2.5
Minimum differential input
sensitivity [V]
Document Number: 002-04922 Rev .*B Page 108 of 128
MB9B560L Series
*3: The output drive capab i li ty of the driv er is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and 2.8 V or above (to the
VSS and 1.5 kΩ load) at High-State (V OH).
*4: The cross voltage of the external differential output signal (D + /D −) of USB I/O buffer is within 1.3 V to 2.0 V.
*5: They indicate ris i ng time (Trise) and falling time (Tfall) of the full-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
For full-speed buffer, Tr/Tf ratio is regu lated as withi n ± 10% to minimize RFI emission.
Max 2.0V
D+
D-
Min 1.3V
Rs=27Ω
Full-speed Buffer
TxD+
TxD-
3-State Enable
Rs=27Ω
CL=50pF
CL=50pF
D+ 90%
Trise Tfall
90%
10%10%
D-
V
CRS
specified range
Rising time
Falling time
Document Number: 002-04922 Rev .*B Page 109 of 128
MB9B560L Series
*6: USB Full-speed connection is performed via twist pair cable shield with 90 Ω ± 15% characteristic impedance (Differential Mode).
USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So, discrete series resistor (Rs)
addition is def ined in order to satisfy the above definiti on and keep bal ance.
When using thi s USB I/O, use it with 25 Ω to 30 Ω (recommendation v alue 27 Ω) Series resistor Rs.
Rs series resistor 25 Ω to 30 Ω
Series resistor of 27 Ω (recommendation val ue) must be added.
And, use "resistance with an uncertainty of 5% by E24 sequence".
*7: They indicate ris ing time (Trise) and falling t i m e (Tfall) of the low-speed differenti al data signa l.
They are defined by the time between 10% and 90% of the output signal voltage.
See Low-Speed Load (Complianc e Load) for conditions of external load.
Rs
Full-speed Buffer
TxD+
TxD-
3-State Enable
Rs
D+ 90%
Trise Tfall
90%
10%10%
D-
Mount it as exter nal resistance.
28Ω to 44Ω Equiv. Imped.
28Ω to 44Ω Equiv. Imped.
Rising time Falling time
Document Number: 002-04922 Rev .*B Page 110 of 128
MB9B560L Series
Low-Speed Load (Upstream Port Load) - Reference 1
Low-Speed Load (Downstream Port Load) - Reference 2
Low-Speed Load (Compli ance Load)
Rs=27Ω
Low-speed Buffer
TxD+
TxD-
3-State Enable
Rs=27Ω
Rpd
Rpd
Rpd=15kΩ
Rs=27Ω
Low-speed Buffer
TxD+
TxD-
3-State Enable
Rs=27Ω
Rpu=1.5kΩ
VTERM=3.6V
Rpu
VTERM
Rs=27Ω
Low-speed Buffer
TxD+
TxD-
3-State Enable
Rs=27Ω
C
L
= 50pF to 150pF
CL = 50pF to 150pF
CL =200pF to
600pF
CL =200pF to
600pF
CL = 200pF to 450pF
CL = 200pF to 450pF
Document Number: 002-04922 Rev .*B Page 111 of 128
MB9B560L Series
12.8 Low-Voltage Detection Characteristics
12.8.1 Low-Voltage Detection Reset
Parameter Symbol Conditions
Value
Unit Remarks
Min Typ Max
Detected voltage
VDL
-
2.25
2.45
2.65
V
When voltage drops
Released voltage
VDH
-
2.30
2.50
2.70
V
When voltage rises
12.8.2 Interrupt of Low-Voltage Detection
Parameter Symbol Conditions
Value
Unit Remarks
Min Typ Max
Detected voltage
VDL
SVHI = 00111
2.58
2.8
3.02
V
When voltage drops
Released voltage
VDH
2.67
2.9
3.13
V
When voltage rises
Detected voltage VDL SVHI = 00100 2.76 3.0 3.24 V When voltage drops
Released voltage
VDH
2.85
3.1
3.34
V
When voltage rises
Detected voltage VDL SVHI = 01100 2.94 3.2 3.45 V When voltage drops
Released voltage
VDH
3.04
3.3
3.56
V
When voltage rises
Detected voltage VDL SVHI = 01111 3.31 3.6 3.88 V When voltage drops
Released voltage
VDH
3.40
3.7
3.99
V
When voltage rises
Detected voltage VDL SVHI = 01110 3.40 3.7 3.99 V When voltage drops
Released voltage
VDH
3.50
3.8
4.10
V
When voltage rises
Detected voltage VDL SVHI = 01001 3.68 4.0 4.32 V When voltage drops
Released voltage
VDH
3.77
4.1
4.42
V
When voltage rises
Detected voltage VDL SVHI = 01000 3.77 4.1 4.42 V When voltage drops
Released voltage
VDH
3.86
4.2
4.53
V
When voltage rises
Detected voltage VDL SVHI = 11000 3.86 4.2 4.53 V When voltage drops
Released voltage
VDH
3.96
4.3
4.64
V
When voltage rises
LVD stabilization wait time TLVDW - - - 4480×
tCYCP* μs
*: tCYCP indicates the APB2 bus clock cycle time.
Document Number: 002-04922 Rev .*B Page 112 of 128
MB9B560L Series
12.9 MainFlash Memory Write/Erase Characteristics (VCC = 2.7V to 5.5V)
Parameter
Value
Unit Remarks
Min Typ Max
Sector erase
time Large Sector - 0.7 3.7 s Includes write time prior to internal erase
Small Sector 0.3 1.1
Half word
(16-bit)
write time
Write cycles
< 100 times
- 12 100
μs Not including system-level overhead time
Write cycles >
100 times
200
Chip erase time - 8.0 38.4 s Includes write time prior to internal erase
Write cycles and data h old time
Erase/Write Cycles (Cycle) Data Hold Time (Year)
1,000 20 *
10,000 10 *
100,000 5 *
*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test result
into average temperature val ue at +85°C).
12.10 WorkFlash Memory Write/ E r ase Characteristics (VCC = 2.7V to 5.5V)
Parameter
Value
Unit Remarks
Min Typ Max
Sector erase time
-
0.3
1.5
s
Includes write time prior to internal erase
Half word (16-bit)
write time - 20 200 μs Not including system-level overhead time
Chip erase time - 1.2 6 s Includes write time prior to internal erase
Write cycles and data h old time
Erase/Write Cycles (Cycle) Data Hold Time (Year)
1,000 20 *
10,000 10 *
100,000 5 *
*: This value comes from the technology qualification (using Arrhenius equation to translate high temperature acceleration test result
into average temperature val ue at +85°C).
Document Number: 002-04922 Rev .*B Page 113 of 128
MB9B560L Series
12.11 Standby Recovery Time
12.11.1 Recovery Cause: Interrupt/WKUP
The time from recovery cause reception of the internal circuit to the program operation star t is shown.
Recovery Count Time (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter Symbol Value Unit Remarks
Typ Max*
Sleep mode
Ticnt
HCLK×1 μs
High-speed CR Timer mode
Main Timer mode
PLL Timer mode
40 80 μs
Low-speed CR timer mode 450 900 μs
Sub timer mode 896 1136 μs
RTC mode
stop mode
(High-speed CR /Main/PLL run mode
return)
316 581 μs
RTC mode
stop mode
(Low-speed CR/sub run mode return)
270 540 μs
Deep standby RTC mode
Deep standby stop mode
365 667 μs
without RAM
retention
365 667 μs
with RAM
retention
*: The maximum value depends on the built-in CR accur acy.
Example of Standby Recovery Operation (when in External Interrupt Recovery*)
Ext.INT
Ticnt
Interrupt factor
accept
CPU
Operation Start
Active
Interrupt factor
clear by CPU
*: External interrupt is set to det ecting fall ed ge.
Document Number: 002-04922 Rev .*B Page 114 of 128
MB9B560L Series
Example of Standby Recovery Operation (when in Internal Resource Interrupt Recovery*)
Internal
Resource INT
Ticnt
Interrupt factor
accept
CPU
Operation Start
Active
Interrupt factor
clear by CPU
*: Depending on the standby mode, interrupt from the internal resource is not included in the recovery cause.
Notes:
− The return factor is different in each Low-P ower consu mpt ion modes.
See CHAPTER 6: Low Power Consumption Mode and O perations of Standby Modes in FM4 Family Peripheral Manual Main
part (002-04856).
− When interrupt recoveries, the operation mode that CPU r ecoveries depend on the stat e before the Low-Pow er consumption
mode transiti on. See CHAPTER 6: Low Power Consumption M ode in FM4 Family Peripheral Manual Main part (002-04856).
Document Number: 002-04922 Rev .*B Page 115 of 128
MB9B560L Series
12.11.2 Recovery Cause: Reset
The time fr om reset release to the program oper ation start i s shown.
Recovery Count Time (VCC = 2.7V to 5.5V, VSS = 0V)
Parameter Symbol Value Unit Remarks
Typ Max*
Sleep mode
Trcnt
155 266 μs
High-speed CR timer mode
Main timer mode
PLL timer mode
155 266 μs
Low-speed CR timer mode 315 567 μs
Sub timer mode 315 567 μs
RTC mode
Stop mode
315 567 μs
Deep standby RTC mode
Deep standby stop mode
336 667 μs
without RAM
retention
336 667 μs
with RAM
retention
*: The maximum value depends on the built-in CR accuracy.
Example of Standby Recovery Operation (when in INITX Recovery)
INITX
Trcnt
Internal RST
CPU
Operation Start
RST Active Release
Document Number: 002-04922 Rev .*B Page 116 of 128
MB9B560L Series
Example of Standby Recovery Operation (when in Internal Resource Reset Recovery*)
Internal
Resource RST
Trcnt
Internal RST
CPU
Operation Start
RST Active Release
*: Depending on the standby mode, the reset iss ue from the internal resource is not include d i n the recover y cause.
Notes:
− The return factor is different in each Low-P ower consu mpt ion modes.
See CHAPTER 6: Low Power Consumption Mode and O perations of Standby Modes in FM4 Family Peripheral Manual Main
part (002-04856).
− The time durin g the power-on reset/ low-voltage det ec tion reset i s excluded to t he recovery source. See (6) Power-on Reset
Timing in 12.4 AC Characteristics in 12. Electrical Characteristics for the detai l on the time during the power-on
reset/low-v ol tage detection reset.
− When in recovery from reset, CPU changes to the high-speed CR run mode. When using the main clock or the PLL clock, it is
necessary to add the main cloc k oscillation stabilization wait time or the main PLL clock st abi lization wait time.
− The internal re source reset m eans the watch dog reset and t he CSV reset.
Document Number: 002-04922 Rev .*B Page 117 of 128
MB9B560L Series
13. Ordering Information
Part Number Package
MB9BF564LPMC1
Plastic・LQFP (0.5mm pitch), 64 pin
(LQD064)
MB9BF565LPMC1
MB9BF566LPMC1
MB9BF564LPMC
Plastic・LQFP (0.65mm pitch), 64 pin
(LQG064)
MB9BF565LPMC
MB9BF566LPMC
MB9BF564KPMC
Plastic・LQFP (0.5mm pitch), 48 pin
(LQA048)
MB9BF565KPMC
MB9BF566KPMC
MB9BF564LQN
Plastic・QFN (0.5mm pitch), 64 pin
(VNC064)
MB9BF565LQN
MB9BF566LQN
MB9BF564KQN
Plastic・QFN (0.5mm pitch), 48 pin
(VNA048)
MB9BF565KQN
MB9BF566KQN
Document Number: 002-04922 Rev .*B Page 118 of 128
MB9B560L Series
002-11499 **
14. Package Dimensions
Package Type
Package Code
LQFP 64pin (0.5mm pitch)
LQD064
DIM EN SIO NS
SYMBOL M IN. NOM . MAX.
07.1A
A1 0.000.20
b0.150.2
c0.090.20
D12.00 BSC.
D1 10.00 BSC.
e 0.50 BSC
E
E1
L0.450.600.75
L1 0.300.500.70
12.00 BSC.
10.00 BSC.
D1
D
e
116
64
4
57
E
E1
4
5
7
3
6
3
0.2 0 C A-B D
b
0.1 0CA-B D
0.0 8 C A-B D
8
7
5
2
A
A1
0.25
10
b
SECTION A -A '
c
9
L1 L
2
A
A'
SEATING
PLAN E
0.0 8C
SID E VIEW
TOP VIEW
BOTTOM VIEW
17
32
33
48
49
1
16
17
32
33 48
64
49
PACKAGE OUTLIN E, 64 LEAD LQ FP
10.0X10.0X1.7 MM LQD064 Rev**
Document Number: 002-04922 Rev .*B Page 119 of 128
MB9B560L Series
002-13881 **
Package Type
Package Code
LQFP 64pin (0.65mm pitch)
LQG064
D IM EN SI ON
SYM BOL M IN. NOM . M AX.
A1.70
A1 0.000.20
b 0.27 0.32 0.37
c 0.09 0.20
D14.00 BSC
D1 12.00 BSC
e0.65 BSC
E
E1
L0.450.600.75
L1 0.300.500.70
14.00 BSC
12.00 BSC
0° 8°θ
D1
D
e
116
64
EE1
4
5
7
4
57
3
3
0.20 C A-B D
b
0.10 CA-B D
0.13 C A-B D
8
7
5
2
2
0.10 C
A
A'
SEATI N G
PLA N E
b
SEC TION A -A'
c
9
θ
A
A1
0.2 510
L1 L
SIDE VIEW
TOP VIEW
BOTTOM VIEW
17
32
3348
49
1
16
17
32
64
49
8433
12.0X12.0X1.7 MMLQG064 REV**
PACKAGE OUTLIN E, 64 LEA D LQFP
Document Number: 002-04922 Rev .*B Page 120 of 128
MB9B560L Series
002-13731 **
Package Type
Package Code
LQFP 48pin (0.5mm pitch)
LQA048
DIM ENSI ON S
SYM BOL M IN . N OM . M AX.
A1.70
A1 0.00 0 .20
b 0.15 0.27
c 0.09 0.20
D 9.00 BSC
D1 7.00 BSC
e0.50 BSC
E
E1
L0.45 0.60 0 .75
L1 0.30 0.50 0.70
9.00 BSC
7.00 BSC
0° 8°
θ
D1
D
e
112
48
EE1
4
5
7
4
57
3
0.20 C A-B D
3
b
0.10 C A-B D
0.80 C A-B D
8
7
5
2
2
A
A'
SEATING
PLA N E
θ
A
A10.25
10
b
SECTION A-A'
c
9
L1 L
6
0.80 C
1
48
13
24
36 25
37
12
13
24
25 36
37
7.0X7.0X1.7 MM LQA048 REV**
PACKAGE OUTLIN E, 48 LEA D LQFP
Document Number: 002-04922 Rev .*B Page 121 of 128
MB9B560L Series
002-13234 **
DIMENSIONS
NOM.MIN.
b
E
5.50 BSC
7.00 BSC
D
A
1
A
7.00 BSC
0.00
SYMBOL
MAX.
0.90
0.05
2. DIMENSIONING AND TOLERANCINC CONFORM S TO ASME Y14.5-1994.
3. N IS THE TOTAL NUM BER OF TERMINALS.
4. DIMENSION "b "APPLIES TO M ETALLIZED TERMINAL AND ISM EA SU RE
D
BETW EEN 0.15 AND 0.30m m FROM TERM INAL TIP.IF THE TERMINALHAS
THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMIN AL. THE
DIMENSION "b"SHOULD NOT BE MEASURED IN THAT RADIUSAREA.
5. ND REFER TO THE NUM BER OF TERM INALS ON D OR E SID E.
6. MAX. PACKAGE W ARPAGE IS 0.05mm.
1. ALL DIMENSIONS ARE IN M ILLIM ETERS
.
0.50 BSC
L
0.20 0.25 0.30
E
D2
25.50 BSC
e
R0.20 REF
7. MAXIMUM ALLOW ABLE BURRS IS 0.076m m IN ALL DIRECTIONS.
8. PIN #1 ID ON TOP WILL BE LOCATEDW ITHIN INDICA TEDZONE.
9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT
SINK SLUG AS W ELL AS THE TERM INALS.
0.40
0.35 0.45
NOTE
10. JEDEC SPEC IFICATIONNO . REF : N/A
SIDE VIEW
BOTTOM VIEW
TOP VIEW
D
A
E
B
0.10 C
2X
0.10 C
2X
0.10 C
A
A1
0.05C
C
SEATING PLANE
D2
E2
0.10 C A B
0.10C A B
1
48
eb
0.10 C A B
0.05 C
R
( N D -1 )× e
INDEX MARK
8
4
5
9
L
912
13
24
3625
37
PACKAGE OUTLINE, 48 LEAD QFN
7.0X7.0X0 .9 MMVNA048 5.5X5.5 MMEPA D (SAW N) REV**
Package Type
Package Code
QFN 64pin (0.5mm pitch)
VNC064
Document Number: 002-04922 Rev .*B Page 122 of 128
MB9B560L Series
002-15528 **
Package Type
Package Code
QFN 48pin (0.5mm pitch)
VNA048
DIMENSIONS
NOM.MIN.
b
E
5.50 BSC
7.00 BSC
D
A
1
A
7.00 BSC
0.00
SYMBOL
MAX.
0.90
0.05
2. DIM ENSIONING AND TOLERANCINC CONFORM S TO ASM E Y14.5-1994.
3. N IS THE TOTAL NUM BER OF TERM INALS.
4. DIMENSION "b "APPLIES TO METALLIZED TERM INAL AND IS M EA SU RED
BETW EEN 0.15 AND 0.30m m FROM TERM INAL TIP.IF THE TERM INALHAS
THE OPTIONAL RADIUSON THE OTHER END OF THE TERMIN AL. THE
DIMENSION "b "SHOULD NOT BE MEASURED IN THAT RADIUSAREA.
5. ND REFER TO THE NUMBER OF TERM INALS ON D OR E SID E.
6. MAX. PACKAGE W ARPAGE IS0.05mm.
1. ALL DIM ENSIONS ARE IN M ILLIM ETERS.
0.50 BSC
L
0.20 0.25 0.30
E
D2
25.50 BSC
e
R0.20 REF
7. MAXIMUM ALLOW ABLE BURRS IS 0.076m m IN ALL DIRECTIONS.
8. PIN #1 ID ON TOP WILL BE LOCATEDW ITHIN INDICA TEDZONE.
9. BILATERAL COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT
SINK SLUG AS W ELL AS THE TERM INALS.
0.400.35 0.45
NOTE
10. JEDEC SPEC IFICATIONNO . REF : N/A
SIDE VIEW
BOTTOM VIEW
TOP VIEW
D
A
E
B
0.10 C
2X
0.10 C
2X
0.10 C
A
A1 0.05 C
C
SEATING PLANE
D2
E2
0.10 C A B
0.10 C A B
1
48
eb0.10 C A B
0.05 C
R
( N D -1 )× e
INDEX MARK
8
4
5
9
L
9
12
13
24
3625
37
PACKAGEOUTLINE, 48 LEAD QFN
7.0X7.0X0.9 MMVNA048 5.5X5.5 MMEPAD (SAWN) REV**
Document Number: 002-04922 Rev .*B Page 123 of 128
MB9B560L Series
15. Major Changes
Spansion Publication Number: DS709-00005
Page
Section
Change Resul t s
-
-
Preliminary
→
Data Sheet
3
■FEATURES
[USB function]
Added the following description :
• The size of each endpoint is according to the follows.
- Endpoint 0, 2 to 5 : 64bytes
- Endpoint 1 : 256bytes
31 to 34 ■I/O CIRCUIT TYPE
Added the following description to Remarks of Type F, G, I, L, M, N:
When this pin is used as an I2C pin, the digital output P-ch transistor is
always off
35 to 36
Added the following description to Remarks of Type O, P, Q:
For I/O setting, refer to VBAT Domain in the PERIPHERAL MANUAL
43
■HANDLING DEVICES
Handling when using debug pins
Added new section
44
■BLOCK DIAGRAM
Revised the block diagram
57
■ELECTRICAL CHARACTERISTICS
2. Recommended Operating Conditions
Added the note to “AVRH”
Revised “Table for package thermal resistance and maximum
permissible power”
58
Revised “Icc(leakmax)”
60 to 65
■ELECTRICAL CHARACTERISTICS
3. DC Characteristics
(1) Current Rating
• Revised the value of TBD
• Added the note to “ICC”
• Added the note to “ICCVBAT”
70
■ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(2) Sub Clock Input Characteristics
Revised the waveform chart :
VCC → VBAT
70
■ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(3) Built-in CR OscillationCharacteristics
• Revised the value of TBD
• Revised the table and the note of “Built-in High-speed CR”
71
■ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(4-1) Operating Conditions of Main PLL(In the
case of using main clock for input clock of PLL)
(4-2)Operating Conditions of USB PLL(In the case
of using main clock for input clock of PLL)
• Revised the table and the note
71
■ELECTRICAL CHARACTERISTICS
4. AC Characteristics
(4-3) Operating Conditions of Main PLL(In the
case of using built-in high-speed CR clock for
input clock of main PLL)
• Revised the value of TBD
• Revised the table and the note
106
■ELECTRICAL CHARACTERISTICS
5. 12-bit A/D Converter
・
Electrical Characteristics for the A/D Converter
• Revised the value of TBD
• Revised the condition of the electrical characteristics table
• Revised the description of "Reference voltage"
109
■ELECTRICAL CHARACTERISTICS
6. 12-bit D/A Converter
・Electrical Characteristics for the D/A Converter
• Revised the value of TBD
• Revised the condition of the electrical characteristics table
• Revised the remarks of “IDDA”
Document Number: 002-04922 Rev .*B Page 124 of 128
MB9B560L Series
Page
Section
Change Resul t s
116
■ELECTRICAL CHARACTERISTICS
11. Standby Recovery T ime
(1) Recovery cause: Interrupt/WKUP
• Revised the value of TBD
• Revised the table of Recovery count time
118
■ELECTRICAL CHARACTERISTICS
11. Standby Recovery T ime
(2) Recovery cause:Reset
• Revised the value of TBD
• Revised the table of Recovery count time
NOTE: Please s ee “Document H istory” about later revised information.
Document Number: 002-04922 Rev .*B Page 125 of 128
MB9B560L Series
Document Histor y
Document Title: MB9B5 60L Series 32-Bit Arm® Cortex®-M4F, FM 4 M icrocontro ller
Document Number: 002-04922
Revision ECN Orig. of
Change
Submission
Date Description of Change
** - AKIH 12/25/2013 Migrated to Cypress and assigned document number 002-04922.
No change to document contents or format.
*A 5273878 AKIH 05/12/2016 Updated to Cypress format.
*B 5555936 YSKA 12/15/2017
Added an explanation of product category in introduction (Page 1).
Changed an explanation from “from 01 to 99” to “from 00 to 99” in Real-Time Clock
(RTC) (Page 3) of Features, and Deleted “Second/A day of the week” of interrupt
function.
Corrected “USB Function" to “USB Device" in the following chapters.
Features (Page 1)
1. Product Lineup (Page 7)
4.2 List of Pin Functions (Page 19)
Divided an explanation into 64 pin and 48 pin in Power Supply (Page 4) of Features.
Changed package code as the following in chapter :
2. Packages (Page 8)
3. Pin Assignment (Page 9 - 12)
12.2 Recommended Operating Conditions (Page 53)
13. Ordering Information (Page 11 7)
14. Package Dimensions (Page 118-122).
FTP-48P-M49 -> LQA048, LCC-48P-M73 -> VNA048,
FTP-64P-M38 -> LQD064, FTP-64P-M39 -> LQG064,
LCC-64P-M24 -> VNC064
Changed 15 pin (Page 15) at LQFP48 from VBAT to VCC in 4.1 List of Pin Numbers.
Added 15 pin (Page 27) to VCC of Power at LQFP48, Deleted 15 pin from VBAT of
VBAT Power at LQFP48 in 4.2 List of Pin Functions.
Added Note for JTAG pin (Page 27) in 4. Pin Description.
Added an explanation in Notes on Power-on (Page 39) of 7. Handling Devices.
Corrected "total maximum output current" to "total average output current" at ∑
IOLAV in 12.1 Absolute Maximum Ratings (Page52).
Added Smoothing capacitor to Parameter, and Added remarks *6 in 12.2
Recommended Operating Conditions (Page 53).
Changed remark *3 to "When all ports are input and are fixed at "0"." in 12.3.1
Current Rating (Page 57 - 62).
In 12.3.1 Current Rating, Added remark *6 to ICCHD, Added remark *7 to ICCRD,
Added remark *8/*9 to ICCVBAT/RTC operation, and Added remark *9 to
ICCVBAT/RTC stop (Page 62).
Added an explanation for 48 pin package in 12.4.2 Sub Clock Input Characteristics
(Page 67).
Document Number: 002-04922 Rev .*B Page 126 of 128
MB9B560L Series
Revision ECN Orig. of
Change
Submission
Date Description of Change
Changed Parameter “Power supply rising time (tVCCR)” to “Power ramp rate (dV/dt)” i
n
12.4.8 Power-on Reset T iming, Changed the minimum to 1.3mV/μs, Changed the
maximum to 1000mV/μs, and Added remarks and note (Page 69).
Deleted setting value “SPI=1” and “MS=0” at using chip select in 12.4.11 UART
Timing, and Added “MS bit = 0” and “MS bit = 1” on the Figure (Page 88-95).
Corrected "Analog port input current" to "Analog port input leak current" in 12.5 12-
bit
A/D Converter (Page 103).
Reflected the following items in "Datasheet Errata for the MB9B560L Series
(002-04923)".
Added “Pull-up resistor : Approximately 50 kΩ” to remarks in Type I (Page 31) of
5.I/O Circuit Ty pe.
Modified S/T of VBAT Pin Status Type and remark *2 in List of VBAT Domain Pin
Status (Page 51) of 11.Pin Status in Each CPU State.
Added remarks *5 in 12.2 Recommended Operating Conditions (Page 53).
Added Frequency stabilization time to Parameter, and Added remarks *2 in Built-in
High-speed CR of 12.4.3 Built-in CR Oscillation Characteristics (Page 67).
Added Conversion time to Parameter in Electrical Characteristics for the D/A
Converter of 12.6 12-bit D/A Converter (Page 106).
Revised Recovery Count Time of 12.11.1 Recovery cause: Interrupt/WKUP (Page
113) as follows.
- Typical Value of Sub timer mode is 896μs.
- Typical Value of RTC mode stop mode (High-speed CR / Main/PLL run mode
return) is 316μs.
- Typical Value of RTC mode stop mode (Low-speed CR / sub run mode return) is
270μs, and Max Value is 540μs.
- Typical Value of Deep standby RTC mode without RAM retention is 365μs.
- Typical Value of Deep standby RTC mode with RAM retention is 365μs.
Revised Recovery Count Time of 12.11.2 Recovery cause: Reset (Page 115) as
follows.
- Typical Value of Sleep mode is 155μs.
- Typical Value of High-speed CR timer mode is 155μs.
- Typical Value of Low-speed CR timer mode is 315μs.
- Typical Value of Sub timer mode is 315μs.
- Typical Value of RTC mode stop mode is 315μs, Max Value is 567μs.
- Typical Value of Deep standby RTC mode without RAM retention is 336μs.
- Typical Value of Deep standby RTC mode with RAM retention is 336μs.
Modified the Chapter name “12.4.11 UART Timing” to “12.4.11
CSIO/UART Timing”.
(Page 72)
Added the Baud rate spec in “12.4.11 CSIO/UART Timing”.(Page 72, 74, 76, 78)
Modified the expression for “Reference power supply current” from “between AVRH
and AVSS” to “AVRH” in chapter 12.5. 12-bit A/D Converter (Page 103)
Moved the value(1.0) in “State transition time to operation permission”
from minimum
to maximum.(Page 103)
Document Number: 002-04922 Rev .*B Page 127 of 128
MB9B560L Series
Revision ECN Orig. of
Change
Submission
Date Description of Change
Modified the expression of Built-in CR in “1. Product Lineup”(Page 7)
Modified the mode name of I2C as follows(Page 2, 100)
High-speed mode Fast-mode, Typical Mode Standard-mode
Modified the typo as below.(Page 72, 74, 76, 78)
SCLKx_0 SCKx_0
Modified typo in the “Recovery Count Time” table in 12.11.1 Recovery cause:
Interrupt/WKUP (Page 113) and 12.11.2 Recovery Cause: Reset (Page 115) as
follows.
Old)
Deep standby RTC mode with RAM retention
Deep standby stop mode with RAM retention
New)
Deep standby RTC mode
Deep standby stop mode
Document Number: 002-04922 Rev .*B December 15, 2017 Page 128 of 128
MB9B560L Series
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