INFORMATION STORAGE EE bbE D M@@ 9003350 0000005 446 MBISDI eearD information Storage Devices, Inc. ISD1012A/1016A/1020A PRELIMINARY Single-Chip Voice Record/Playback Devices FEATURES Natural, high-quality playback suitable for voice, music, and tones Single-chip voice record and playback device ~ Direct analog storage technology Microphone preamplifier Automatic gain control Antialiasing and smoothing filters Speaker amplifier Eliminates digital memory, data converters, modulators, and battery back-up circuits e Easy-to-use; programming and development e Flexible record and playback control options e Nonvolatile EEPROM technologyzero power storage and 10K record cycles 10-year voice retention e Power down mode for lowest power consumption e Single 5-volt power supply Multiple message address options Directly cascadable for longer storage duration e Manual switch or microprocessor controllable Significantly reduced EMI generation and high system not required immunity to external EMI ISD1000A FAMILY SUMMARY Record/ U P. The ISD1000A Family includes three device types. Part Pyayback Input Sample Bed Limit ISD1000A Family replaces ISD1000 Family with improved Number (seconds) Rate (KHz) (KHz) noise characteristics. The ISD1000A Family is fully com- patible with the ISD1000 Family. The table summarizes ISD1012A 12 10-6 45 the characteristics of each device. ISD1016A 16 8 3.4 ISD1020A 20 6.4 2.7 ISD1012A, 1016A, 1020A BLOCK DIAGRAM Internal Clock 4 Timing DIRECT ANALOG s7 } Leer TECHNOLOGY Sampling Clock mo SP+ Analn o= > Antialiasing Filter Analog Transceivers = -{ Smoothing Filter -j Mux > - = Io SP- Ana Out o- 8 128K Cell ; Nonvolatile Mic Pre- 8 Analog Storage Array Amp a Mic Ref o AGC 0 AGC Power Conditioning Address Buffers Device Control o 9 9 8 666646466 Veco +5V eo Qo Q Q AO A1 A2 A3 A4 AS AB A7 Test(CLK) PD P/R CE EOM Aux in February 1992INFORMATION STORAGE 1$D1012A/1016A/1020A bbE D MH 9003390 0000006 312 MBISDI GENERAL DESCRIPTION The ISD1000A Family of devices is designed to record and playback audio and voice information in a single chip with a minimum of circuit complexity. This compact, easy-to- use, nonvolatile, low-power solution has been made possi- ble by ISDs patented DAST technologya breakthrough in Direct Analog Storage Technology in EEPROM. ISDs DAST technology results in storage density that is eight times greater than digital memory. The DAST nonvolatile analog array consists of 128K cellsthe equivalent of 1M bits of digital storage. The ISD1000A Family eliminates the need for digital con- version, digital compression, and voice synthesis tech- niques that often compromise voice quality and complicate usage. The ISD1000A Family of devices includes signal conditioning circuits and control functions which enable a complete, high quality recording and playback system ina single device. The ISD1000A is available in three versions which store voice in 12, 16, or 20 second DAST arrays. Addi- tional devices may be cascaded to achieve longer recording durations. The nonvolatile storage array is based on pro- duction-proven, low-power CMOS EEPROM technology. The highly integrated ISD1000A Family contains all of the basic functions required for high quality voice recording and playback. The noise cancelling Microphone Preampli- fier and Automatic Gain Control (AGC) records both low volume and high volume sounds. The AGC attack and re- lease times are adjusted by an external resistor and capaci- tor. Antialiasing is performed by a continuous fifth-order Chebyshev filter requiring no external components nor clocks to give toll quality reproduction. The low corner of the passband is user-settable by two external capacitors. The devices contain their own temperature-stabilized time-based oscillator. The ISD1000A devices drive a speaker directly through differential outputs which boosts output by four times and eliminates the need for an output amplifier. A series capacitor requirement is also eliminated. The device will operate from single 5-volt power supplies or from batteries. The device also includes a power down function for applications where minimum power consumption is criti- cal. The CMOS-based design, combined with the non- volatile storage array, assures lowest possible overall power consumption. On-chip control functions make the ISD1000A Family very easy to use in virtually any application. Each device offers a variety of operating modes and interface options. The devices may be used in applications that require little more than a few switches and a battery. The devices may also be integrated into electronic systems where digital addresses can be provided for more sophisticated message addressing and control. The ISD1000A DAST arrays are organized in 160 segments. Addresses AO through A7 provide access to each segment in the array for message addressing. Addressing provides the capability of constructing mes- sages by concatenating stored phrases and sounds. PIN NAMES Pin Pin # Name Pin Pin # Name A0-A5 1-6 Address Ana Out 21 Analog Output A6-A7 9, 10 Address Ana In 20 Analog Input Vocp 28 VCC Digital Power Supply AGC 19 Automatic Gain Control Veca 16 VCC Analog Power Supply Mic 17 Microphone Input Vasp 12 VSS Digital Ground Mic Ref 18 Microphone Reference Vasa 13 VSS Analog Ground PD 24 Power Down SP+ 14 Speaker Output + P/R 27 Playback/Record SP- 15 Speaker Output - EOM 25 End-of-Message Test (CLK) 26 TestMust be tied Low CE 23 Chip Enable Aux In 11 Auxiliary InputINFORMATION STORAGE bE D M 9003390 0000007 259 MEISDI er INFORMATION ISD DEVICES, INC. Errata Sheet 1SD1012A/1016A/1020A Data Sheet February 1992 Revision CORPORATE HEADQUARTERS 2841 Junction Avenue, Suite 204 San Jose, CA 95134 408/428-1400 FAX 408/428-1422 Page Item Correction 3 DIP and SOIC Pinout Pin 28 is Vccp not Vssp. Pin 26 is Test (CLK). Mic pin is Pin 17. PLCC Pinout Package dot should be below Pin 1. 4 Power Down (PD) Insert Low in last sentence. Sentence should read When EOM goes Low for overflow . . . Chip Enable (CE) Last sentence should read If the ISD1000A is not selected and is in the playback mode, then when CE is taken High, the auxiliary input is directed to the speaker amplifier. Address Inputs (A0A7) Table should read ISD1020A not ISD10120A. 5 Table 1. Operational Modes All references to EOM and CE should havea bar over the reference. 6 Design Schematic Capacitor between pins 20 and 21 should be C3 not C1. 7 DC Parameters Typ should read Typo. sD esc DEVICES, INC. aAINFORMATION STORAGE 1SD1000A FAMILY PIN ASSIGNMENTS 40 1] @ 2B Vex AD 2 [} 27 PR A2 3 CI al 26 Test 9CLK) As 4 [] 25 EOM AS 5 Cc [J] 24 PD AB 6 CJ [] 23 CE ne 7 Soi pz te nc 8 C1 ispioz0q I 7 Anau A 9 [] 20 Anain A7 10 Cy Tj] 19 AGC AUXIN 11 c [] 18 Mic Ref Veo 12 [_] 13 Mic Vesa 13 [7] [] 16 Veca see 14 [] 15 sP- DIP and SOIC bbE D) W@ 9003390 9000008 195 MBISDI 1$D1012A/1016A/1020A A3 A2 A1 AO Veco P/R Test (CLK) 4 3 2 1 28 27 2% M1 Fi 7) 1 e ms [] 25 EOM ase CO [] 24 PD cE nc 70 ISD1012A L] 28 ISD1016A [J 22 NC nc 8 [] {SD1020A Ae 9 o r] 21 Ana Out A710 C r] 20 Ana In Auxin 11 CO L] 19 AGC UuUUU UU Uo 12,13 14 #15 16 #417 18 Vsso Vssn SP+ SP- Vcca Mic Mic Ref PLCC ISD1000A FAMILY PIN DESCRIPTIONS Microphone Input (Mic) The microphone is AC-coupled to this pin via a series ca- pacitor. The user-selectable value of the input series ca- pacitor (together with the 10K ohm resistance internal to the ISD1000A) determines the low frequency cut-off for the ISD1000A passband. Microphone Reference (Mic Ref) When AC is coupled to microphone ground, the recorded noise level is significantly reduced. Ground noise is refer- enced to the preamplifier. If this pin is not used, it must NOT be connected to any signal or voltage. It must float. Analog Output (Ana Out) The microphone signal is amplified and is output to the Ana Out pin. The voltage gain of the pre-amp is determined by the voltage level at the Automatic Gain Control (AGC) pin. It has a maximum gain of about 24dB for small input signal levels. Analog In (Ana In) The external capacitor connects Ana In to the Ana Out pin. The value of the external capacitor, together with the 2.7KQinput impedance at Ana In, can be chosen to give ad- ditional cut-off at the low frequency end of the voice passband. The Ana In pin may also be used to input alter- native sources of analog signal, other than the microphone signal. Automatic Gain Control (AGC) The purpose of the AGC is to dynamically adjust the pre- amplifier gain, and therefore extend the range of input sig- nals which can be applied to the microphone input without distortion. The AGC considerably extends the range of recordable sounds from whispers to loud voices. Peak volt- age levels at the Amplifier output are detected in the AGC circuit, and charge the external capacitor C2 on the AGC Control pin. The source resistance (5K) of the internal AGC circuit and the external capacitor C2 determine the at- tack time of the gain control. Release time is determined by the RC time constant of the external resistor (R2) and capacitor (C2). For AGC voltages of 1.5V and below, the preamplifier is at its maximum gain 24dB. Reduction in preamplifier gain occurs for voltages of approximately 1.8V. Speaker Outputs (SP+/SP-) The SP+ and SP- pins provide direct drive for loudspeakers with impedances as low as 16 ohms. A single output may be used, but, for direct drive loudspeakers, the two opposite polarity outputs give an improvement in output power of up to four times over a single-ended connection. Further- more, when SP+ and SP- connections are used, a speaker coupling capacitor is not required. A single-ended connec- tion will require an AC coupling capacitor between the SP pin and the speaker. The speaker outputs are held at V,., during recording and Power Down.INFORMATION STORAGE ISD1012A/1016A/1020A PIN DESCRIPTION, continued Power Down (PD) The Power Down pin is taken high (when not recording or playing back) to provide a very low power mode to the ISD1000A. When EOM goes for overflow condition, PD must be brought High to reset addresses. Chip Enable(CE) The Chip Enable pin is taken low toenable all playback and record operations. The address inputs (A0-A7) and the playback/record input are latched into the ISD1000A by this falling edge. When CE is taken high, the ISD1000A is unselected, and the auxiliary input is directed into the speaker power amplifier. Playback/Record (P/R) The state of the P/Ris latched into the ISD1000A on the falling edge of CE. A High level selects a playback cycle, while a Low level selects a record cycle. During record, the playback circuits and speaker output amplifiers are pow- ered down, and the SP+ and SP- outputs are held at Vgg,- During playback, the internal record and analog inputs are disabled. In playback mode, it is only necessary to supply the starting message address. The ISD1000A will playback until an End-of-Message is encountered (see Table 1, Page 5 for other options). In record mode, the start address determines the beginning of the message. The ISD1000A Family records until CE is brought High or until an over- flow is detected. Address Inputs (A0-A7) The Address Inputs provide two functions in the ISD1000A Family: (1) Message address (A6 OR A7 = Low) (2) ISD1000A Family Operational Mode Options (A6 AND A7 = High) Operational mode options are shown in Table 1 (Page 5). There are a maximum of 160 message addresses (or seg- ments). Each segment corresponds to one of 160 rows in the analog storage array. The message addresses (segments) are in locations 0 through 159 contiguous. The playback/re- cord duration of each segment depends on the device and is as follows: Family Segment Playback/Record Member Duration (seconds) ISD1012A 0.075 ISD1016A 0.100 ISD10120A | 0.125 An operation may be started at any address, as defined by address pins A0-A7. Record or playback continues with automatic incrementing of internal on-chip address until bbhE D M@ 9003390 00000045 021 MEISDI either CE is brought high (record), an end of message bit is encountered (playback with GE high) or an overflow (device full) condition results. Test (CLK) Test (CLK) is normally only used by manufacturing for test. In applications circuits it is tied to ground, however, if greater timing precision is desired, (internal clock hast 2% tolerance over temperature and voltage range) the chip can be externally clocked through this pin. For the ISD1016A this clock is a 1024 KHz signal; the ISD1012A is 1365 KHz; and the ISD1020A is 819 KHz. The duty cycle is not critical, as this clock is immediately divided by two. End of Message (EOM) A digital End-of-Message marker is automatically inserted in an internal nonvolatile register at the end of each re- corded message. The EOM output goes Low under the fol- lowing conditions: e At end of each message Message overflow (device full) The ISD1000A Family has an internal V,, detect circuit. When V,,p drops below 3.5V, EOMis forced Low and the de- vice is placed in playback mode. The SOM marker provides a convenient handshake signal for a processor. The EOM function also facilitates cascading. Auxiliary Input (Aux-in) The input to the internal output power amplifier is multi- plexed between the storage array and the auxiliary input pin. The auxiliary input is active when CE=High and play- back has ended or EOM=Low due to overflow. The active power amplifier input (storage array or auxiliary input) in- hibits the other input. (For noise considerations, it is sug- gested that the auxiliary input not be driven when the stor- age array is active.) The Auxiliary Input also facilitates cascading. Veca and Veco (+5.0 Volts) Analog and digital circuits internal to the ISD1000A Fam- ily use separate power buses to minimize noise on the chip. These +5 Volt buses are brought out to separate pins on the package and should be tied together as close to the supply as possible. It is important that the +5 Volt supply be decoupled as close as possible to the package. Vesa and Voesp (Ground) Similar to V.,, and Vocp the analog and digital circuits in- ternal to the ISD1000A Family use separate ground buses to minimize noise. These pins should be tied together as close as possible to the device.INFORMATION STORAGE BLE D M@@ 9003390 0000010 443 MISDI 1S01012A/1016A/1020A OPERATIONAL MODES The ISD1000A Family can be used in systems with various levels of control sophistication, from microprocessor-con- trolled environments to simple push-buttons or switches. Different operational modes are enabled by taking address pins A7 AND A6 HIGH. In this mode, the states of address Table 1. Operational Modes pins A5 through AO determine the control function and NOT the message address. The options are shown in the Table below. Each option is selected by bringing the appro- priate address High. Multiple options may be selected by applying a High level to each of the desired address pins. Address Control Function (High) Pin # Typical Use Message cueing (speaker output disabled). AQ 1 Selecting messages when ad- (See Note 1) dress is unknown. Indirect mes- sage addressing. EOM markers are deleted by the next mes- Al 2 Position a single EOM marker at sage use with (A4 = 1). (Available Q3/1992) the end of the last message. During playback, EOM pulses low at array A2 3 Playing back messages whose overflow only (used for cascading function). duration exceeds a single chip limitation. Continuous playback (at EOM loops back to A3 4 Continous repeat. beginning and repeats message). Consecutive addressing - Message start A4 5 Recording consecutive multiple pointer is reset only when operational mode messages. is changed (playback/record). (See Note 2) Playback is chip enable level activated. AS 6 Terminate playback with CE. Notes: 1. Message Cueing (Available Q3, 1992) Message cueing allows the user to skip through messages. Each time CE memory is pulsed Low with the address in- puts set to this mode, the internal message pointer skips forward until it encounters an end-of-message marker and then stops. By providing a certain number of pulses to the CE pin in message cueing mode and then changing to con- secutive addressing mode, the user can select and then re- cord or playback a desired message. Message cueing should not be used in Record mode. 2. Consecutive Addressing Consecutive addressing allows for recording and playback of consecutive messages without the need for direct ad- dressing or any other kind of message management. Dur- ing recording, each time that CE is taken Low, a message is recorded at the next position in memory. When CE is taken High again, an End-of-Message marker is written to indi- cate the position of the End of the message. In this fashion, a string of messages is recorded, each one placed immedi- ately after the previous one.INFORMATION STORAGE 1$D1012A/1016A/1020A bbE D M@ 9003390 0000011 74T BSISDI APPLICATION EXAMPLE DESIGN SCHEMATIC Voc Vee ISD1012A/1016A/1020A 4. . AO vccD 22yF = Ai VCCA o = Chip Enable na vssD 2 24 Ad VSSA 4 9 AS 14 TO 2 As sp, Lit $o oY a7 sp- 2 ____--- AUXIN, ELL Power Down 23 | oe ANA IN 120 I Tc, I | 8 or 16 Q Speaker 1_ BP ANAOUT Fo 10. 5e|P/R 18 +pF 10Q EOM MIC REF} To Playback/Record MIC + A Test(cik) acc | Vv C. oc R: I ? C, C. 470 K Q 4.7pF _ =~ R, Toor T 22nr 2K Mic Ref Electret Microphone Note: If desired, this pin may be left unconnected (microphone preamplifier noise will be higher). In this case, pin 18 must not be tied to any other signal or voltage. APPLICATION EXAMPLE APPLICATION EXAMPLE-- BASIC DEVICE CONTROL PASSIVE COMPONENT FUNCTIONS Control Function Action Part | Function Comments e P R1 | Microphone power Reduces power 1 Power-up chip and 1.PD = Low supply decoupling supply noise select record/play- 2.P/R = As desired network back mode R2 | Release time constant} Sets release time 2 Set message ad- Set addresses for AGC dress for record/ A0Q-A7 playback R3 | Microphone biasing Provides biasing 7 = resistor for microphone 3 Begin record/ CE = Low operation playback _ Cl | Microphone Decouples microphone 4 End cycle CE = High DC-blocking capaci- | bias from chip. tor. Low frequency Provides single-pole low cutoff frequency cutoff C2 Attack/ Release Sets attack /release time constant time for AGC C3 | Low frequency Provides additional cutoff capacitor pole for low frequency cutoff C4 | Microphone power Reduces power supply decoupling supply noise network C5 | Noise reduction Reduces input noiseINFORMATION STORAGE BEE D M@ 90033590 oo0001e bib MISDI 1$D1012A/1016A/1020A ABSOLUTE MAXIMUM RATINGS (1ISD1012A/1016A/1020A) Condition Value Operating Temperature 0C to +70C Temperature under bias* 65 C to +125 C Storage temperature range* 65 C to +150 C Voltage applied to any pin* (Vs3 -0.3 V) to (Vee + 0.3 V) Voltage applied to any pin (input current limited to + 20 mA)* Lead temperature (soldering 10 seconds)* Veo Vss (Ves 1.0 V) to (Vec + 1.0 Vv) 300 C 0.3 V to+7.0V * Stresses above those listed may cause permanent damage to the device. Exposure to the absolute maximum ratings denoted by (*) may affect device reliability. Stress ratings denoted by (*) do not imply functional operation at these conditions. DC PARAMETERS (1SD1012A/1016A/1020A) Operating Conditions Ty =0Cto 70C (Note #4); Voc (Note #5) = 5.0V 410%; Ves (Note #6) = 0 V; Unless otherwise noted Symbol Parameters Min Typo, Max Units Conditions Vir Input Low Voltage 0.8 Vv Vin Input High Voltage 2.0 Vv Vor Output Low Voltage 0.4 Vv lo. = 4.0 mA Vou Output High Voltage 2.4 Vv lon = -1.6 mA Vout Output High Voltage Veco -0.4 Vv lon = 10 pA loc Voc Current (Operating) 25 mA Rexr = 00 Ig Vec Current (Standby) 1 10 HA In Input Leakage Current +1 pA Rexr Output Load Impedance 16 Q Speaker Load Ruic Pre-Amp In Input Resistance 10 KQ Pins 17 and 18 Ravx Aux Input Resistance 10 KQ Rana In Ana In Input Resistance 2.7 KQ Aprn Pre-Amp Gain 1 24 dB AGC = 0.0 V Apr Pre-Amp Gain 2 5 dB AGC =2.5V Aaux Aux In/SP + Gain 0.9 1.0 V/V Aas Ana In to SP+/- 22 dB Racc AGC Output Resistance 5 KQ Toren Pre-Amp Out Source 100 pA @Vour = 1.0 V Trret Pre-amp In Sink 100 pA @Vour = 2.0VINFORMATION STORAGE BbE D M@ 9003390 0000013 S52 MMISDI 1$D1012A/1016A/1020A ISD1012A12-SECOND DURATION DEVICE AC PARAMETERS Operating Conditions Ta =0 Cto 70C (Note #4); Voc (Note #5) = 5.0 V+ 10%; Vos (Note #6) = 0 V; Unless otherwise noted Symbol Characteristics Min Type Max Units Conditions FS Internal Clock 10.6 KHz Sampling Frequency BW Passband (3) 4500 Hz THD Total Harmonic Distortion 2 % @ 1KHz Pour Speaker Output Power 50 mW Rexr = 16Q Vour Voltage across speaker pins 2.5 Vp-p Rexr = 6002 Vin Mic input voltage 20 mv Peak - Peak (2) Vine Ana In input voltage 50 mv Peak - Peak Ving Aux In input voltage 1.25 v Peak Peak; Rexr = 16Q Tser Control / Address set-up 300 nsec Trow Control / Address hold 0 nsec Toe CE Record time 100 nsec Tpup Power up delay 18.75 msec Trou Power down hold 0 nsec Trec Record time 12 sec Tray Playback time 12 sec Tzom EOM pulse width 9.4 msec Notes: 1. Typical values @ T, = 25 C and nominal voltages 4. Case temperature 2. With 12 KQ series resistor at Ana In 5. Voc = Vocn = Voca 3. Low frequency cutoff depends on value of external 6. Ves = Vasa = Vesp capacitors (see Pin Descriptions). 7. Voc, and Vogy connected togetherINFORMATION STORAGE bbE D M@ 9003390 0000014 459 MEISDI 1$D1012A/1016A/1020A TIMING DIAGRAMS (ISD1012A) RECORD P/R Tron PD Don't Care Don't Care Don't Care Ao Ar Mic Ana In SP+/- ~ PLAYBACK ce Tse: _\ PIR \ Don't Care NY jetjane -> PD Don't Care \ Tow Tron Don't Care AoAz2 Don't Care x xX Don't Care Vesa * Tse) Ag SP4/- he Tey > Tpray epe TemINFORMATION STORAGE bLE D M@@ 1003350 OO00015 3e5 MBISDI 1SD1012A/1016A/1020A ISD1016A16-SECOND DURATION DEVICE AC PARAMETERS Operating Conditions Ta = 0 Cto 70C (Note #4); Voc (Note #5) = 5.0 V+ 10%; Vos (Note #6) = 0 V; Unless otherwise noted @ Symbol Characteristics Min Typo Max Units Conditions FS Internal Clock 8 KHz Sampling Frequency BW Passband (3) 3400 Hz THD Total Harmonic Distortion 2 % @ 1KHz Pour Speaker Output Power 50 mW Rexr == 16Q Vour Voltage across speaker pins 2.5 Vp-p Rexr = 600Q Vien Mic input voltage 20 mv Peak Peak (2) Vine Ana In input voltage 50 mv Peak Peak Vas Aux In input voltage 1.25 Vv Peak Peak; Rexr = 16Q Tser Control/ Address set-up 300 nsec Tow Control/ Address hold 0 nsec Tos CE Record time 100 nsec Tpup Power up delay 25 msec Tron Power down hold 0 nsec Trac Record time 16 sec Trray Playback time 16 sec Tom EOM pulse width 12.5 msec Notes: 1. Typical values @ T, = 25 C and nominal voltages 4. Case temperature 2. With 12 KQ series resistor at Ana In 5. Voc = Veon = Voca 3. Low frequency cutoff depends on value of external 6. Veg = Vasa = Vesp capacitors (see Pin Descriptions). 7. Voca and Vocp connected together 10INFORMATION STORAGE bbE D 9003390 OOO00Lb 2bl BMISDI 1SD1012A/1016A/1020A TIMING DIAGRAMS (ISD1016A) RECORD P/R Don't Care Tron PD Don't Care AoAz Mic Ana In SP4/- - eres a Tce CE N Y Teer >We PIR \ Dont Care ~~ TN PD Don't Care \ Two. Tron Don't Care Ac-Az Don't Care OK Don't Care Vesa sey SP4/- hd EOmM Teruo _ TeLay Teom 11INFORMATION STORAGE bEE D M@ 9003390 0000017 178 MBISDI 1SD1012A/1016A/1020A 1SD1020A20-SECOND DURATION DEVICE AC PARAMETERS Operating Conditions Ts =0 Cto 70C (Note #4); Voc (Note #5) = 5.0 V + 10%; Vss (Note #6) = 0 V; Unless otherwise noted Symbol Characteristics Min Typo Max Units Conditions FS Internal Clock 6.4 KHz Sampling Frequency BW Passband (3) 2700 Hz THD Total Harmonic Distortion 2 % @ 1KHz Pour Speaker Output Power 50 mW Rexr == 162 Vour Voltage across speaker pins 25 Vp-p Rexr == 600Q Vin Mic input voltage 20 mv Peak Peak (2) Vin Ana In input voltage 50 mv Peak Peak Ving Aux In input voltage 1.25 Vv Peak Peak; Rexr = 16Q Tser Control/ Address set-up 300 nsec Turow Control / Address hold 0 nsec Tee CE Record time 100 nsec Trup Power up delay 31.25 msec Trou Power down hold 0 nsec Trac Record time 20 sec Trray Playback time 20 sec Tuom EOM pulse width 15.6 msec Notes: 1. Typical values @ T, = 25 C and nominal voltages 4. Case temperature 2. With 12 KQ series resistor at Ana In 5. Veo = Veo = Veca 3. Low frequency cutoff depends on value of external 6. Vas = Vasa = Veep capacitors (see Pin Descriptions). 7. Voc, and Vocp connected together 12INFORMATION STORAGE TIMING DIAGRAMS (ISD1020A) bbE D MM 9003350 0000018 O34 MBISDI 1SD1012A/1016A/1020A RECORD CE P/AR Don't Care . Tron PD Don't Care Ao Az Dont Care Don't Care Mic Ana In " SP4+/- - PLAYBACK \ Toe * V . CE Tser eS , P/R \ Don't Care rr \ -F PD Don't Care \ Tnovo Tron Don't Care Ao Az Don't Care V Don't Care Vssa Tset SP4/- h, EOM a Typ e$ Tray Teo 13INFORMATION STORAGE 1SD1012A/1016A/1020A bEE D MM 9003390 0000019 T70 MHISDI PACKAGE DIAGRAMS 28-lead Plastic Dual In-line Package (DIP) Type P DO er er) o O O va Yh "LP THA - Ci 4 28-lead Plastic Small Outline Package (SOIC) Type G BAR RRERRARR REE o o Ooo wo oer Uniess otherwise specified: all tolerances are + .007 inches INCHES MILLIMETERS MIN NOM | MAX. MIN NOM | MAX. A |i4as | 1.450 | 1.455 36.7 _ | 36.83 | 36.95 B 150 3.89 C1 | 600 625 15.24 15.88 C2 | 530 | 540 | 550 13.46 | 13.72 | 13.97 D 1.25 1.30 | 1.35 2.92 | 3.05 3.18 E A25 AZO | 135 3.18 3.43 F 015 018 | 022 0.38 | 0.46 0.56 6 055 .060__| .065 1.40 1.52 1.65 H -100 254 6 0 7 15 o 7 15 INCHES MILLIMETERS MIN NOM | MAX. MIN NOM | MAX. A .706 714 | 718 17.93 | 18.14 | 18.24 B 086 -088 090) 2.18 2.24 2.29 c 340 346 | 350 8.64 | 8.79 | 889 D 004 .007 010 102 | .178 .254 E 014 016 | .020 360 410 480 F .050 1.27 6 463 470 =| 477 W476 | 1200] 12.12 H .020 O3t .042 S10 | .790 1.07 INCHES MILLIMETERS MIN NOM | MAX. MIN NOM | MAX. A 465 .490 | .495 12.32 | 12.45 | 1257 B .450 452 454 11.43 | 11.48 | 11.53 c .485 .490 | .495 12.32 | 1245 | 1257 D .450 452 | .454 11.43 | 11.48 { 1153 E .026 032 F .100 101 110 254 | 256 2.79 6 148 152 | 1156 3.76 | 3.86 3.96 H 65 $72 | 180 419 | 437 | 457 K .050 14INFORMATION STORAGE bbE D M@ 9003390 O0000e0 752 BMISDI 1SD1012A/1016A/1020A IMPORTANT NOTICE THE WARRANTY FOR EACH PRODUCT OF INFORMA- TION STORAGE DEVICES, INC. IS CONTAINED IN A WRITTEN WARRANTY WHICH GOVERNS SALE AND USE OF SUCH PRODUCT. SUCH WARRANTY IS CONTAINED IN THE PRINTED TERMS AND CONDI- TIONS UNDER WHICH SUCH PRODUCT IS SOLD, OR IN A SEPARATE WRITTEN WARRANTY SUPPLIED WITH THE PRODUCT. PLEASE REFER TO SUCH WRITTEN WARRANTY WITH RESPECT TO ITS APPLICABILITY TO CERTAIN APPLICATIONS OF SUCH PRODUCT. Information Storage Devices (ISD) reserves the right to change the ISD1000A Family product specifications identi- fied in this publication and to discontinue the ISD1000A Family products without notice. ISD assumes no responsibility or liability for any use of the ISD1000A Family products, ISD conveys no license or title, either express or implied, under any patent, copyright or mask work right to the ISD1000A Family products, and ISD makes no warranties or representations that the ISD1000A Family products are free from patent, copyright or mask work right infringement, unless otherwise speci- fied. Applications described in this publication are for illustra- tive purposes only, and ISD makes no warranties or repre- sentations that the ISD1000A Family products will be suit- able for such applications. Information contained in this ISD1000A Family product specification supersedes all data for the ISD1000A Family products published by ISD before February, 1992. ORDERING INFORMATION When placing an order for the ISD1000A Family of devices, please refer to the following model numbers: Model Number Record/Playback Description Duration (Seconds) ISD1012AP 12 28-pin plastic dual in-line package ISD1012AJ 12 28-lead plastic leadless chip carrier (PLCC) ISD1012AG 12 28-lead small outline integrated circuit (SOIC) 1SD1012AX 12 Bare unpackaged die ISD1016AP 16 28-pin plastic dual in-line package ISD1016AJ 16 28-lead plastic leadless chip carrier (PLCC) ISD1016AG 16 28-lead small outline integrated circuit (SOIC) 1SD1016AX 16 Bare unpackaged die ISD1020AP 20 28-pin plastic dual in-line package ISD1020AJ 20 28-lead plastic leadless chip carrier (PLCC) ISD1020AG 20 28-lead small outline integrated circuit (SOIC) ISD1020AX 20 Bare unpackaged dieINFORMATION STORAGE BEE D MM 9003390 0000024 338 MMISDI ISD1100 SERIES PRELIMINARY DATA SHEET APPLICATION SCHEMATIC Voc Voc ISD1100 Veo = Veo Voc 28 TT. Cc | v [ee D4 Vv Co yo 16 Ry REC yon 42 0.1 UF 1 KQ 162 LED .001 WF SsD T SPEAKER Vgsa - = _.. 14 . O oO SP+ 15 PLAYL SP- ANAIN |" Cg oO Oo o , R2 R C1] 220 uF PLAYE 23) BLAYL ANA OUT 21 AAA AI 0.1 pF 3 -T 24 | BLAVE 51KQ 10 Ke: ELECTRET 7 | =o a 11 C4 MICROPHONE ono. REC MIC REF \\0.1 nF RECORD R7 mic 2 A\\A9254 RECLED = aa L = 1KQ : C6 R4 470 KQ Zz C5 v i HF Additional components may be required for some applications. For more details, please refer to the ISD Application Notes and Design Manual. FUNCTIONAL DESCRIPTION EXAMPLE The following example operating sequence demonstrates the functionality of the ISD1100 Series devices. 1. Record a message filling the memory. Pulling the REC signal LOW initiates a record cycle from the beginning of the message space. If REC is held LOW, the recording continues until the message space has been filled. Once the message space is filled, recording ceases. The device will automatically power down after REC is released HIGH. 2. Edge-activated playback. Pulling the PLAYE signal LOW initiates a playback cycle from the beginning of the message space. The rising edge of PLAYE has no effect on operation. If a recording has filled the message space, the entire message is played. When the device reaches the end of the message space, it automatically powers down. A subsequent falling edge on PLAYE initiates a new play cycle from the beginning of the memory. 3. Level-activated playback. Pulling the PLAYL signal LOW initiates a playback cycle from the beginning of the message space. If PLAYL remains LOW, the device plays through to the end of the message and subsequently enters the power-down mode. 4, Level-activated playback (truncated). If PLAYL is pulled HIGH any time during the playback cycle, the device stops playing and enters the power-down mode. 5. Record (interrupting playback). The REC signal takes precedence over other operations. Any LOW-going transition on REC initiates a new record operation from the beginning of the memory, regardless of any current operation in progress. 6. Record a message, partially filling the memory. A record operation need not fill the entire memory. Releasing the REC signal HIGH before filling the message space causes the recording to stop and an end-of- message marker to be placed. The device powers down automatically. 7. Play back a message, partially filling the memory. Pulling the PLAYE or PLAYI signal LOW initiates a playback cycle which is then completed when the end-of- message marker is encountered. Playback ceases and the device powers down. 8. RECLED operation. The RECLED output pin provides an active-LOW signal which can be used to drive an LED as a record in progress indicator. It returns to a HIGH state when the REC pin is released HIGH or when the recording is completed due to the memory being filled. 4 Single-Chip Solutions That Speak For Themselves October, 1993