HUF75344G3, HUF75344P3 Data Sheet N-Channel UltraFET Power MOSFET 55 V, 75 A, 8 m These N-Channel power MOSFETs are manufactured using the innovative UltraFET process. This advanced process technology achieves the lowest possible onresistance per silicon area, resulting in outstanding performance. This device is capable of withstanding high energy in the avalanche mode and the diode exhibits very low reverse recovery time and stored charge. It was designed for use in applications where power efficiency is important, such as switching regulators, switching converters, motor drivers, relay drivers, low-voltage bus switches, and power management in portable and batteryoperated products. October 2013 Features * 75A, 55V * Simulation Models - Temperature Compensated PSPICE(R) and SABERTM Models - Thermal Impedance PSPICE and SABER Models Available on the web at: www.fairchildsemi.com * Peak Current vs Pulse Width Curve * UIS Rating Curve * Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol Formerly developmental type TA75344. D Ordering Information PART NUMBER PACKAGE BRAND HUF75344G3 TO-247 75344G HUF75344P3 TO-220AB 75344P G S Packaging JEDEC STYLE TO-247 JEDEC TO-220AB SOURCE DRAIN GATE SOURCE DRAIN GATE DRAIN (FLANGE) DRAIN (TAB) All ON Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification. (c)2004 Semiconductor Components Industries, LLC. September-2017, Rev 3 Publication Order Number: HUF75344G3/DD HUF75344G3, HUF75344P3 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified UNITS V V V 55 55 20 Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (Figure 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . .TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . Tpkg 75 Figure 4 Figure 6 285 1.90 -55 to 175 A W W/oC oC 300 260 oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS 55 - - V OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current BVDSS IDSS IGSS ID = 250A, VGS = 0V (Figure 11) VDS = 50V, VGS = 0V - - 1 A VDS = 45V, VGS = 0V, TC = 150oC - - 250 A VGS = 20V - - 100 nA ON STATE SPECIFICATIONS Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250A (Figure 10) 2 - 4 V Drain to Source On Resistance rDS(ON) ID = 75A, VGS = 10V (Figure 9) - 6.5 8.0 m THERMAL SPECIFICATIONS Thermal Resistance Junction to Case RJC (Figure 3) - - 0.52 oC/W Thermal Resistance Junction to Ambient RJA TO-247 - - 30 oC/W TO-220 - - 62 oC/W VDD = 30V, ID 75A, RL = 0.4, VGS = 10V, RGS = 3.0 - - 187 ns - 13 - ns SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-Off Time tON td(ON) - 125 - ns td(OFF) - 46 - ns tf - 57 - ns tOFF - - 147 ns - 175 210 nC tr GATE CHARGE SPECIFICATIONS Total Gate Charge Qg(TOT) VGS = 0V to 20V Gate Charge at 10V Qg(10) VGS = 0V to 10V Threshold Gate Charge Qg(TH) VGS = 0V to 2V Gate to Source Gate Charge Qgs Reverse Transfer Capacitance Qgd VDD = 30V, ID 75A, RL = 0.4 Ig(REF) = 1.0mA - 90 108 nC - 5.9 7.0 nC (Figure 13) - 14 - nC - 39 - nC CAPACITANCE SPECIFICATIONS Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) www.onsemi.com 2 - 3200 - pF - 1170 - pF - 310 - pF HUF75344G3, HUF75344P3 Source to Drain Diode Specifications PARAMETER SYMBOL Source to Drain Diode Voltage MIN TYP MAX UNITS ISD = 75A - - 1.25 V trr ISD = 75A, dISD/dt = 100A/s - - 105 ns QRR ISD = 75A, dISD/dt = 100A/s - - 210 nC VSD Reverse Recovery Time Reverse Recovered Charge TEST CONDITIONS Typical Performance Curves 80 1.0 ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 0.8 0.6 0.4 60 40 20 0.2 0 0 0 25 50 75 100 125 150 25 175 50 TC , CASE TEMPERATURE (oC) 75 100 125 150 175 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 2 THERMAL IMPEDANCE ZJC, NORMALIZED 1 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE www.onsemi.com 3 100 101 HUF75344G3, HUF75344P3 Typical Performance Curves (Continued) IDM, PEAK CURRENT (A) 2000 TC = 25oC 1000 FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: 175 - TC I = I25 150 VGS = 20V VGS = 10V 100 TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 50 10-5 10-4 10-3 10-2 10-1 100 101 t, PULSE WIDTH (s) FIGURE 4. PEAK CURRENT CAPABILITY 1000 TJ = MAX RATED TC = 25oC 100 IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 1000 100s 1ms 10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10ms If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 100 STARTING TJ = 25oC STARTING TJ = 150oC VDSS(MAX) = 55V 10 0.01 1 1 10 100 200 VDS, DRAIN TO SOURCE VOLTAGE (V) 1 0.1 tAV, TIME IN AVALANCHE (ms) 10 NOTE: Refer to ON Semiconductor Application Notes AN9321 and FIGURE 5. FORWARD BIAS SAFE OPERATING AREA AN9322. FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 150 150 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V 120 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) VGS = 20V VGS = 10V VGS = 7V VGS = 6V 90 60 VGS = 5V 30 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX TC = 25oC 0 0 1 2 3 VDS, DRAIN TO SOURCE VOLTAGE (V) 120 90 60 25oC 30 175oC -55oC 0 4 FIGURE 7. SATURATION CHARACTERISTICS 0 1.5 3 4.5 6 VGS, GATE TO SOURCE VOLTAGE (V) FIGURE 8. TRANSFER CHARACTERISTICS www.onsemi.com 4 7.5 HUF75344G3, HUF75344P3 Typical Performance Curves (Continued) 1.2 VGS = VDS, ID = 250A PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 75A NORMALIZED GATE THRESHOLD VOLTAGE NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2.5 2.0 1.5 1.0 0.5 -80 0 -40 40 80 120 0.8 0.6 0.4 -80 200 160 1.0 TJ, JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 1.2 4500 ID = 250A C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE -40 1.1 1.0 CISS VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 3000 COSS 1500 CRSS 0.9 -80 -40 0 40 80 120 160 200 0 0 TJ , JUNCTION TEMPERATURE (oC) FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE 10 20 30 40 50 VDS , DRAIN TO SOURCE VOLTAGE (V) FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE VGS , GATE TO SOURCE VOLTAGE (V) 10 VDD = 30V 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 75A ID = 55A ID = 35A ID = 20A 2 0 0 25 50 75 Qg, GATE CHARGE (nC) 100 NOTE: Refer to ON Semiconductor Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT www.onsemi.com 5 60 HUF75344G3, HUF75344P3 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN REQUIRED PEAK IAS + RG VDS IAS VDD VDD - VGS DUT tP 0V IAS 0 0.01 tAV FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS VDS VDD RL Qg(TOT) VDS VGS VGS = 20V Qg(10) + VDD VGS = 10V VGS DUT VGS = 2V IG(REF) 0 Qg(TH) Qgs Qgd Ig(REF) 0 FIGURE 16. GATE CHARGE TEST CIRCUIT FIGURE 17. GATE CHARGE WAVEFORM VDS tON tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% + VGS - VDD 10% 10% 0 DUT 90% RGS VGS VGS 0 FIGURE 18. SWITCHING TIME TEST CIRCUIT 10% 50% 50% PULSE WIDTH FIGURE 19. RESISTIVE SWITCHING WAVEFORMS www.onsemi.com 6 HUF75344G3, HUF75344P3 PSPICE Electrical Model .SUBCKT HUF75337 2 1 3 ; rev 3 Feb 1999 CA 12 8 4.9e-9 CB 15 14 4.75e-9 CIN 6 8 2.85e-9 LDRAIN DPLCAP DRAIN 2 5 10 DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD DBREAK + RSLC2 5 51 ESLC 11 - EBREAK 11 7 17 18 59.7 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 RLDRAIN RSLC1 51 RDRAIN 6 8 ESG EVTHRES + 19 8 + LGATE GATE 1 LDRAIN 2 5 1e-9 LGATE 1 9 2.6e-9 LSOURCE 3 7 1.1e-9 KGATE LSOURCE LGATE 0.0085 + 50 - EVTEMP RGATE + 18 22 9 20 21 EBREAK 17 18 DBODY - 16 MWEAK 6 MMED MSTRO RLGATE LSOURCE CIN 8 SOURCE 3 7 RSOURCE RLSOURCE MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD S1A 12 RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 1.94e-3 RGATE 9 20 0.36 RLDRAIN 2 5 10 RLGATE 1 9 26 RLSOURCE 3 7 11 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 3.5e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B S2A 13 8 14 13 S1B 17 18 RVTEMP S2B 13 CA RBREAK 15 CB 6 8 EGS 19 - - IT 14 + + VBAT 5 8 EDS - + 8 22 RVTHRES 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*400),3))} .MODEL DBODYMOD D (IS = 2.95e-12 RS = 2.6e-3 TRS1 = 1.05e-3 TRS2 = 5.0e-7 CJO = 5.19e-9 TT = 5.9e-8 M = 0.55) .MODEL DBREAKMOD D (RS = 1.65e-1 IKF = 30 TRS1 = 1.15e-4 TRS2 = 2.27e-6) .MODEL DPLCAPMOD D (CJO = 5.40e-9 IS = 1e-30 N=1 M = 0.88 ) .MODEL MMEDMOD NMOS (VTO = 3.29 KP = 5.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 0.36) .MODEL MSTROMOD NMOS (VTO = 3.83 KP = 123 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.90 KP =0.04 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 3.6) .MODEL RBREAKMOD RES (TC1 = 1.15e-3 TC2 = 2.0e-7) .MODEL RDRAINMOD RES (TC1 = 1.37e-2 TC2 = 3.85e-5) .MODEL RSLCMOD RES (TC1 = 1.45e-4 TC2 = 2.11e-6) .MODEL RSOURCEMOD RES (TC1 = 0 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -3.7e-3 TC2 = -1.6e-5) .MODEL RVTEMPMOD RES (TC1 = -2.4e-3 TC2 = 7e-7) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -6.9 VOFF= -3.9) VON = -3.9 VOFF= -6.9) VON = -2.99 VOFF= 2.39) VON = 2.39 VOFF= -2.99) .ENDS NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. www.onsemi.com 7 HUF75344G3, HUF75344P3 SABER Electrical Model REV 3 February 1999 template huf75344 n2, n1, n3 electrical n2, n1, n3 { var i iscl d..model dbodymod = (is = 2.95e-12, cjo = 5.19e-9, tt = 5.90e-8, m = 0.55) d..model dbreakmod = () d..model dplcapmod = (cjo = 5.40e-9, is = 1e-30, n = 1, m = 0.88) m..model mmedmod = (type=_n, vto = 3.29, kp = 5.5, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 3.83, kp = 123, is = 1e-30, tox = 1) m..model mweakmod = (type=_n, vto = 2.90, kp = 0.04, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -6.9, voff = -3.9) sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -3.9, voff = -6.9) sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -2.99, voff = 2.39) sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 2.39, voff = -2.99) 10 RSLC1 51 i.it n8 n17 = 1 RDRAIN 6 8 EVTHRES + 19 8 21 DBODY EBREAK + 17 18 MSTRO - 8 LSOURCE 7 RSOURCE RLSOURCE S1A 12 m.mmed n16 n6 n8 n8 = model=mmedmod, l = 1u, w = 1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l = 1u, w = 1u m.mweak n16 n21 n8 n8 = model=mweakmod, l = 1u, w = 1u res.rbreak n17 n18 = 1, tc1 = 1.15e-3, tc2 = 2e-7 res.rdbody n71 n5 = 2.6e-3, tc1 = 1.05e-3, tc2 = 5e-7 res.rdbreak n72 n5 = 1.65e-1, tc1 = 1.15e-4, tc2 = 2.27e-6 res.rdrain n50 n16 = 1.94e-3, tc1 = 1.37e-2, tc2 = 3.85e-5 res.rgate n9 n20 = 0.36 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 26 res.rlsource n3 n7 = 11 res.rslc1 n5 n51 = 1e-6, tc1 = 1.45e-4, tc2 = 2.11e-6 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 3.5e-3, tc1 = 0, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -2.4e-3, tc2 = 7e-7 res.rvthres n22 n8 = 1, tc1 = -3.7e-3, tc2 = -1.6e-5 MWEAK MMED CIN 71 11 16 6 RLGATE RDBODY DBREAK 50 EVTEMP RGATE + 18 22 9 20 l.ldrain n2 n5 = 1e-9 l.lgate n1 n9 = 2.6e-9 l.lsource n3 n7 = 1.1e-9 k.kl i(l.lgate) i(l.lsource) = l(l.lgate), l(l.lsource), 0.0085 72 ISCL + GATE 1 RLDRAIN RDBREAK RSLC2 ESG LGATE DRAIN 2 5 - c.ca n12 n8 = 4.9e-9 c.cb n15 n14 = 4.75e-9 c.cin n6 n8 = 2.85e-9 d.dbody n7 n71 = model=dbodymod d.dbreak n72 n11 = model=dbreakmod d.dplcap n10 n5 = model=dplcapmod LDRAIN DPLCAP S2A 13 8 14 13 S1B CA RBREAK 15 17 18 RVTEMP S2B 13 CB 6 8 EGS 19 - - IT 14 + + VBAT 5 8 EDS - + 8 22 RVTHRES spe.ebreak n11 n7 n17 n18 = 59.7 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc = 1 equations { i (n51->n50) + = iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/400))** 3)) } } www.onsemi.com 8 SOURCE 3 HUF75344G3, HUF75344P3 SPICE Thermal Model th JUNCTION REV 5 February 1999 HUF75344 CTHERM1 th 6 5.0e-3 CTHERM2 6 5 1.0e-2 CTHERM3 5 4 1.3e-2 CTHERM4 4 3 1.5e-2 CTHERM5 3 2 2.2e-2 CTHERM6 2 tl 8.5e-2 RTHERM1 RTHERM1 th 6 6.0e-4 RTHERM2 6 5 3.5e-3 RTHERM3 5 4 2.5e-2 RTHERM4 4 3 4.8e-2 RTHERM5 3 2 1.6e-1 RTHERM6 2 tl 1.8e-1 RTHERM2 CTHERM1 6 CTHERM2 5 RTHERM3 CTHERM3 SABER Thermal Model SABER thermal model HUF75344 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 = 5.0e-3 ctherm.ctherm2 6 5 = 1.0e-2 ctherm.ctherm3 5 4 = 1.3e-2 ctherm.ctherm4 4 3 = 1.5e-2 ctherm.ctherm5 3 2 = 2.2e-2 ctherm.ctherm6 2 tl = 5.5e-2 rtherm.rtherm1 th 6 = 6.0e-4 rtherm.rtherm2 6 5 = 3.5e-3 rtherm.rtherm3 5 4 = 2.5e-2 rtherm.rtherm4 4 3 = 4.8e-2 rtherm.rtherm5 3 2 = 1.6e-1 rtherm.rtherm6 2 tl = 1.8e-1 } 4 RTHERM4 CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 tl www.onsemi.com 9 CASE ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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