Data Sheet A m p l i fy t h e H u m a n E x p e r i e n c e Comlinear CLC1003 (R) Low Distortion, Low Offset, RRIO Amplifier General Description Applications n Active filters n Sensor interface n High-speed transducer amp n Medical instrumentation n Probe equipment n Test equipment n Smoke detecters n Hand-held analytic instruments Typical Application - Current Sensing in 3-Phase Motor The COMLINEAR CLC1003 is a single channel, high-performance, voltage feedback amplifier with near precision performance, low input voltage noise, and ultra low distortion. The CLC1003 family of amplifiers offers 1mV maximum input offset voltage, 3.5nV/Hz broadband input voltage noise, and 0.00005% THD at 1kHz. These amplifiers also provide 55MHz gain bandwidth product and 12V/s slew rate making them well suited for applications requiring precision DC performance and high AC performance. These COMLINEAR high-performance amplifiers also offer a rail-to-rail input and output, simplifying single supply designs and offering larger dynamic range possibilities. The inputs extend beyond the rails by 500mV. The COMLINEAR CLC1003 family of amplifiers are designed to operate from 2.5V to 12V supplies and operate over the extended temperature range of -40C to +125. VCC + CLC1003 lph_1 - SPM (Smart Power Module) M lph_2 Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier features n 1mV max input offset voltage n 0.00005% THD at 1kHz n 5.3nV/Hz input voltage noise >10kHz n -90dB/-85dB HD2/HD3 at 100kHz, RL=100 n <-100dB HD2 and HD3 at 10kHz, RL=1k n Rail-to-Rail input and output n 55MHz unity gain bandwidth n 12V/s slew rate n +80mA, -55mA output current n -40C to +125C operating temperature range n Fully specified at 3V and 5V supplies n CLC1003: Pb-free SOT23-5, SOIC-8 n Future option CLC2003: Dual n Future option CLC4003: Quad Rev 1A lph_3 Ordering Information Part Number Package Pb-Free RoHS Compliant Operating Temperature Range Packaging Method CLC1003IST5X SOT23-5 Yes Yes -40C to +85C Reel CLC1003ISO8X* SOIC-8 Yes Yes -40C to +85C Reel CLC1003ISO8* SOIC-8 Yes Yes -40C to +85C Rail CLC1003AST5X SOT23-5 Yes Yes -40C to +125C Reel CLC1003ASO8X* SOIC-8 Yes Yes -40C to +125C Reel CLC1003ASO8* SOIC-8 Yes Yes -40C to +125C Rail *Preliminary Product Information Moisture sensitivity level for all parts is MSL-1. (c)2008 CADEKA Microcircuits LLC www.cadeka.com Data Sheet CLC1003 SOT Pin Configuration OUT 1 -V S 2 3 + -IN 4 CLC1003 SOIC Pin Configuration NC -IN1 Pin Name Description 1 OUT Output 2 -VS Negative supply 3 +IN Positive input 4 -IN Negative input 5 +VS Positive supply CLC1003 SOIC Pin Assignments Pin No. Pin Name Description No connect 1 NC 1 8 NC 2 -IN1 Negative input 2 7 +VS 3 +IN1 Positive input 4 -VS Negative supply 5 NC No connect 6 OUT Output 7 +VS Positive supply 8 NC No connect +IN1 3 6 OUT -V S 4 5 NC CLC2003 Pin Configuration OUT1 1 8 +VS -IN1 2 7 OUT2 +IN1 3 6 -IN2 -V S 4 5 +IN2 CLC4003 Pin Configuration CLC2003 (Future Option) Pin Configuration Pin No. Pin Name 1 OUT1 Description Output, channel 1 2 -IN1 Negative input, channel 1 3 +IN1 Positive input, channel 1 4 -VS 5 +IN2 Positive input, channel 2 6 -IN2 Negative input, channel 2 7 OUT2 Output, channel 2 8 +VS Negative supply Positive supply CLC4003 (Future Option) Pin Configuration Pin No. Pin Name Description 1 OUT1 Output, channel 1 1 14 OUT4 2 -IN1 Negative input, channel 1 -IN1 2 13 -IN4 3 +IN1 Positive input, channel 1 +IN1 3 12 +IN4 4 +VS Positive supply +VS 4 11 -VS 5 +IN2 Positive input, channel 2 6 -IN2 Negative input, channel 2 +IN2 5 10 +IN3 7 OUT2 Output, channel 2 -IN2 6 9 -IN3 8 OUT3 Output, channel 3 7 8 OUT3 OUT2 (c)2004-2008 CADEKA Microcircuits LLC 9 -IN3 Negative input, channel 3 10 +IN3 Positive input, channel 3 11 -VS 12 +IN4 Positive input, channel 4 13 -IN4 Negative input, channel 4 14 OUT4 Output, channel 4 Rev 1A OUT1 Pin No. Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier +IN +VS 5 CLC1003 SOT23-5 Pin Assignments Negative supply www.cadeka.com 2 Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the "Absolute Maximum Ratings". The device should not be operated at these "absolute" limits. Adhere to the "Recommended Operating Conditions" for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots. Supply Voltage Input Voltage Range Min Max Unit 0 -Vs -0.5V 14 +Vs +0.5V V V Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier Parameter Reliability Information Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Package Thermal Resistance 5-Lead SOT23 8-Lead SOIC 14-Lead SOIC Min Typ -65 Max Unit 150 150 260 C C C 221 100 88 C/W C/W C/W Notes: Package thermal resistance (qJA), JDEC standard, multi-layer test boards, still air. Recommended Operating Conditions Parameter Min Operating Temperature Range (CLC1003I) Operating Temperature Range (CLC1003A) Supply Voltage Range -40 -40 2.5 Typ Max Unit +85 +125 12 C C V Rev 1A (c)2004-2008 CADEKA Microcircuits LLC www.cadeka.com 3 Data Sheet Electrical Characteristics at +3V TA = 25C, Vs = +3V, Rf = 1k, RL = 1k to VS/2, G = 2; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units Frequency Domain Response -3dB Gain Bandwidth Product G = 10, VOUT = 0.05Vpp 31 MHz UGBW Unity Gain Bandwidth BWSS -3dB Bandwidth VOUT = 0.05Vpp , Rf = 0 50 MHz VOUT = 0.05Vpp 24 BWLS Large Signal Bandwidth MHz VOUT = 2Vpp 3.3 MHz Time Domain Response tR, tF Rise and Fall Time VOUT = 2V step; (10% to 90%) 150 ns tS Settling Time to 0.1% VOUT = 2V step 78 ns OS Overshoot VOUT = 2V step 0.3 % SR Slew Rate 2V step 11 V/s 2Vpp, 10kHz, RL = 1k -98 dBc 2Vpp, 100kHz, RL = 100 -85 dBc 2Vpp, 10kHz, RL = 1k -95 dBc -81 dBc Distortion/Noise Response HD2 2nd Harmonic Distortion HD3 3rd Harmonic Distortion THD Total Harmonic Distortion en Input Voltage Noise 2Vpp, 100kHz, RL = 100 1Vpp, 1kHz, G=1, RL = 2k 0.0005 % > 10kHz 5.5 nV/Hz > 100kHz 3.9 nV/Hz 0.088 mV V/C DC Performance VIO dVIO Input Offset Voltage Average Drift 1.3 Ib Input Bias Current -0.340 A dIb Average Drift 0.8 nA/C Ios Input Offset Current 0.2 nA PSRR Power Supply Rejection Ratio DC 100 dB AOL Open-Loop Gain VOUT = VS / 2 104 dB IS Supply Current per channel 1.85 mA Input Characteristics Input Resistance CIN Input Capacitance CMIR Common Mode Input Range CMRR Common Mode Rejection Ratio Non-inverting, G = 1 DC , Vcm=0.5V to 2.5V 30 M 1.1 pF -0.5 to 3.5 V 94 dB 0.085 to 2.80 V 0.04 to 2.91 V +75, -40 mA +95, -50 mA Rev 1A RIN Output Characteristics RL = 150 VOUT Output Voltage Swing IOUT Output Current ISC Short-Circuit Output Current RL = 1k VOUT = VS / 2 Notes: 1. 100% tested at 25C (c)2004-2008 CADEKA Microcircuits LLC www.cadeka.com Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier GBWP 4 Data Sheet Electrical Characteristics at 5V TA = 25C, Vs = 5V, Rf = 1k, RL = 1k to GND, G = 2; unless otherwise noted. Symbol Parameter Conditions Min Typ Max Units Frequency Domain Response -3dB Gain Bandwidth Product G = 10, VOUT = 0.05Vpp 35 MHz UGBW Unity Gain Bandwidth BWSS -3dB Bandwidth VOUT = 0.05Vpp , Rf = 0 55 MHz VOUT = 0.05Vpp 25 BWLS Large Signal Bandwidth MHz VOUT = 2Vpp 3.6 MHz Time Domain Response tR, tF Rise and Fall Time VOUT = 2V step; (10% to 90%) 125 ns tS Settling Time to 0.1% VOUT = 2V step 80 ns OS Overshoot VOUT = 2V step 0.3 % SR Slew Rate 4V step 12 V/s 2Vpp, 10kHz, RL = 1k -125 dBc 2Vpp, 100kHz, RL = 100 -90 dBc 2Vpp, 10kHz, RL = 1k -127 dBc -85 dBc Distortion/Noise Response HD2 2nd Harmonic Distortion HD3 3rd Harmonic Distortion THD Total Harmonic Distortion en Input Voltage Noise 2Vpp, 100kHz, RL = 100 1Vpp, 1kHz, G=1, RL = 2k 0.00005 % > 10kHz 5.3 nV/Hz > 100kHz 3.5 nV/Hz DC Performance VIO dVIO Ib dIb Input Offset Voltage(1) -1 0.050 -2.6 -0.30 Average Drift 1 1.3 Input Bias Current (1) Average Drift V/C 2.6 0.85 A nA/C Ios Input Offset Current (1) PSRR Power Supply Rejection Ratio (1) DC 82 100 dB AOL Open-Loop Gain (1) VOUT = VS / 2 95 115 dB IS Supply Current per channel 2.2 Non-inverting, G = 1 30 M 1 pF (1) 0.2 mV 0.7 2.75 A mA Input Characteristics RIN Input Resistance CIN Input Capacitance CMIR Common Mode Input Range CMRR Common Mode Rejection Ratio (1) DC , Vcm= -3V to 3V 70 5.5 V 95 dB -4.826 to 4.534 V RL = 150 VOUT Output Voltage Swing IOUT Output Current ISC Short-Circuit Output Current RL = 1k (1) VOUT = VS / 2 -4.7 -4.93 to 4.85 4.7 Rev 1A Output Characteristics V +80, -55 mA +115, -90 mA Notes: 1. 100% tested at 25C (c)2004-2008 CADEKA Microcircuits LLC www.cadeka.com Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier GBWP 5 Data Sheet Typical Performance Characteristics TA = 25C, Vs = 5V, Rf = 1k, RL = 1k to GND, G = 2; unless otherwise noted. Non-Inverting Frequency Response Inverting Frequency Response 1 0 0 -1 Normalized Gain (dB) Normalized Gain (dB) G=1 Rf = 0 G=2 -3 G=5 G = 10 -6 G = -1 -2 G = -2 -3 G = -5 G = -10 -4 -5 -6 VOUT = 0.05Vpp -9 VOUT = 0.05Vpp -7 0.1 1 10 100 0.1 1 Frequency (MHz) 10 100 10 100 Frequency (MHz) Frequency Response vs. CL Frequency Response vs. CL without RS 1 4 -1 2 CL = 500pF Rs = 10 -2 Normalized Gain (dB) Normalized Gain (dB) 0 CL = 1000pF Rs = 7.5 -3 CL = 3000pF Rs = 4 -4 -5 CL = 500pF 0 CL = 300pF -2 CL = 100pF -4 CL = 50pF -6 -6 -7 -8 0.1 1 10 100 CL = 10pF VOUT = 0.05Vpp Rs = 0 VOUT = 0.05Vpp 0.1 1 Frequency (MHz) Frequency (MHz) Frequency Response vs. VOUT Frequency Response vs. RL 3 2 Normalized Gain (dB) Normalized Gain (dB) 0 VOUT = 1Vpp VOUT = 2Vpp -3 VOUT = 4Vpp -6 RL = 150 0 RL = 2.5K -1 RL = 1K -2 -3 -4 -5 -9 Rev 1A RL = 50 1 VOUT = 0.05Vpp -6 0.1 1 10 Frequency (MHz) (c)2004-2008 CADEKA Microcircuits LLC 100 0.1 1 10 100 Frequency (MHz) www.cadeka.com Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier 3 6 Data Sheet Typical Performance Characteristics TA = 25C, Vs = 5V, Rf = 1k, RL = 1k to GND, G = 2; unless otherwise noted. Non-Inverting Frequency Response at VS = 3V Inverting Frequency Response at VS = 3V 1 0 0 -1 Normalized Gain (dB) Normalized Gain (dB) G=1 Rf = 0 G=2 -3 G=5 G = 10 -6 G = -1 -2 G = -2 -3 G = -5 G = -10 -4 -5 -6 VOUT = 0.05Vpp -9 VOUT = 0.05Vpp -7 0.1 1 10 100 0.1 1 Frequency (MHz) 10 Frequency Response vs. VOUT at VS = 3V Frequency Response vs. RL at VS = 3V 3 2 RL = 50 1 0 Normalized Gain (dB) Normalized Gain (dB) 100 Frequency (MHz) VOUT = 1Vpp VOUT = 2Vpp -3 VOUT = 2.5Vpp -6 RL = 150 0 RL = 2.5K -1 RL = 1K -2 -3 -4 -5 -9 VOUT = 0.05Vpp -6 0.1 1 10 100 0.1 1 Frequency (MHz) 10 100 Frequency (MHz) -3dB Bandwidth vs. Output Voltage at VS = 3V -3dB Bandwidth vs. Output Voltage 24 Rev 1A 24 21 -3dB Bandwidth (MHz) -3dB Bandwidth (MHz) 21 18 15 12 9 6 3 18 15 12 9 6 3 0 0 0.0 0.5 1.0 1.5 VOUT (VPP) (c)2004-2008 CADEKA Microcircuits LLC 2.0 2.5 Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier 3 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 VOUT (VPP) www.cadeka.com 7 Data Sheet Typical Performance Characteristics - Continued TA = 25C, Vs = 5V, Rf = 1k, RL = 1k to GND, G = 2; unless otherwise noted. Open Loop Gain and Phase vs. Frequency CMIR -75 PHASE -150 20 -225 GAIN 0 -300 -20 -375 -40 -450 -60 0.3 PHASE () 40 0.4 Vout (V) 60 GAIN (dB) 0.5 0 0.1 0 -0.1 -525 10 100 1,000 10,000 100,000 0.2 -6 1,000,000 -4 -2 0 2 4 6 Vni(V) FREQ (KHz) Input Voltage Noise CMIR at VS = 3V 14 0.5 12 0.4 11 10 0.3 9 Vout (V) Input Voltage Noise (nV/Hz) 13 8 7 6 0.2 0.1 5 4 0 3 2 -0.1 0.0001 0.001 0.01 0.1 1 -1 -0.5 0 0.5 Frequency (MHz) 2 2.5 3 3.5 4 PSRR vs. Frequency 110 100 100 90 90 CMRR (dB) 110 80 70 80 70 60 60 50 50 40 Rev 1A CMRR (dB) 1.5 Vni(V) CMRR vs. Frequency 0.001 1 40 0.01 0.1 1 Frequency (MHz) (c)2004-2008 CADEKA Microcircuits LLC 10 100 1000 0.001 Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier 80 0.01 0.1 1 10 100 1000 Frequency (MHz) www.cadeka.com 8 Data Sheet Typical Performance Characteristics - Continued TA = 25C, Vs = 5V, Rf = 1k, RL = 1k to GND, G = 2; unless otherwise noted. 2nd Harmonic Distortion vs. RL 3rd Harmonic Distortion vs. RL -60 RL = 100 RL = 10K -70 Distortion (dBc) Distortion (dBc) -60 -80 -90 RL = 10K RL = 1K -70 RL = 100 -80 -90 RL = 1K RL = 500 RL = 500 -100 -100 VOUT = 2Vpp VOUT = 2Vpp -110 -110 100 200 300 400 500 600 700 800 900 100 1000 200 300 400 2nd Harmonic Distortion vs. VOUT 600 700 800 900 1000 3rd Harmonic Distortion vs. VOUT -40 -30 -40 -50 -50 -60 Distortion (dBc) Distortion (dBc) 500 Frequency (KHz) Frequency (KHz) RF=RL=1K -70 -80 -60 RF=RL=1K -70 -80 RF=RL=10K RF=RL=10K -90 -90 FREQ = 500KHz -100 FREQ = 500KHz -100 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 Output Amplitude (Vpp) 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 Output Amplitude (Vpp) THD vs. Frequency -65 Rev 1A -70 -75 THD (dB) Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier -50 -50 -80 -85 -90 VOUT = 1Vpp RL = 1K AV+1 -95 -100 100 200 300 400 500 600 700 800 900 1000 Frequency (kHz) (c)2004-2008 CADEKA Microcircuits LLC www.cadeka.com 9 Data Sheet Typical Performance Characteristics - Continued TA = 25C, Vs = 5V, Rf = 1k, RL = 1k to GND, G = 2; unless otherwise noted. 3rd Harmonic Distortion vs. RL at VS = 3V -40 -40 -50 -50 -70 -80 RL = 10K RL = 1K RL = 500 Distortion (dBc) RL = 100 -60 -60 RL = 100 -70 -80 RL = 500 RL = 10K RL = 1K -90 -90 VOUT = 2Vpp VOUT = 2Vpp -100 -100 100 200 300 400 500 600 700 800 900 100 1000 200 300 500 600 700 800 900 1000 3rd Harmonic Distortion vs. VOUT at VS = 3V -40 -40 -50 -50 -60 Distortion (dBc) Distortion (dBc) 2nd Harmonic Distortion vs. VOUT at VS = 3V RF=RL=10K -70 -80 400 Frequency (KHz) Frequency (KHz) RF=RL=1K -90 -60 RF=RL=10K -70 -80 RF=RL=1K -90 FREQ = 500KHz FREQ = 500KHz -100 -100 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 Output Amplitude (Vpp) 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 Output Amplitude (Vpp) THD vs. Frequency at VS = 3V -65 Rev 1A -70 -75 THD (dB) Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier Distortion (dBc) 2nd Harmonic Distortion vs. RL at VS = 3V -80 -85 -90 VOUT = 1Vpp RL = 1K AV+1 -95 -100 100 200 300 400 500 600 700 800 900 1000 Frequency (kHz) (c)2004-2008 CADEKA Microcircuits LLC www.cadeka.com 10 Data Sheet Typical Performance Characteristics - Continued TA = 25C, Vs = 5V, Rf = 1k, RL = 1k to GND, G = 2; unless otherwise noted. Small Signal Pulse Response Small Signal Pulse Response at VS = 3V 1.6 0.25 1.55 Voltage (V) 0.5 Voltage (V) 1.65 0 1.5 -0.25 1.45 -0.5 1.4 -0.75 1.35 0 0.5 1 1.5 2 0 0.5 Time (ns) 1.5 2 Large Signal Pulse Response at VS = 3V 6 3 4 2.5 2 2 Voltage (V) Voltage (V) Large Signal Pulse Response 0 1.5 -2 1 -4 0.5 -6 0 0 1 2 3 4 5 6 7 8 9 10 0 0.5 1 Time (ns) 1.5 2 Time (ns) Input Offset Voltage vs. Temperature Input Offset Voltage Distribution 5000 0.05 4000 Rev 1A 0.1 0 3000 Units Vio (V) 1 Time (ns) -0.05 2000 -0.1 1000 -0.15 (c)2004-2008 CADEKA Microcircuits LLC 100 120 0.98 80 0.7 60 0.42 40 Temperature (C) 0.14 20 -0.14 0 -0.42 -20 -0.7 -40 -0.98 0 -0.2 Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier 0.75 Input Offset Voltage (mV) www.cadeka.com 11 Data Sheet Application Information perature, the package thermal resistance value ThetaJA (JA) is used along with the total die power dissipation. Basic Operation +Vs Input 6.8F Output RL 0.1F Rf 6.8F Figure 1. Typical Non-Inverting Gain Circuit R1 Input Rg Pload = ((VLOAD)RMS2)/Rloadeff The effective load resistor (Rloadeff) will need to include the effect of the feedback network. For instance, RL || (Rf + Rg) 6.8F Output 0.1F 6.8F -Vs Vsupply = VS+ - VS- Rloadeff in figure 3 would be calculated as: 0.1F + Psupply = Vsupply x IRMS supply Power delivered to a purely resistive load is: G = 1 + (Rf/Rg) -Vs +Vs In order to determine PD, the power dissipated in the load needs to be subtracted from the total power delivered by the supplies. Supply power is calculated by the standard power equation. - Rg Where TAmbient is the temperature of the working environment. PD = Psupply - Pload 0.1F + TJunction = TAmbient + (JA x PD) RL Rf These measurements are basic and are relatively easy to perform with standard lab equipment. For design purposes however, prior knowledge of actual signal levels and load impedance is needed to determine the dissipated power. Here, PD can be found from PD = PQuiescent + PDynamic - PLoad G = - (Rf/Rg) For optimum input offset voltage set R1 = Rf || Rg Figure 2. Typical Inverting Gain Circuit Power dissipation should not be a factor when operating under the stated 300 ohm load condition. However, applications with low impedance, DC coupled loads should be analyzed to ensure that maximum allowed junction temperature is not exceeded. Guidelines listed below can be used to verify that the particular application will not cause the device to operate beyond it's intended operating range. Maximum power levels are set by the absolute maximum junction rating of 150C. To calculate the junction tem- (c)2004-2008 CADEKA Microcircuits LLC Rev 1A Power Dissipation Quiescent power can be derived from the specified IS values along with known supply voltage, VSupply. Load power can be calculated as above with the desired signal amplitudes using: Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier Figures 1 and 2 illustrate typical circuit configurations for non-inverting, inverting, and unity gain topologies for dual supply applications. They show the recommended bypass capacitor values and overall closed loop gain equations. (VLOAD)RMS = VPEAK / 2 ( ILOAD)RMS = ( VLOAD)RMS / Rloadeff The dynamic power is focused primarily within the output stage driving the load. This value can be calculated as: PDYNAMIC = (VS+ - VLOAD)RMS x ( ILOAD)RMS Assuming the load is referenced in the middle of the power rails or Vsupply/2. Figure 3 shows the maximum safe power dissipation in the package vs. the ambient temperature for the packages available. www.cadeka.com 12 Data Sheet For a given load capacitance, adjust RS to optimize the tradeoff between settling time and bandwidth. In general, reducing RS will increase bandwidth at the expense of additional overshoot and ringing. 2 SOIC-8 1.5 SOT23-6 Overdrive Recovery 1 0.5 0 -40 -20 0 20 40 60 80 Ambient Temperature (C) Figure 3. Maximum Power Derating An overdrive condition is defined as the point when either one of the inputs or the output exceed their specified voltage range. Overdrive recovery is the time needed for the amplifier to return to its normal or linear operating point. The recovery time varies, based on whether the input or output is overdriven and by how much the range is exceeded. The CLCx003 will typically recover in less than 20ns from an overdrive condition. Figure 5 shows the CLC1003 in an overdriven condition. 3 Driving Capacitive Loads Input 2 2 Input Voltage (V) 1 1 Input 1 0 0 Output -1 -1 Output Voltage (V) Increased phase delay at the output due to capacitive loading can cause ringing, peaking in the frequency response, and possible unstable behavior. Use a series resistance, RS, between the amplifier and the load to help improve stability and settling performance. Refer to Figure 4. 2 VIN = .8Vpp G=5 -1 + Rs - Output CL Rf -2 -2 -3 RL -2 0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 Time (us) Rg Figure 5. Overdrive Recovery Figure 4. Addition of RS for Driving Capacitive Loads CL (pF) RS () -3dB BW (MHz) 500 10 27 1000 7.5 20 3000 4 15 Table 1: Recommended RS vs. CL Offset Analysis There are three sources of offset contribution to consider; input bias current, input bias current mismatch, and input offset voltage. The input bias currents are assumed to be equal with and additional offset current in one of the inputs to account for mismatch. The bias currents will not affect the offset as long as the parallel combination of Rf and Rg matches Rt. Refer to Figure 6. +Vs Rf Rg - IN Rt CLC1003 + RL -Vs Figure 6: Circuit for Evaluating Offset (c)2004-2008 CADEKA Microcircuits LLC www.cadeka.com 13 Rev 1A The CLC1003 family of amplifiers is capable of driving up to 300pF directly, with no series resistance. Directly driving 500pF causes over 4dB of frequency peaking, as shown in the plot on page 6. Table 1 provides the recommended RS for various capacitive loads. The recommended RS values result in <=1dB peaking in the frequency response. The Frequency Response vs. CL plots, on page 6, illustrates the response of the CLCx003. Considerations for Offset and Noise Performance Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier Maximum Power Dissipation (W) 2.5 Data Sheet Rt = Rg||Rf Where Vorext is the noise due to the external resistors and is given by: 2 v o = en 1 + RF RG 2 RF RG + eG 2 2 + eF The complete equation can be simplified to: This equation can be rearranged to solve for Rg: 2 v o Rg = (Rt * Rf) / (Rf - Rt) ( 2 ) ( ) = 3 4kT G RT + enG ( + 2 in RT 2 ) The other consideration is desired gain (G) which is: G = (1 + Rf/Rg) By plugging in the value for Rg we get Rf = G * Rt And Rg can be written in terms of Rt and G as follows: Rg = (G * Rt) / (G - 1) The complete input offset equation is now only dependent on the voltage offset and input offset terms given by: VI OS = 2 2 ( VIO ) + (IOS RT) And the output offset is: VO OS = G 2 It's easy to see that the effect of amplifier voltage noise is proportionate to gain and will tend to dominate at large gains. The other terms will have their greatest impact at large Rt values at lower gains. Layout Considerations General layout and supply bypassing play major roles in high frequency performance. CADEKA has evaluation boards to use as a guide for high frequency layout and as aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: * Include 6.8F and 0.1F ceramic capacitors for power supply decoupling 2 ( V IO ) + (I OS RT ) * Place the 6.8F capacitor within 0.75 inches of the power pin Noise analysis * Place the 0.1F capacitor within 0.1 inches of the power pin The complete equivalent noise circuit is shown in Figure 7. * Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance Rg Rf +- +- +- + +- RL w + - Refer to the evaluation board layouts below for more information. CLC1003 Rg Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of these devices: Figure 7: Complete Equivalent Noise Circuit The complete noise equation is given by: 2 v o 2 RF = vorext + en 1 + RG 2 + ibp RT 1 + (c)2004-2008 CADEKA Microcircuits LLC RF RG Evaluation Board # 2 ( + ibn RF 2 ) CEB002 CEB003 Products CLC1003 in SOT23-5 CLC1003 in SOIC-8 www.cadeka.com 14 Rev 1A * Minimize all trace lengths to reduce series inductances - Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier The first place to start is to determine the source resistance. If it is very small an additional resistance may need to be added to keep the values of Rf and Rg to practical levels. For this analysis we assume that Rt is the total resistance present on the non-inverting input. This gives us one equation that we must solve: Data Sheet Evaluation Board Schematics Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier Evaluation board schematics and layouts are shown in Figures 8-13. These evaluation boards are built for dual- supply operation. Follow these steps to use the board in a single-supply application: 1. Short -Vs to ground. 2. Use C3 and C4, if the -VS pin of the amplifier is not directly connected to the ground plane. Figure 10. CEB002 Bottom View Figure 8. CEB002 Schematic Figure 11. CEB003 Top View Rev 1A Figure 9. CEB002 Top View (c)2004-2008 CADEKA Microcircuits LLC Figure 12. CEB003 Bottom View www.cadeka.com 15 Data Sheet Mechanical Dimensions SOT23-5 Package Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplifier SOIC-8 Rev 1A For additional information regarding our products, please visit CADEKA at: cadeka.com CADEKA Headquarters Loveland, Colorado T: 970.663.5452 T: 877.663.5415 (toll free) CADEKA, the CADEKA logo design, and Comlinear and the Comlinear logo design, are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright (c)2008 by CADEKA Microcircuits LLC. All rights reserved. A m p l i fy t h e H u m a n E x p e r i e n c e