Data Sheet
©2008 CADEKA Microcircuits LLC www.cadeka.com
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplier Rev 1A
Comlinear® CLC1003
Low Distortion, Low Offset, RRIO Amplier
Amplify the Human Experience
FEATURES
n 1mV max input offset voltage
n 0.00005% THD at 1kHz
n 5.3nV/√Hz input voltage noise >10kHz
n -90dB/-85dB HD2/HD3 at 100kHz, RL=100Ω
n <-100dB HD2 and HD3 at 10kHz, RL=1kΩ
n Rail-to-Rail input and output
n 55MHz unity gain bandwidth
n 12V/μs slew rate
n +80mA, -55mA output current
n -40°C to +125°C operating temperature
range
n Fully specied at 3V and ±5V supplies
n CLC1003: Pb-free SOT23-5, SOIC-8
n Future option CLC2003: Dual
n Future option CLC4003: Quad
APPLICATIONS
n Active lters
n Sensor interface
n High-speed transducer amp
n Medical instrumentation
n Probe equipment
n Test equipment
n Smoke detecters
n Hand-held analytic instruments
General Description
The COMLINEAR CLC1003 is a single channel, high-performance, voltage
feedback amplier with near precision performance, low input voltage noise,
and ultra low distortion. The CLC1003 family of ampliers offers 1mV maxi-
mum input offset voltage, 3.5nV/√Hz broadband input voltage noise, and
0.00005% THD at 1kHz. These ampliers also provide 55MHz gain bandwidth
product and 12V/μs slew rate making them well suited for applications requir-
ing precision DC performance and high AC performance. These COMLINEAR
high-performance ampliers also offer a rail-to-rail input and output, simplify-
ing single supply designs and offering larger dynamic range possibilities. The
inputs extend beyond the rails by 500mV.
The COMLINEAR CLC1003 family of ampliers are designed to operate from
2.5V to 12V supplies and operate over the extended temperature range of
-40°C to +125°.
Typical Application - Current Sensing in 3-Phase Motor
Ordering Information
Part Number Package Pb-Free RoHS Compliant Operating Temperature Range Packaging Method
CLC1003IST5X SOT23-5 Yes Yes -40°C to +85°C Reel
CLC1003ISO8X* SOIC-8 Yes Yes -40°C to +85°C Reel
CLC1003ISO8* SOIC-8 Yes Yes -40°C to +85°C Rail
CLC1003AST5X SOT23-5 Yes Yes -40°C to +125°C Reel
CLC1003ASO8X* SOIC-8 Yes Yes -40°C to +125°C Reel
CLC1003ASO8* SOIC-8 Yes Yes -40°C to +125°C Rail
*Preliminary Product Information
Moisture sensitivity level for all parts is MSL-1.
+
–
CLC1003 lph_1
lph_2
lph_3
VCC
SPM
(Smart
Power
Module) M
Data Sheet
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 2
CLC1003 SOT23-5 Pin Assignments
Pin No. Pin Name Description
1 OUT Output
2-VSNegative supply
3 +IN Positive input
4 -IN Negative input
5 +VSPositive supply
CLC1003 SOIC Pin Assignments
Pin No. Pin Name Description
1 NC No connect
2 -IN1 Negative input
3 +IN1 Positive input
4-VSNegative supply
5 NC No connect
6 OUT Output
7 +VSPositive supply
8NC No connect
CLC2003 (Future Option) Pin Conguration
Pin No. Pin Name Description
1 OUT1 Output, channel 1
2 -IN1 Negative input, channel 1
3 +IN1 Positive input, channel 1
4-VSNegative supply
5 +IN2 Positive input, channel 2
6 -IN2 Negative input, channel 2
7 OUT2 Output, channel 2
8 +VSPositive supply
CLC4003 (Future Option) Pin Conguration
Pin No. Pin Name Description
1 OUT1 Output, channel 1
2 -IN1 Negative input, channel 1
3 +IN1 Positive input, channel 1
4 +VSPositive supply
5 +IN2 Positive input, channel 2
6 -IN2 Negative input, channel 2
7 OUT2 Output, channel 2
8 OUT3 Output, channel 3
9 -IN3 Negative input, channel 3
10 +IN3 Positive input, channel 3
11 -VSNegative supply
12 +IN4 Positive input, channel 4
13 -IN4 Negative input, channel 4
14 OUT4 Output, channel 4
CLC1003 SOT Pin Conguration
CLC2003 Pin Conguration
2
3
45
6
7
8
OUT2
+IN1 -IN2
+IN2
1
-IN1
OUT1
-V
S
+V
S
CLC4003 Pin Conguration
2
3
4 11
12
13
14
-IN4
+IN1
OUT4
+IN4
1
-IN1
OUT1
5
6
7
OUT2
-IN2
+IN2
8
9
10 +IN3
-IN3
OUT3
+VS -VS
2
3
5
4
+IN
+VS
-IN
1
-VS
OUT
-
+
CLC1003 SOIC Pin Conguration
2
3
45
6
7
8
+IN1
NC
OUT
NC
1
-IN1
NC
-V
S
+V
S
Data Sheet
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 3
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper de-
vice function. The information contained in the Electrical Characteristics tables and Typical Performance plots reect the
operating conditions noted on the tables and plots.
Parameter Min Max Unit
Supply Voltage 0 14 V
Input Voltage Range -Vs -0.5V +Vs +0.5V V
Reliability Information
Parameter Min Typ Max Unit
Junction Temperature 150 °C
Storage Temperature Range -65 150 °C
Lead Temperature (Soldering, 10s) 260 °C
Package Thermal Resistance
5-Lead SOT23 221 °C/W
8-Lead SOIC 100 °C/W
14-Lead SOIC 88 °C/W
Notes:
Package thermal resistance (qJA), JDEC standard, multi-layer test boards, still air.
Recommended Operating Conditions
Parameter Min Typ Max Unit
Operating Temperature Range (CLC1003I) -40 +85 °C
Operating Temperature Range (CLC1003A) -40 +125 °C
Supply Voltage Range 2.5 12 V
Data Sheet
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 4
Electrical Characteristics at +3V
TA = 25°C, Vs = +3V, Rf = 1kΩ, RL = 1kΩ to VS/2, G = 2; unless otherwise noted.
Symbol Parameter Conditions Min Typ Max Units
Frequency Domain Response
GBWP -3dB Gain Bandwidth Product G = 10, VOUT = 0.05Vpp 31 MHz
UGBW Unity Gain Bandwidth VOUT = 0.05Vpp , Rf = 0 50 MHz
BWSS -3dB Bandwidth VOUT = 0.05Vpp 24 MHz
BWLS Large Signal Bandwidth VOUT = 2Vpp 3.3 MHz
Time Domain Response
tR, tFRise and Fall Time VOUT = 2V step; (10% to 90%) 150 ns
tSSettling Time to 0.1% VOUT = 2V step 78 ns
OS Overshoot VOUT = 2V step 0.3 %
SR Slew Rate 2V step 11 V/µs
Distortion/Noise Response
HD2 2nd Harmonic Distortion
2Vpp, 10kHz, RL = 1kΩ -98 dBc
2Vpp, 100kHz, RL = 100Ω -85 dBc
HD3 3rd Harmonic Distortion
2Vpp, 10kHz, RL = 1kΩ -95 dBc
2Vpp, 100kHz, RL = 100Ω -81 dBc
THD Total Harmonic Distortion 1Vpp, 1kHz, G=1, RL = 2kΩ 0.0005 %
enInput Voltage Noise
> 10kHz 5.5 nV/√Hz
> 100kHz 3.9 nV/√Hz
DC Performance
VIO Input Offset Voltage 0.088 mV
dVIO Average Drift 1.3 µV/°C
IbInput Bias Current -0.340 μA
dIb Average Drift 0.8 nA/°C
Ios Input Offset Current 0.2 nA
PSRR Power Supply Rejection Ratio DC 100 dB
AOL Open-Loop Gain VOUT = VS / 2 104 dB
ISSupply Current per channel 1.85 mA
Input Characteristics
RIN Input Resistance Non-inverting, G = 1 30 MΩ
CIN Input Capacitance 1.1 pF
CMIR Common Mode Input Range -0.5 to
3.5 V
CMRR Common Mode Rejection Ratio DC , Vcm=0.5V to 2.5V 94 dB
Output Characteristics
VOUT Output Voltage Swing
RL = 150Ω 0.085 to
2.80 V
RL = 1kΩ 0.04 to
2.91 V
IOUT Output Current +75, -40 mA
ISC Short-Circuit Output Current VOUT = VS / 2 +95, -50 mA
Notes:
1. 100% tested at 25°C
Data Sheet
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 5
Electrical Characteristics at ±5V
TA = 25°C, Vs = ±5V, Rf = 1kΩ, RL = 1kΩ to GND, G = 2; unless otherwise noted.
Symbol Parameter Conditions Min Typ Max Units
Frequency Domain Response
GBWP -3dB Gain Bandwidth Product G = 10, VOUT = 0.05Vpp 35 MHz
UGBW Unity Gain Bandwidth VOUT = 0.05Vpp , Rf = 0 55 MHz
BWSS -3dB Bandwidth VOUT = 0.05Vpp 25 MHz
BWLS Large Signal Bandwidth VOUT = 2Vpp 3.6 MHz
Time Domain Response
tR, tFRise and Fall Time VOUT = 2V step; (10% to 90%) 125 ns
tSSettling Time to 0.1% VOUT = 2V step 80 ns
OS Overshoot VOUT = 2V step 0.3 %
SR Slew Rate 4V step 12 V/µs
Distortion/Noise Response
HD2 2nd Harmonic Distortion
2Vpp, 10kHz, RL = 1kΩ -125 dBc
2Vpp, 100kHz, RL = 100Ω -90 dBc
HD3 3rd Harmonic Distortion
2Vpp, 10kHz, RL = 1kΩ -127 dBc
2Vpp, 100kHz, RL = 100Ω -85 dBc
THD Total Harmonic Distortion 1Vpp, 1kHz, G=1, RL = 2kΩ 0.00005 %
enInput Voltage Noise
> 10kHz 5.3 nV/√Hz
> 100kHz 3.5 nV/√Hz
DC Performance
VIO Input Offset Voltage(1) -1 0.050 1 mV
dVIO Average Drift 1.3 µV/°C
IbInput Bias Current (1) -2.6 -0.30 2.6 μA
dIb Average Drift 0.85 nA/°C
Ios Input Offset Current (1) 0.2 0.7 μA
PSRR Power Supply Rejection Ratio (1) DC 82 100 dB
AOL Open-Loop Gain (1) VOUT = VS / 2 95 115 dB
ISSupply Current (1) per channel 2.2 2.75 mA
Input Characteristics
RIN Input Resistance Non-inverting, G = 1 30 MΩ
CIN Input Capacitance 1 pF
CMIR Common Mode Input Range ±5.5 V
CMRR Common Mode Rejection Ratio (1) DC , Vcm= -3V to 3V 70 95 dB
Output Characteristics
VOUT Output Voltage Swing
RL = 150Ω -4.826
to 4.534 V
RL = 1kΩ (1) -4.7 -4.93 to
4.85 4.7 V
IOUT Output Current +80, -55 mA
ISC Short-Circuit Output Current VOUT = VS / 2 +115, -90 mA
Notes:
1. 100% tested at 25°C
Data Sheet
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 6
Typical Performance Characteristics
TA = 25°C, Vs = ±5V, Rf = 1kΩ, RL = 1kΩ to GND, G = 2; unless otherwise noted.
Frequency Response vs. VOUT Frequency Response vs. RL
Frequency Response vs. CLFrequency Response vs. CL without RS
Non-Inverting Frequency Response Inverting Frequency Response
-9
-6
-3
0
3
0.1 110 100
Normalized Gain (dB)
Frequency (MHz)
-7
-6
-5
-4
-3
-2
-1
0
1
0.1 110 100
Normalized Gain (dB)
Frequency (MHz)
-7
-6
-5
-4
-3
-2
-1
0
1
0.1 110 100
Normalized Gain (dB)
Frequency (MHz)
-8
-6
-4
-2
0
2
4
0.1 110 100
Normalized Gain (dB)
Frequency (MHz)
-9
-6
-3
0
3
0.1 110 100
Normalized Gain (dB)
Frequency (MHz)
-6
-5
-4
-3
-2
-1
0
1
2
0.1 110 100
Normalized Gain (dB)
Frequency (MHz)
Data Sheet
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 7
Typical Performance Characteristics
TA = 25°C, Vs = ±5V, Rf = 1kΩ, RL = 1kΩ to GND, G = 2; unless otherwise noted.
-3dB Bandwidth vs. Output Voltage at VS = 3V -3dB Bandwidth vs. Output Voltage
Frequency Response vs. VOUT at VS = 3V Frequency Response vs. RL at VS = 3V
Non-Inverting Frequency Response at VS = 3V Inverting Frequency Response at VS = 3V
-9
-6
-3
0
3
0.1 110 100
Normalized Gain (dB)
Frequency (MHz)
-7
-6
-5
-4
-3
-2
-1
0
1
0.1 110 100
Normalized Gain (dB)
Frequency (MHz)
-9
-6
-3
0
3
0.1 110 100
Normalized Gain (dB)
Frequency (MHz)
-6
-5
-4
-3
-2
-1
0
1
2
0.1 110 100
Normalized Gain (dB)
Frequency (MHz)
0
3
6
9
12
15
18
21
24
0.0 0.5 1.0 1.5 2.0 2.5
-3dB Bandwidth (MHz)
V
OUT
(V
PP
)
0
3
6
9
12
15
18
21
24
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
-3dB Bandwidth (MHz)
V
OUT
(V
PP
)
Data Sheet
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 8
Typical Performance Characteristics - Continued
TA = 25°C, Vs = ±5V, Rf = 1kΩ, RL = 1kΩ to GND, G = 2; unless otherwise noted.
CMRR vs. Frequency PSRR vs. Frequency
Input Voltage Noise CMIR at VS = 3V
Open Loop Gain and Phase vs. Frequency CMIR
-525
-450
-375
-300
-225
-150
-75
0
-60
-40
-20
0
20
40
60
80
10 100 1,000 10,000 100,000 1,000,000
PHASE (°)
GAIN (dB)
F R E Q ( K H z )
-0.1
0
0.1
0.2
0.3
0.4
0.5
-6 -4 -2 0 2 4 6
Vout (V)
Vni(V)
2
3
4
5
6
7
8
9
10
11
12
13
14
0.0001 0.001 0.01 0.1 1
Input Voltage Noise (nV/√Hz)
Frequency (MHz)
-0.1
0
0.1
0.2
0.3
0.4
0.5
-1 -0.5 00.5 11.5 22.5 33.5 4
Vout (V)
Vni(V)
40
50
60
70
80
90
100
110
0.001 0.01 0.1 110 100
CMRR (dB)
Frequency (MHz)
40
50
60
70
80
90
100
110
0.001 0.01 0.1 110 100
CMRR (dB)
Frequency (MHz)
Data Sheet
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 9
Typical Performance Characteristics - Continued
TA = 25°C, Vs = ±5V, Rf = 1kΩ, RL = 1kΩ to GND, G = 2; unless otherwise noted.
THD vs. Frequency
2nd Harmonic Distortion vs. VOUT 3rd Harmonic Distortion vs. VOUT
2nd Harmonic Distortion vs. RL 3rd Harmonic Distortion vs. RL
-110
-100
-90
-80
-70
-60
-50
100 200 300 400 500 600 700 800 900 1000
Distortion (dBc)
Frequency (KHz)
-110
-100
-90
-80
-70
-60
-50
100 200 300 400 500 600 700 800 900 1000
Distortion (dBc)
Frequency (KHz)
-100
-90
-80
-70
-60
-50
-40
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7 . 5 8.5 9.5
Distortion (dBc)
Output Amplitude (Vpp)
-100
-90
-80
-70
-60
-50
-40
-30
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7 . 5 8.5 9.5
Distortion (dBc)
Output Amplitude (Vpp)
-100
-95
-90
-85
-80
-75
-70
-65
100 200 300 400 500 600 700 800 900 1000
THD (dB)
Frequency (kHz)
Data Sheet
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 10
Typical Performance Characteristics - Continued
TA = 25°C, Vs = ±5V, Rf = 1kΩ, RL = 1kΩ to GND, G = 2; unless otherwise noted.
THD vs. Frequency at VS = 3V
2nd Harmonic Distortion vs. VOUT at VS = 3V 3rd Harmonic Distortion vs. VOUT at VS = 3V
2nd Harmonic Distortion vs. RL at VS = 3V 3rd Harmonic Distortion vs. RL at VS = 3V
-100
-90
-80
-70
-60
-50
-40
100 200 300 400 500 600 700 800 900 1000
Distortion (dBc)
Frequency (KHz)
-100
-90
-80
-70
-60
-50
-40
100 200 300 400 500 600 700 800 900 1000
Distortion (dBc)
Frequency (KHz)
-100
-90
-80
-70
-60
-50
-40
0.5 0.75 11.25 1.5 1.75 22.25 2.5
Distortion (dBc)
Output Amplitude (V
pp
)
-100
-90
-80
-70
-60
-50
-40
0.5 0.75 11.25 1.5 1.75 22.25 2.5
Distortion (dBc)
Output Amplitude (V
pp
)
-100
-95
-90
-85
-80
-75
-70
-65
100 200 300 400 500 600 700 800 900 1000
THD (dB)
Frequency (kHz)
Data Sheet
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 11
Typical Performance Characteristics - Continued
TA = 25°C, Vs = ±5V, Rf = 1kΩ, RL = 1kΩ to GND, G = 2; unless otherwise noted.
Input Offset Voltage vs. Temperature Input Offset Voltage Distribution
Large Signal Pulse Response Large Signal Pulse Response at VS = 3V
Small Signal Pulse Response Small Signal Pulse Response at VS = 3V
-0.75
-0.5
-0.25
0
0.25
0.5
0.75
00.5 11.5 2
Voltage (V)
T i m e ( n s )
1.35
1.4
1.45
1.5
1.55
1.6
1.65
00.5 11.5 2
Voltage (V)
T i m e ( n s )
-6
-4
-2
0
2
4
6
012345678910
Voltage (V)
T i m e ( n s )
0
0.5
1
1.5
2
2.5
3
00.5 11.5 2
Voltage (V)
T i m e ( n s )
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
-40 -20 020 40 60 80 100 120
Vio (V)
Temperature (°C)
0
1000
2000
3000
4000
5000
-0.98
-0.7
-0.42
-0.14
0.14
0.42
0.7
0.98
Units
Input Offset Vo l tage (mV)
Data Sheet
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 12
Application Information
Basic Operation
Figures 1 and 2 illustrate typical circuit congurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations.
+
-
Rf
0.1μF
6.8μF
Output
G = 1 + (Rf/Rg)
Input
+Vs
-Vs
Rg
0.1μF
6.8μF
RL
Figure 1. Typical Non-Inverting Gain Circuit
Figure 2. Typical Inverting Gain Circuit
Power Dissipation
Power dissipation should not be a factor when operating
under the stated 300 ohm load condition. However, ap-
plications with low impedance, DC coupled loads should
be analyzed to ensure that maximum allowed junction
temperature is not exceeded. Guidelines listed below can
be used to verify that the particular application will not
cause the device to operate beyond it’s intended operat-
ing range.
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction tem-
perature, the package thermal resistance value ThetaJA
(ӨJA) is used along with the total die power dissipation.
TJunction = TAmbient + (ӨJA × PD)
Where TAmbient is the temperature of the working environment.
In order to determine PD, the power dissipated in the load
needs to be subtracted from the total power delivered by
the supplies.
PD = Psupply - Pload
Supply power is calculated by the standard power equa-
tion.
Psupply = Vsupply × IRMS supply
Vsupply = VS+ - VS-
Power delivered to a purely resistive load is:
Pload = ((VLOAD)RMS2)/Rloadeff
The effective load resistor (Rloadeff) will need to include
the effect of the feedback network. For instance,
Rloadeff in gure 3 would be calculated as:
RL || (Rf + Rg)
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purposes
however, prior knowledge of actual signal levels and load
impedance is needed to determine the dissipated power.
Here, PD can be found from
PD = PQuiescent + PDynamic - PLoad
Quiescent power can be derived from the specied IS val-
ues along with known supply voltage, VSupply. Load power
can be calculated as above with the desired signal ampli-
tudes using:
(VLOAD)RMS = VPEAK / √2
( ILOAD)RMS = ( VLOAD)RMS / Rloadeff
The dynamic power is focused primarily within the output
stage driving the load. This value can be calculated as:
PDYNAMIC = (VS+ - VLOAD)RMS × ( ILOAD)RMS
Assuming the load is referenced in the middle of the pow-
er rails or Vsupply/2.
Figure 3 shows the maximum safe power dissipation in
the package vs. the ambient temperature for the pack-
ages available.
+
-
Rf
0.1μF
6.8μF
Output
G = - (Rf/Rg)
For optimum input offset
voltage set R1 = Rf || Rg
Input
+Vs
-Vs
0.1μF
6.8μF
RL
Rg
R1
Data Sheet
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 13
0
0.5
1
1.5
2
2.5
-40 -20 020 40 60 80
Maximum Power Dissipation (W)
Ambient Temperature (°C)
SOT23-6
SOIC-8
Figure 3. Maximum Power Derating
Driving Capacitive Loads
Increased phase delay at the output due to capacitive load-
ing can cause ringing, peaking in the frequency response,
and possible unstable behavior. Use a series resistance,
RS, between the amplier and the load to help improve
stability and settling performance. Refer to Figure 4.
+
-
Rf
Input
Output
Rg
Rs
CLRL
Figure 4. Addition of RS for Driving
Capacitive Loads
The CLC1003 family of ampliers is capable of driving up to
300pF directly, with no series resistance. Directly driving
500pF causes over 4dB of frequency peaking, as shown in
the plot on page 6. Table 1 provides the recommended RS
for various capacitive loads. The recommended RS values
result in <=1dB peaking in the frequency response. The
Frequency Response vs. CL plots, on page 6, illustrates
the response of the CLCx003.
CL (pF) RS (Ω) -3dB BW (MHz)
500 10 27
1000 7.5 20
3000 4 15
Table 1: Recommended RS vs. CL
For a given load capacitance, adjust RS to optimize the
tradeoff between settling time and bandwidth. In general,
reducing RS will increase bandwidth at the expense of ad-
ditional overshoot and ringing.
Overdrive Recovery
An overdrive condition is dened as the point when ei-
ther one of the inputs or the output exceed their specied
voltage range. Overdrive recovery is the time needed for
the amplier to return to its normal or linear operating
point. The recovery time varies, based on whether the
input or output is overdriven and by how much the range
is exceeded. The CLCx003 will typically recover in less
than 20ns from an overdrive condition. Figure 5 shows the
CLC1003 in an overdriven condition.
Figure 5. Overdrive Recovery
Considerations for Offset and Noise Performance
Offset Analysis
There are three sources of offset contribution to consider;
input bias current, input bias current mismatch, and input
offset voltage. The input bias currents are assumed to
be equal with and additional offset current in one of the
inputs to account for mismatch. The bias currents will not
affect the offset as long as the parallel combination of Rf
and Rg matches Rt. Refer to Figure 6.
IN
RgRf
Rt
RL
+Vs
-Vs
–
+
CLC1003
Figure 6: Circuit for Evaluating Offset
-2
-2
-1
-1
0
1
1
2
2
-3
-2
-1
0
1
2
3
00.25 0.5 0.75 11.25 1.5 1.75 2
Output Voltage (V)
Input Voltage (V)
T i m e ( u s )
Output
Input
V
IN
= .8V
pp
G = 5
Data Sheet
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 14
The rst place to start is to determine the source resis-
tance. If it is very small an additional resistance may need
to be added to keep the values of Rf and Rg to practical
levels. For this analysis we assume that Rt is the total re-
sistance present on the non-inverting input. This gives us
one equation that we must solve:
Rt = Rg||Rf
This equation can be rearranged to solve for Rg:
Rg = (Rt * Rf) / (Rf - Rt)
The other consideration is desired gain (G) which is:
G = (1 + Rf/Rg)
By plugging in the value for Rg we get
Rf = G * Rt
And Rg can be written in terms of Rt and G as follows:
Rg = (G * Rt) / (G - 1)
The complete input offset equation is now only dependent
on the voltage offset and input offset terms given by:
VIOS =VIO
( )
2+IOS ∗RT
( )
2
And the output offset is:
VOOS =G∗VIO
( )
2+IOS ∗RT
( )
2
Noise analysis
The complete equivalent noise circuit is shown in Figure 7.
RgRf
RL
–
+
CLC1003
+ – + –
Rg
+ –
+
–
+ –
w
Figure 7: Complete Equivalent Noise Circuit
The complete noise equation is given by:
v2
o=v2
orext +en1+RF
RG
2+ibp ∗RT 1 +RF
RG
2+ibn∗RF
( )
2
Where Vorext is the noise due to the external resistors and
is given by:
=en1+RF
RG
2+eG∗RF
RG
2+e2
F
v2
o
The complete equation can be simplied to:
=3∗4kT ∗G∗RT
( )
+enG
( )
2+2∗in∗RT
( )
2
v2
o
It’s easy to see that the effect of amplier voltage noise
is proportionate to gain and will tend to dominate at large
gains. The other terms will have their greatest impact at
large Rt values at lower gains.
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CADEKA has evaluation
boards to use as a guide for high frequency layout and as
aid in device testing and characterization. Follow the steps
below as a basis for high frequency layout:
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more in-
formation.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board # Products
CEB002 CLC1003 in SOT23-5
CEB003 CLC1003 in SOIC-8
Data Sheet
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplier Rev 1A
©2004-2008 CADEKA Microcircuits LLC www.cadeka.com 15
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in Fig-
ures 8-13. These evaluation boards are built for dual- sup-
ply operation. Follow these steps to use the board in a
single-supply application:
1. Short -Vs to ground.
2. Use C3 and C4, if the -VS pin of the amplier is not
directly connected to the ground plane.
Figure 8. CEB002 Schematic
Figure 9. CEB002 Top View
Figure 10. CEB002 Bottom View
Figure 11. CEB003 Top View
Figure 12. CEB003 Bottom View
For additional information regarding our products, please visit CADEKA at: cadeka.com
CADEKA, the CADEKA logo design, and Comlinear and the Comlinear logo design, are trademarks or registered trademarks of CADEKA
Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved.
CADEKA Headquarters Loveland, Colorado
T: 970.663.5452
T: 877.663.5415 (toll free)
Data Sheet
Comlinear CLC1003 Low Distortion, Low Offset, RRIO Amplier Rev 1A
Amplify the Human Experience
Mechanical Dimensions
SOT23-5 Package
SOIC-8