March 2001 AS7C1024 AS7C31024 (R) 5V/3.3V 128Kx8 CMOS SRAM (Evolutionary Pinout) Features * 2.0V data retention * Easy memory expansion with CE1, CE2, OE inputs * TTL/LVTTL-compatible, three-state I/O * 32-pin JEDEC standard packages * AS7C1024 (5V version) * AS7C31024 (3.3V version) * Industrial and commercial temperatures * Organization: 131,072 words x 8 bits * High speed - - 12/15/20 ns address access time - 6,7,8 ns output enable access time * Low power consumption: ACTIVE 300 mil SOJ 400 mil SOJ 8 x 20mm TSOP I 8 x 13.4 mm sTSOP I * ESD protection 2000 volts * Latch-up current 200 mA - 825 mW (c) / max @ 12 ns - 360 mW (AS7C31024) / max @ 12 ns * Low power consumption: STANDBY - 55 mW (AS7C1024) / max CMOS - 36 mW (AS7C31024) / max CMOS Pin arrangement I/O7 512x256x8 Array (1,048,576) Sense amp Row decoder Input buffer I/O0 Control circuit 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 WE OE CE1 CE2 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 A9 A10 A11 A12 A13 A14 A15 A16 Column decoder A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 AS7C1024 AS7C31024 GND A0 A1 A2 A3 A4 A5 A6 A7 A8 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) 32-pin TSOP I (8 x 20mm) VCC AS7C1024 AS7C31024 Logic block diagram Selection guide Maximum address access time Maximum output enable access time Maximum operating current Maximum CMOS standby current AS7C1024 AS7C31024 AS7C1024 AS7C31024 AS7C1024-12 AS7C31024-12 12 6 140 90 10 10 AS7C1024-15 AS7C31024-15 15 8 125 80 10 10 AS7C1024-20 AS7C31024-20 20 10 110 75 15 15 Unit ns ns mA mA mA mA Shaded areas contain advance information. 3/23/01; v.1.0 Alliance Semiconductor P. 1 of 9 Copyright (c) Alliance Semiconductor. All rights reserved. AS7C1024 AS7C31024 (R) Functional description The AS7C1024 and AS7C31024 are high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 12/15/20 ns with output enable access times (tOE) of 6,7,8 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems. When CE1 is high or CE2 is low the devices enter standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1 or ISB2). For example, the AS7C31024 is guaranteed not to exceed 0.33mW under nominal full standby conditions. All devices in this family will retain data when VCC is reduced as low as 2.0V. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chips drive I/O pins with the data word referenced by the input address. When either chip enable is inactive, output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. Absolute maximum ratings Parameter Symbol Min Max Unit AS7C1024 Vt1 -0.50 +7.0 V AS7C31024 Vt1 -0.50 +5.0 V Voltage on any pin relative to GND Vt2 -0.50 VCC +0.50 V Power dissipation PD - 1.0 W Storage temperature (plastic) Tstg -65 +150 C Ambient temperature with VCC applied Tbias -55 +125 C DC current into outputs (low) IOUT - 20 mA Voltage on VCC relative to GND Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE1 CE2 WE OE Data Mode H X X X High Z Standby (ISB, ISB1) X L X X High Z Standby (ISB, ISB1) L H H H High Z Output disable (ICC) L H H L DOUT Read (ICC) L H L X DIN Write (ICC) Key: X = Don't Care, L = Low, H = High 3/23/01; v.1.0 Alliance Semiconductor P. 2 of 9 AS7C1024 AS7C31024 (R) Recommended operating conditions Parameter Supply voltage Input voltage Device Symbol Min Nominal Max Unit AS7C1024 VCC 4.5 5.0 5.5 V AS7C31024 VCC 3.0 3.3 3.6 V AS7C1024 VIH 2.2 - VCC + 0.5 V AS7C31024 VIH 2.0 - VCC + 0.5 V -0.5 - 0.8 V VIL Ambient operating temperature commercial TA 0 - 70 C industrial TA -40 - 85 C VILmin = -3.0V for pulse width less than tRC/2. DC operating characteristics (over the operating range)1 -12 -15 -20 Unit Parameter Sym Test conditions Device Min Max Min Max Min Max Input leakage current |ILI| VCC = Max, VIN = GND to VCC - 1 - 1 - 1 A Output leakage current |ILO| VCC = Max, CE1 = VIH or CE2 = VIL, VOUT = GND to VCC - 1 - 1 - 1 A Operating power supply current VCC = Max, CE1 = VIL, AS7C1024 CE2 = VIH, f = fMax, IOUT = 0 AS7C31024 mA - 140 - 125 - 110 ICC - 90 - 80 - 75 VCC = Max, CE1 VIH and/or AS7C1024 CE2 VIL, VIN = VIH or VIL, AS7C31024 f = fMax, IOUT = 0mA - 75 - 65 - 60 ISB - 50 - 40 - 35 VCC = Max, CE1 VCC-0.2V VIN GND + 0.2V or VIN VCC -0.2V, f = 0 AS7C1024 - 10 - 10 - 15 ISB1 AS7C31024 - 10 - 10 - 15 VOL IOL = 8 mA, VCC = Min - 0.4 - 0.4 - 0.4 V VOH IOH = -4 mA, VCC = Min 2.4 - 2.4 - 2.4 - V Standby power supply current Output voltage mA mA mA Shaded areas contain advance information. Capacitance (f = 1 MHz, Ta = 25 C, VCC = NOMINAL)2 Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CE1, CE2, WE, OE VIN = 0V 5 pF I/O capacitance CI/O I/O VIN = VOUT = 0V 7 pF 3/23/01; v.1.0 Alliance Semiconductor P. 3 of 9 AS7C1024 AS7C31024 (R) Read cycle (over the operating range)3,9,12 -12 Parameter -15 -20 Symbol Min Max Min Max Min Max Unit Notes Read cycle time tRC 12 - 15 - 20 - ns Address access time tAA - 12 - 15 - 20 ns 3 Chip enable (CE1) access time tACE1 - 12 - 15 - 20 ns 3, 12 Chip enable (CE2) access time tACE2 - 12 - 15 - 20 ns 3, 12 Output enable (OE) access time tOE - 6 - 7 - 8 ns Output hold from address change tOH 3 - 3 - 3 - ns 5 CE1 Low to output in low Z tCLZ1 3 - 3 - 3 - ns 4, 5, 12 CE2 High to output in low Z tCLZ2 3 - 3 - 3 - ns 4, 5, 12 CE1 Low to output in high Z tCHZ1 - 3 - 4 - 5 ns 4, 5, 12 CE2 Low to output in high Z tCHZ2 - 3 - 4 - 5 ns 4, 5, 12 OE Low to output in low Z tOLZ 0 - 0 - 0 - ns 4, 5 OE High to output in high Z tOHZ - 3 - 4 - 5 ns 4, 5 Power up time tPU 0 - 0 - 0 - ns 4, 5, 12 Power down time tPD - 12 - 15 - 20 ns 4, 5, 12 Key to switching waveforms Rising input Falling input Undefined / don't care Read waveform 1 (address controlled)3,6,7,9,12 tRC Address tAA tOH DOUT Data valid Read waveform 2 (CE1, CE2, and OE controlled)3,6,8,9,12 tRC1 CE1 CE2 tOE OE DOUT Current supply 3/23/01; v.1.0 tOHZ tCHZ1, tCHZ2 tOLZ tACE1, tACE2 tCLZ1, tCLZ2 tPU Data valid tPD 50% 50% Alliance Semiconductor ICC ISB P. 4 of 9 AS7C1024 AS7C31024 (R) Write cycle (over the operating range)11, 12 -12 Parameter -15 -20 Symbol Min Max Min Max Min Max Unit Notes Write cycle time tWC 12 - 15 - 20 - ns Chip enable (CE1) to write end tCW1 10 - 12 - 12 - ns 12 Chip enable (CE2) to write end tCW2 10 - 12 - 12 - ns 12 Address setup to write end tAW 10 - 12 - 12 - ns Address setup time tAS 0 - 0 - 0 - ns Write pulse width tWP 8 - 9 - 12 - ns Address hold from end of write tAH 0 - 0 - 0 - ns Data valid to write end tDW 6 - 9 - 10 - ns Data hold time tDH 0 - 0 - 0 - ns 4, 5 Write enable to output in high Z tWZ - 5 - 5 - 5 ns 4, 5 Output active from write end tOW 3 - 3 - 3 - ns 4, 5 12 Shaded areas contain advance information. Write waveform 1 ( WE controlled)10,11,12 tWC tAW tAH Address tWP WE tAS tDW DIN tDH Data valid tWZ tOW DOUT Write waveform 2 (CE1 and CE2 controlled)10,11,12 tAW tWC tAH Address tAS tCW1, tCW2 CE1 CE2 tWP WE tWZ DIN tDW tDH Data valid DOUT 3/23/01; v.1.0 Alliance Semiconductor P. 5 of 9 AS7C1024 AS7C31024 (R) Data retention characteristics (over the operating range)13 Parameter Symbol VCC for data retention VDR Data retention current ICCDR Chip deselect to data retention time tCDR Operation recovery time Test conditions VCC = 2.0V CE1 VCC-0.2V or CE2 0.2V VIN VCC-0.2V or VIN 0.2V tR Input leakage current Device Min Max Unit 2.0 - V AS7C1024 - 5 mA AS7C31024 - 1 mA 0 - ns tRC - ns - 1 A | ILI | Data retention waveform Data retention mode VCC VDR 2.0V VCC VCC tCDR tR VDR VIH CE1 VIH AC test conditions - - - - 5V output load: see Figure B or Figure C. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. Thevenin equivalent: 168W DOUT +1.728V (5V and 3.3V) +5V +3.3V 480W +3.0V GND 90% 10% 90% 2 ns Figure A: Input pulse 10% DOUT 255W C(14) GND Figure B: 5V Output load 320W DOUT 255W C(14) GND Figure C: 3.3V Output load Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification. This parameter is sampled and not 100% tested. For test conditions, see AC Test Conditions, Figures A, B, and C. tCLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured 500mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is High for read cycle. CE1 and OE are Low and CE2 is High for read cycle. Address valid prior to or coincident with CE1 transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. CE1 or WE must be High or CE2 Low during address transitions. Either CE1 or WE asserting high terminates a write cycle. All write cycle timings are referenced from the last valid address to the first transitioning address. CE1 and CE2 have identical timing. 2V data retention applies to commercial temperature operating range only. C=30pF, except all high Z and low Z parameters, C=5pF. 3/23/01; v.1.0 Alliance Semiconductor P. 6 of 9 AS7C1024 AS7C31024 (R) Typical DC and AC characteristics 1.4 1.0 0.8 0.6 ISB 0.4 0.2 0.6 ISB 0.4 0.0 -55 MAX 1.4 625 5 1 0.2 0.04 -10 35 80 125 Ambient temperature (C) -55 Normalized access time tAA vs. ambient temperature Ta 1.5 Normalized access time Ta = 25 C 1.2 1.1 1.0 0.9 VCC = VCC(NOMINAL) 1.2 1.1 1.0 0.9 0.8 MIN NOMINAL Supply voltage (V) Output source current IOH vs. output voltage VOH 120 VCC = VCC(NOMINAL) 100 Ta = 25 C 80 60 40 20 0 VCC Output voltage (V) 3/23/01; v.1.0 0.6 0.4 0.0 0 30 Ta = 25 C 100 100 35 VCC = VCC(NOMINAL) 120 25 50 75 Cycle frequency (MHz) Typical access time change tAA vs. output capacitive loading 80 60 40 20 VCC = VCC(NOMINAL) 25 20 15 10 5 0 0 0.8 -10 35 80 125 Ambient temperature (C) Output sink current IOL vs. output voltage VOL 140 Output sink current (mA) 140 Ta = 25 C 1.0 0.2 0.8 -55 MAX 125 VCC = VCC(NOMINAL) 1.2 1.3 -10 35 80 Ambient temperature (C) Normalized supply current ICC vs. cycle frequency 1/tRC, 1/tWC 1.4 1.4 1.3 VCC = VCC(NOMINAL) 25 Normalized ICC NOMINAL Supply voltage (V) Normalized access time tAA vs. supply voltage VCC 1.5 Normalized access time 0.8 0.2 0.0 MIN Output source current (mA) ICC 1.0 Normalized supply current ISB1 vs. ambient temperature Ta Normalized ISB1 (log scale) 1.2 ICC Normalized ICC, ISB Normalized ICC, ISB 1.2 Normalized supply current ICC, ISB vs. ambient temperature Ta Change in tAA (ns) 1.4 Normalized supply current ICC, ISB vs. supply voltage VCC 0 0 VCC Output voltage (V) Alliance Semiconductor 0 250 500 750 Capacitance (pF) 1000 P. 7 of 9 AS7C1024 AS7C31024 (R) Package dimensions A D B S E1 E A A1 B b c D E E1 e eA L a S L e A1 b Seating Plane Pin 1 c eA D B e A E1 E2 A1 Seating Plane b Pin 1 A A1 A2 B b c D E E1 E2 e c A2 E b e D Hd 32-pin SOJ 300 mil 32-pin SOJ 400 mil Min Max Min Max 0.145 0.145 0.025 0.025 0.086 0.105 0.086 0.115 0.026 0.032 0.026 0.032 0.014 0.020 0.015 0.020 0.006 0.013 0.007 0.013 0.820 0.830 0.820 0.830 0.250 0.275 0.360 0.380 0.292 0.305 0.395 0.405 0.330 0.340 0.435 0.445 0.050 BSC 0.050 BSC c A2 L E pin 1 pin 32 pin 16 pin 17 A A1 A A1 A2 b c D e E Hd L 3/23/01; v.1.0 32-pin PDIP Min Max 0.180 0.015 0.045 0.055 0.015 0.021 0.008 0.012 1.571 0.300 0.325 0.280 0.295 0.100 BSC 0.330 0.370 0.110 0.142 0 15 0.043 Alliance Semiconductor 32-pin TSOP 8x20 Min Max - 1.20 0.05 0.15 0.95 1.05 0.17 0.27 0.10 0.21 18.20 18.60 0.50 nominal 7.80 8.20 19.80 20.20 0.50 0.70 0 5 P. 8 of 9 AS7C1024 AS7C31024 (R) Ordering codes Volt/Temp 12 ns 15 ns 20 ns 5V commercial AS7C1024-12TJC AS7C1024-15TJC AS7C1024-20TJC 5V industrial AS7C1024-12TJI AS7C1024-15TJI AS7C1024-20TJI 3.3V commercial AS7C31024-12TJC AS7C31024-15TJC AS7C31024-20TJC 3.3V industrial AS7C31024-12TJI AS7C31024-15TJI AS7C31024-20TJI 5V commercial AS7C1024-12JC AS7C1024-15JC AS7C1024-20JC 5V industrial AS7C1024-12JI AS7C1024-15JI AS7C1024-20JI 3.3V commercial AS7C31024-12JC AS7C31024-15JC AS7C31024-20JC 3.3V industrial AS7C31024-12JI AS7C31024-15JI AS7C31024-20JI 5V commercial AS7C1024-12TC AS7C1024-15TC AS7C1024-20TC 5V industrial AS7C1024-12TI AS7C1024-15TI AS7C1024-20TI 3.3V commercial AS7C31024-12TC AS7C31024-15TC AS7C31024-20TC 3.3V industrial AS7C31024-12TI AS7C31024-15TI AS7C31024-20TI Package \ Access time Plastic SOJ, 300 mL Plastic SOJ, 400 mL TSOP 8x20 NA: not available Shaded areas contain advance information. Part numbering system AS7C X 1024 -XX X X SRAM prefix Blank=5V CMOS 3=3.3V CMOS Device number Access time Package: TP=PDIP 300 mil T=TSOP 8x20 J=SOJ 400 mil TJ=SOJ 300 mil Temperature range C = Commercial, 0C to 70C I = Industrial, -40C to 85C 3/23/01; v.1.0 Alliance Semiconductor P. 9 of 9 (c) Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. 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