To our custo mers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
Corporation, and Renesas Electronics Corpor ation took over all the business of both
companies. Therefore, althoug h the old com pany name remains in this docum ent, it is a valid
Renesas Electronics document. W e appreciate your understanding.
Renesas Electronics website: http://www.renesas.com
April 1st, 2010
Renesas Electronics Corporation
Issued by: Renesas Electronics Corporation (http://www.renesas.com)
Send any inquiries to http://www.renesas.com/inquiry.
Notice
1. All information included in this document is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please
confirm the latest product information with a Renesas Electronics sales office. Also, please pay regular and careful attention to
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(Note 2) “Renesas Electronics product(s)” means any product developed or manufactured by or for Renesas Electronics.
REJ03C0107-0200 Rev.2.00,
Dec.12.2008, page 1 of 15
R1RW0416D Series
4M High Speed SRAM (256-kword × 16-bit)
REJ03C0107-0200
Rev. 2.00
Dec.12.2008
Description
The R1RW0416D is a 4-Mbit high speed static RAM organized 256-kword × 16-bit. It has realized high
speed access time by employing CMOS process (6-transistor memory cell) and high speed circuit
designing technology. It is most appropriate for the application which requires high speed, high density
memory and wide bit width configuration, such as cache and buffer memory in system. Especially, L-
Version and S-Version ar e low power consumption an d it is the b est for th e battery backup system. The
package prepares 400-mil 44-pin SOJ and 400-mil 44-pin plastic TSOPII for high density surface
mounting.
Features
• Single 3.3 V supply: 3.3 V ± 0.3 V
• Access time: 10 ns / 12 ns (max)
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Directly TTL compatible
All inputs and outputs
• Operating current: 145 / 130mA (max)
• TTL standby current: 40 mA (max)
• CMOS standby current : 5 mA (max)
: 0.8 mA (max) (L-version)
: 0.5 mA (max) (S -v ersion)
• Data retention current : 0.4 mA (max) (L-version)
:0.2 mA (max) (S-version)
• Data retention voltage: 2.0 V (min) (L-version , S-version)
• Center VCC and VSS type pin out
R1RW0416D S er i e s
REJ03C0107-0200 Rev.2.00,
Dec.12.2008, page 2 of 15
Ordering Information
Type No. Access time Package
R1RW0416DGE-0PR 10 ns
R1RW0416DGE-2PR 12 ns 400-mil 44-pin plastic SOJ (44P0K)
R1RW0416DGE-2LR 12 ns
R1RW0416DGE-2SR 12 ns
R1RW0416DSB-0PR 10 ns
R1RW0416DSB-2PR 12 ns 400-mil 44-pin plastic TSOPII (44P3W-H)
R1RW0416DSB-2LR 12 ns
R1RW0416DSB-2SR 12 ns
Pin Arrangement
A0
A1
A2
A3
A4
CS#
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE#
A5
A6
A7
A8
A9
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A17
A16
A15
OE#
UB#
LB#
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
44-pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A0
A1
A2
A3
A4
CS#
I/O1
I/O2
I/O3
I/O4
VCC
VSS
I/O5
I/O6
I/O7
I/O8
WE#
A5
A6
A7
A8
A9
A17
A16
A15
OE#
UB#
LB#
I/O16
I/O15
I/O14
I/O13
VSS
VCC
I/O12
I/O11
I/O10
I/O9
NC
A14
A13
A12
A11
A10
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
44-pin TSOP
(Top View)
R1RW0416D S er i e s
REJ03C0107-0200 Rev.2.00,
Dec.12.2008, page 3 of 15
Pin Description
Pin name Function
A0 to A17 Address input
I/O1 to I/O16 Data input/output
CS# Chip select
OE# Output enable
WE# Write enable
UB# Upper byte select
LB# Lower byte select
VCC Power supply
VSS Ground
NC No connection
R1RW0416D S er i e s
REJ03C0107-0200 Rev.2.00,
Dec.12.2008, page 4 of 15
Block Diagram
Memory matrix
1024 rows × 32 columns ×
8 blocks × 16 bit
(4,194,304 bits)
CS
VCC
VSS
A8 A9 A17 A15 A16 A0 A2 A4
Column I/O
Column decoder
I/O1
WE#
Input
data
control
Row
decoder
OE#
CS#
CS
CS
LB#
UB#
I/O16
I/O9
I/O8
.
.
.
.
.
.
A14
A13
A12
A5
A6
A7
A11
A10
A3
A1
(LSB)
(LSB)
(MSB)
(MSB)
R1RW0416D S er i e s
REJ03C0107-0200 Rev.2.00,
Dec.12.2008, page 5 of 15
Operation Table
CS# OE# WE# LB# UB# Mode VCC current I /O 1−I/O8 I/O9−I/O16 Ref. cycle
H × × × × Standby ISB, ISB1 High-Z High-Z
L H H × × Output disable ICC High-Z High-Z
L L H L L Read ICC Output Output Read cycle
L L H L H Lower byte read ICC Output High-Z Read cycle
L L H H L Upper byte read ICC High-Z Output Read cycle
L L H H H I
CC High-Z High-Z
L × L L L Write ICC Input Input Write cycle
L × L L H Lower byte write ICC Input High-Z Write cycle
L × L H L Upper byte write ICC High-Z Input Write cycle
L × L H H I
CC High-Z High-Z
Note: H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter Symbol Value Unit
Supply voltage relative to VSS V
CC −0.5 to +4.6 V
Voltage on any pin relative to VSS V
T −0.5*1 to VCC + 0.5*2 V
Power dissipation PT 1.0 W
Operating temperature Topr 0 to +70 °C
Storage temperature Tstg −55 to +125 °C
Storage temperature under bias Tbias −10 to +85 °C
Notes: 1. VT (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns.
2. VT (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns.
R1RW0416D S er i e s
REJ03C0107-0200 Rev.2.00,
Dec.12.2008, page 6 of 15
Recommended DC Operating Conditions
(Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit
Supply voltage VCC*3 3.0 3.3 3.6 V
V
SS*4 0 0 0 V
Input voltage VIH 2.0 V
CC + 0.5*2 V
V
IL −0.5*1 0.8 V
Notes: 1. VIL (min) = −2.0 V for pulse width (under shoot) ≤ 6 ns.
2. VIH (max) = VCC + 2.0 V for pulse width (over shoot) ≤ 6 ns.
3. The supply voltage w i th al l VCC pins must be on the same level.
4. The supply voltage w i th al l VSS pins must be on the same level.
R1RW0416D S er i e s
REJ03C0107-0200 Rev.2.00,
Dec.12.2008, page 7 of 15
DC Char ac ter istics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, VSS = 0 V)
Parameter Symbol Min Max Unit Test conditions
Input leakage current |ILI| 2 µA VIN = VSS to VCC
Output leakage current |ILO| 2 µA VIN = VSS to VCC
Operating power supply
current 10 ns cycle ICC 145 mA Min cycle
CS# = VIL, IOUT = 0 mA
Other inputs = VIH/VIL
12 ns cycle ICC 130 mA
Standby power supply current ISB 40 mA Min cycle, CS# = VIH,
Other inputs = VIH/VIL
I
SB1 5 mA f = 0 MHz
VCC ≥ CS# ≥ VCC − 0.2 V,
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2
V
*1 0.8*1 mA
*2 0.5*2 mA
Output voltage VOL 0.4 V IOL = 8 mA
V
OH 2.4
V IOH = −4 mA
Note: 1. This characteristics is guaranteed only for L-version.
2. This characteristics is guaranteed only for S-version.
Capacitance
(Ta = +25°C, f = 1.0 MHz)
Parameter Symbol Min Max Unit Test conditions
Input capacitance*1 C
IN 6 pF VIN = 0 V
Input/output capacitance*1 C
I/O 8 pF VI/O = 0 V
Note: 1. This parameter is sampled and not 100% tested.
R1RW0416D S er i e s
REJ03C0107-0200 Rev.2.00,
Dec.12.2008, page 8 of 15
AC Char ac ter istics
(Ta = 0 to +70°C, VCC = 3.3 V ± 0.3 V, unless otherwise noted.)
Test Conditions
• Input pulse levels: 3.0 V/0.0 V
• Input rise and fall time: 3 ns
• Input and output timing reference levels: 1.5 V
• Output load: See figures (Including scope and jig)
Output load (B)
(for t
CLZ
, t
OLZ
, t
BLZ
, t
CHZ
, t
OHZ
,
t
BHZ
, t
WHZ
, and t
OW
)
D
OUT
353 Ω
319 Ω
3.3 V
5 pF
1.5 V
30 pF
D
OUT
RL = 50 Ω
Output load (A)
Zo = 50 Ω
Read Cycle
R1RW0416D
10ns Version 12ns Version
Parameter Symbol Min Max Min Max Unit Notes
Read cycle time tRC 10
12
ns
Address access time tAA 10 12 ns
Chip select access time tACS 10 12 ns
Output enable to output valid tOE 5 6 ns
Byte select to output valid tBA 5 6 ns
Output hold from address change tOH 3 3 ns
Chip select to output in low-Z tCLZ 3 3 ns 1
Output enable to output in low-Z tOLZ 0 0 ns 1
Byte select to output in low-Z tBLZ 0 0 ns 1
Chip deselect to output in high-Z tCHZ 5 6 ns 1
Output disable to output in high-Z tOHZ 5 6 ns 1
Byte deselect to output in high-Z tBHZ 5 6 ns 1
R1RW0416D S er i e s
REJ03C0107-0200 Rev.2.00,
Dec.12.2008, page 9 of 15
Write Cycle
R1RW0416D
10ns Version 12ns Version
Parameter Symbol Min Max Min Max Unit Notes
Write cycle time t WC 10 12 ns
Address valid to end of write tAW 7 8 ns
Chip select to end of write tCW 7 8 ns 8
Write pulse width tWP 7 8 ns 7
Byte select to end of wr ite tBW 7 8 ns
Address setu p time tAS 0
0 ns 5
Write recovery time tWR 0
0 ns 6
Data to write time overlap tDW 5
6 ns
Data hold from write time tDH 0
0 ns
Write disable to output in low-Z tOW 3 3 ns 1
Output disable to output in high-Z tOHZ 5 6 ns 1
Write enable to output in high-Z tWHZ 5 6 ns 1
Notes: 1. Transition is measured ±200 mV from steady voltage with output load (B). This parameter is
sampled and not 100% tested.
2. If the CS# or LB# or UB# low transition occurs simultaneously with the WE# low transition or after
the WE# transition, output remains a high impedance state.
3. WE# and/or CS# must be high during address transition time.
4. If CS#, OE#, LB# and UB# are low during this period, I/O pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
5. tAS is measured from the latest address transition to the latest of CS#, WE#, LB# or UB# going
low.
6. tWR is measured from the earliest of CS#, WE#, LB# or UB# going high to the first address
transition.
7. A write occurs during the overlap of a low CS#, a low WE# and a low LB# or a low UB# (tWP). A
write begins at the latest transition among CS# going low, WE# going low and LB# going low or
UB# going low. A write ends at the earliest transition among CS# going high, WE# going high
and LB# going high or UB# going high.
8. tCW is measured from the later of CS# going low to the end of write.
R1RW0416D S er i e s
REJ03C0107-0200 Rev.2.00,
Dec.12.2008, page 10 of 15
Timing Waveforms
Read Timing Wavefo rm (1) (WE# = VIH)
t
AA
t
ACS
t
OE
t
BA
t
BLZ
t
OLZ
t
CLZ
t
OH
t
CHZ
t
OHZ
t
BHZ
t
RC
Address Valid address
Valid data
D
OUT
CS#
OE#
LB#, UB#
High impedance
*
1
*
1
*
1
*
1
*
1
*
1
*
4
*
4
R1RW0416D S er i e s
REJ03C0107-0200 Rev.2.00,
Dec.12.2008, page 11 of 15
Read Timing Wavefo rm (2) (WE# = VIH, LB# = VIL, UB# = VIL)
t
AA
t
ACS
t
RC
t
OE
t
CLZ
Valid data
Address
CS#
D
OUT
Valid address
High impedance
t
OHZ
OE#
t
OH
t
CHZ
t
OLZ
*
1
*
1
*
1
*
1
*
4
*
4
R1RW0416D S er i e s
REJ03C0107-0200 Rev.2.00,
Dec.12.2008, page 12 of 15
Write Timing Waveform (1) (WE# Controlled)
Address
WE#*
3
t
WC
t
AW
t
AS
t
WR
t
WP
t
WHZ
t
OLZ
t
OW
t
OHZ
t
CW
t
BW
t
DH
t
DW
Valid address
Valid data
CS#*
3
OE#
LB#, UB#
D
OUT
D
IN
High impedance
*
2
R1RW0416D S er i e s
REJ03C0107-0200 Rev.2.00,
Dec.12.2008, page 13 of 15
Write Timing Waveform (2) (CS# Controlled)
Address
CS# *
3
t
WC
t
AW
t
AS
t
WR
t
WP
t
WHZ
t
OLZ
t
OW
t
OHZ
t
CW
t
BW
t
DH
t
DW
Valid address
Valid data
WE#
*
3
OE#
LB#, UB#
D
OUT
D
IN
High impedance
*
2
*
4
R1RW0416D S er i e s
REJ03C0107-0200 Rev.2.00,
Dec.12.2008, page 14 of 15
Write Timing Waveform (3) (LB#, UB# Controlled, OE# = VIH)
Address
D
IN
-UB
(D
IN
-LB)
D
IN
-LB
(D
IN
-UB)
D
OUT
High impedance
Valid address
t
DW
t
DH
t
CW
t
AS
t
BW
t
WP
t
WC
t
WR
t
AW
WE#*
3
CS#*
3
UB# (LB#)
LB# (UB#)
t
BW
Valid data
t
DW
t
DH
Valid data
R1RW0416D S er i e s
REJ03C0107-0200 Rev.2.00,
Dec.12.2008, page 15 of 15
Low VCC Data Retention Characteristics
(Ta = 0 to +70°C)
This characteristics is guaranteed on ly for L-version and S- version.
Parameter Symbol Min Max Unit Test conditions
VCC for data retention VDR 2.0 V VCC ≥ CS# ≥ VCC − 0.2 V,
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
L-Version 400 Data retention current
S-Version
ICCDR
200
µA VCC = 3 V
VCC ≥ CS# ≥ VCC − 0.2 V,
(1) 0 V ≤ VIN ≤ 0.2 V or
(2) VCC ≥ VIN ≥ VCC − 0.2 V
Chip deselect to data retention time tCDR 0 ns See retention waveform
Operation recovery time tR 5 ms
Low VCC Data Rete ntion Timing Waveform
CC
V
3.0 V
0 V
CS#
t
CDR
t
R
V
CC
≥ CS# ≥ V
CC
– 0.2 V
2.0 V
DR
V
Data retention mode
Revision History R1RW0416D Series Data Sheet
Contents of Modification Rev. Date
Page Description
0.01 Sep. 30, 2003 Initial issue
1.00 Mar.12.2004 Deletion of Preliminary
2.00 Dec.12.2008
P2
P2
P7
P8/P9
P15
Addition of access grade 10ns version and S-version.
The product lineup :R1RW0416DSB-0PR/DGE-0PR is added.
The product lineup :R1RW0416DSB-2SR/DGE-2SR is added.
Operating power supply current of 10ns cycle version is described to the
DC characteristic.
ISB1 of S-Version is described to the DC characteristic.
The timing standard of 10ns version is described at the read cycle
The timing standard of 10ns version is described at the write cycle
ICCDR of S-version is described to the low Vcc data retention characteristic.
Notes:
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes
warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property
rights or any other rights of Renesas or any third party with respect to the information in this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including,
but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass
destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws
and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this
document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document,
please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be
disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a
result of errors or omissions in the information included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability
of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular
application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications
or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality
and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or
undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall
have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing
applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range,
movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages
arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain
rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage
caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and
malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software
alone is very difficult, please evaluate the safety of the final products or system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as
swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products.
Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have
any other inquiries.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2377-3473
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jln Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
RENESAS SALES OFFICES
© 2008. Renesas Technology Corp., All rights reserved. Printed in Japan.
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