®
Altera Corporation 265
FLASHlogic
Programmable Logic
Device Family
June 1996, ver. 2 Data Sheet
A-DS-FLSH-02
Features...
■
High-performance programmable logic device (PLD) family
– SRAM-based logic with shadow FLASH memory elements
fabricated on advanced CMOS technology
– Logic densities from 1,600 to 3,200 usable gates (see Table 1)
– Combinatorial speeds with
t
PD
as low as 10 ns
– Counter frequencies of up to 80 MHz
■
8 to 16 logic array blocks (LABs) linked by a 100
%
-connectable
programmable interconnect array (PIA) for improved fitting of
complex designs
■
24V10 macrocell features available
– Dual feedback on all I/O pins
– Product-term allocation matrix supporting up to 16 product
terms per macrocell
– Programmable registers providing D, T, SR, and JK flipflop
functionality with clear, preset, and clock controls
– Fast 12-bit identity compare option
■
Fully compliant with
PCI Local Bus Specification
, version 2.1
Table 1. FLASHlogic Device Features
Feature EPX880 EPX8160
Usable gates 1,600 3,200
Maximum SRAM bits 10,240 20,480
Macrocells 80 160
Logic array blocks (LABs) 8 16
Package options
(maximum user I/O pins) 84-pin PLCC (62)
132-pin PQFP (104) 208-pin PQFP (172)
t
PD
(ns) 10 10
t
CO
(ns) 6 6
f
CNT
(MHz) 80 80
266 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
... and More
Features
■
LABs can be configured as either one of the following:
– 24V10 logic block with 10 macrocells
– 128
×
10 SRAM block
■
3.3-V or 5.0-V I/O on all devices (selectable in each LAB)
■
Low power consumption (1 mA/MHz in standby mode;
1.5 to 2.5 mA/MHz in active mode)
■
84 to 208 pins available in plastic J-lead (PLCC) and plastic quad flat
pack (PQFP) packages (see Table 1)
■
Open-drain output option
■
Joint Test Action Group (JTAG) IEEE 1149.1-compatible test port
– Boundary-scan testing (BST) support
– In-circuit reconfigurability (ICR) support
– In-system programmability (ISP) support
■
Programmable security bit for protection of proprietary designs
■
Supported by industry-standard design and programming tools
from Altera and other vendors
General
Description
FLASHlogic devices are SRAM-based devices with shadow FLASH
memory elements. Fabricated on advanced CMOS technology,
FLASHlogic devices provide from 1,600 to 3,200 usable gates, pin-to-pin
delays as fast as 10 ns, and counter speeds of up to 80 MHz. Table 2 shows
the available speed grades for FLASHlogic devices.
FLASHlogic devices have a unique combination of features that is ideal
for a variety of applications, including communications and bus interface
controllers. They provide low power consumption and user-selectable
5.0-V and 3.3-V outputs, making FLASHlogic devices useful for mixed-
voltage applications such as portable and embedded systems.
The FLASHlogic device architecture supports 100
%
TTL emulation and
high-density integration of SSI, MSI, and LSI logic functions. In addition,
FLASHlogic devices easily integrate multiple programmable logic
devices ranging from PALs, GALs, and 22V10s to MACH, pLSI, and
FPGA devices. With speed, density, and I/O resources comparable to
commonly used masked gate arrays, FLASHlogic devices are ideal for
gate array prototyping and PC applications. In addition, FLASHlogic
devices in the -10 speed grade are PCI-compliant.
Table 2. FLASHlogic Speed Grades
Device Available Speed Grades
-10 -12
EPX880
VV
EPX8160
VV
Altera Corporation 267
FLASHlogic Programmable Logic Device Family Data Sheet
FLASHlogic devices are available in plastic J-lead chip carrier (PLCC) and
plastic quad flat pack (PQFP) packages.
FLASHlogic devices contain 8 to 16 LABs linked by a PIA. Each LAB can
be defined as either a 24V10 logic block of 10 macrocells or a 128
×
10
SRAM block. When defined as a 24V10 logic block, all 10 macrocells have
a programmable-
AND
/allocatable-
OR
array and a configurable register
with independently programmable clock, clear, and preset functions. To
build complex logic functions, product-term allocation allows up to 16
product terms for a single macrocell.
FLASHlogic devices provide dedicated pins compliant with the JTAG
IEEE 1149.1-1990 specification. The JTAG pins support BST, ICR, and ISP.
ICR and ISP offer the designer greater flexibility in prototyping new
designs. These features make FLASHlogic devices ideal for applications
in which the final configuration is not fixed.
FLASHlogic devices are supported by industry-standard PC- and
workstation-based EDA tools, including the Altera PLDshell Plus
development system. The MAX+PLUS II development software also
provides programming and configuration support for FLASHlogic
devices.
Functional
Description
The FLASHlogic device architecture includes the following elements:
■
Logic array blocks (LABs)
– 24V10 configuration
– SRAM configuration
■
Programmable interconnect array (PIA)
■
I/O control blocks
Figure 1 shows the block diagram of the FLASHlogic device architecture,
which consists of LABs linked by a 100
%
-connectable PIA.
268 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
Figure 1. FLASHlogic Device Block DIagram
Logic Array Blocks
The FLASHlogic device architecture is based on the linking of high-
performance, flexible logic array modules called logic array blocks
(LABs). Each LAB can be configured as a 24V10 logic block or as a 128
×
10
SRAM block. The LABs are linked via the PIA, which is fed by all
dedicated inputs, I/O pins, and either macrocells (in 24V10 configuration)
or SRAM outputs (in SRAM configuration). Each LAB is fed by 24 signals
from the PIA and 2 global clocks.
24V10 Configuration
When a LAB is configured as a 24V10 logic block, each block contains the
following elements:
■
10 macrocells
■
A 12-bit identity comparator
■
2 global clocks
■
Control logic for array clocks, and for clear, preset and output enable
signals
10
24
5 to 10
5 to 10
10
24
5 to 10
10
5 to 10
10
24
LAB 0
Macrocells
0 to 9
LAB 1
LAB 2 LAB 3
Dedicated
Inputs
Clock
5 to 10
0 to 48
5 to 10
5 to 10 5 to 10
2 to 4
Macrocells
20 to 29
Macrocells
10 to 19
2
22
2
5 to 10
I/O pins
2 Output
Enables
5 to 10
I/O pins
2 Output
Enables
2 Output
Enables
5 to 10
I/O pins
2 Output
Enables
5 to 10
I/O pins
Macrocells
30 to 39
22
PIA
24
I/O
Control
Block
I/O
Control
Block
I/O
Control
Block
I/O
Control
Block
Altera Corporation 269
FLASHlogic Programmable Logic Device Family Data Sheet
Figure 2 shows a diagram of a LAB configured as a 24V10 logic block.
Figure 2. LAB in 24V10 Configuration
Macrocell 0
to I/O Control
Block
C/P1
C/P2
ACLK1
ACLK2
OE1
OE2 to I/O Control
Block
to PIA
to I/O Control
Block
Global Clock 1
Global Clock 2
From PIA
Delay
Delay
24 24
24
Global
Clock
Select
LAB
Identity
Comparator
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
Macrocell 8
Macrocell 9
Global
Clock
Select
270 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
Macrocells
Each FLASHlogic macrocell can be individually configured for either
sequential or combinatorial logic operation. The macrocell consists of
three functional blocks: the logic array, the product-term allocation
circuit, and the programmable register. See Figure 3.
Figure 3. FLASHlogic Device Macrocell
Combinatorial logic is implemented in the logic array, which provides 2
sets of 2 product terms per macrocell. Macrocells 0 and 9 each have 14
product terms, and macrocells 2 through 8 each have 4 product terms.
Each macrocell can borrow product terms from adjacent macrocells to
increase the total number of product terms per macrocell up to a
maximum of 8. The macrocells located at the ends of each LAB have
additional product terms and support up to 16 product-term equations.
The performance of each macrocell is uniform regardless of whether 2 or
16 product terms are used. Figure 4 shows the flexible product-term
allocation circuit.
In registered functions, each macrocell flipflop can be individually
programmed to implement D, T, JK, or SR operation with programmable
clock, preset, and clear controls. If necessary, the register can be bypassed
for combinatorial operation.
Product-
Term
Allocation
Circuit
LAB Clear/
Preset LAB
Clocks
4
PRN
CLRN
D/T Q
Register
Bypass
to I/O
Control
Block
Invert
Select
to PIA
2
Feedback
Select
to & from
Previous
Macrocell
from
Identity
Comparator
(A = B)
to & from
Next
Macrocell
24 PIA
Signals
Logic Array
Altera Corporation 271
FLASHlogic Programmable Logic Device Family Data Sheet
Figure 4. LAB Product-Term Allocation
Each LAB supports four clock signals—two global clocks and two array
clock signals. The EPX8160 has 4 global clock pins:
CLK1
and
CLK2
are for
LABs 0 through 7, and
CLK3
and
CLK4
are for LABs 8 through 15. Global
clocking is provided by either of two global clock signals or two delayed
global clock signals. Array clocking is provided by two LAB product
terms. Each register in the LAB can be clocked by the true or the
complement of any two of the four clock signals.
Macrocell 0
Product-Term Logic
Macrocell 1
Product-Term Logic
Macrocell 8
Product-Term Logic
Macrocell 9
Product-Term Logic
a = b
a = b
a = b
a = b
a = b
a = b
2
2
2
2
2
12
12
2
272 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
Each programmable register can be clocked in three different modes:
■
Global mode, by either of two global clock signals. This mode
achieves the fastest clock-to-output performance.
■
Delayed global mode, by either of two global clock signals with an
added local delay (within the LAB).
■
Array mode, by either of two array clocks implemented with a
product term. In this mode, the register can be clocked by signals
from buried macrocells.
These clocking modes give FLASHlogic devices increased timing
flexibility, enabling the designer to vary the setup, hold, and clock-to-
output times of each register. See Table 3. These clocking modes are
particularly useful for integrating devices with short-setup-time
microprocessors, such as a Pentium microprocessor.
Each register also supports array preset and clear functions. These
functions are driven by product terms and can be inverted. See Figure 2
on page 269 for a diagram of this logic.
Table 3. EPX880-10 & EPX8160-10 Sample Clocking Modes
Clock Mode Setup Time Hold Time Clock-to-Output Time Unit
Global 6.5 0 6 ns
Delayed global 5 2 8 ns
Array 2 5 12 ns
Altera Corporation 273
FLASHlogic Programmable Logic Device Family Data Sheet
Comparator Circuit
Each LAB also provides a comparator circuit that compares up to 12 pairs
of inputs within the
t
PD
of the device. The product-term allocation matrix
allows any one of the 10 macrocells in the LAB to use the output of the
comparator circuit. See Figure 5.
Figure 5. 12-Bit Identity Compare Logic
The an and bn signals represent a fan-in pair. The /en signal represents an architecture
control bit.
inv
b4
a4
/e4
b5
a5
/e5
b6
a6
/e6
b7
a7
/e7
b8
a8
/e8
b9
a9
/e9
b10
a10
b11
a11
b0
a0
/e0
b1
a1
/e1
b2
a2
/e2
b3
a3
/e3
/e11
/e10
a = b
274 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
SRAM Configuration
Each FLASHlogic LAB can be configured as a 128
×
10 (128 words by
10 bits) SRAM block, as shown in Figure 6. The SRAM block can be
defined with either a bidirectional I/O data bus or with separate input and
output data buses.
Figure 6. LAB in SRAM Configuration
do[9..0]
128 × 10
SRAM Array
a[6..0]
di[9..0]
/BE
/OE
/Block
Write
/Block
Output
Enable
/WE
This inverted (active-high) option
is available only with the EPX8160.
10 10 10
10
Global
Clock
Select
Global Clock 1
Global Clock 2
Delay
Delay
10
PIA
DQ
CLK
LAB
Altera Corporation 275
FLASHlogic Programmable Logic Device Family Data Sheet
The SRAM is accessed using a subset of the 24-signal fan-in from the PIA:
7 bits are for address information; 10 bits are for input data; 3 bits are for
block enable (
/BE
), write enable (
/WE
), and output enable (
/OE
) controls,
as shown in Table 4.
During power-up, the SRAM memory elements are initialized by on-chip,
nonvolatile configuration cells. During operation, the SRAM contains a
copy of the information contained in the nonvolatile configuration
FLASH cells unless other data is written to these SRAM blocks. Therefore,
the SRAM block can emulate read-only memory (ROM).
When an LAB is configured as SRAM, all product terms are used as
SRAM blocks and cannot be used for regular macrocell logic. Multiple
LABs can be cascaded to create larger SRAM blocks to increase the width
or depth of the memory.
Programmable Interconnect Array
Signals are routed between LABs by the 100
%
-connectable programmable
interconnect array (PIA). This global bus connects any signal source to
any destination on the device. All dedicated pins, I/O pins, and macrocell
outputs feed into the PIA and are accessible to all LABs. The high degree
of connectivity and efficient resource management between LABs
minimizes routing problems during design debugging.
The routing delays of channel-based routing schemes in masked or field-
programmable gate arrays (FPGAs) are cumulative, variable, and path-
dependent. In contrast, the FLASHlogic PIA has a fixed delay. Therefore,
the PIA eliminates skew between signals, making timing and
performance easy to predict.
Table 4. SRAM Functions
Inputs Cycle I/O Pins
/BE /WE /OE
1 X X None Disabled
0 1 1 Read Disabled
0 1 0 Read Enabled
0 0 1 Write Disabled
0 0 0 Write Enabled
276 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
I/O Control Blocks
The I/O control block allows each I/O pin to be individually configured
for input, output, or bidirectional operation. All I/O pins have a tri-state
buffer that is either individually controlled by one of the two local LAB
output enable signals generated within each LAB or directly connected to
GND or V
CC
. Figure 7 shows the I/O control block for FLASHlogic
devices.
Figure 7. FLASHlogic Device I/O Control Block
When the tri-state buffer control is connected to GND, the output is tri-
stated (high-impedance), and the I/O pin can be used as a dedicated
input. When the tri-state buffer control is connected to V
CC
, the output is
enabled.
The FLASHlogic architecture provides dual I/O feedback in which
macrocell and pin feedbacks are independent. When an I/O pin is
configured as an input, the associated macrocell can be used for buried
logic.
Input
Configuration
Device inputs, as well as I/O pins that are used as inputs, can be
optimized for minimum standby current during either CMOS or TTL
operation by using the
CMOS_LEVEL
keyword (for 5.0-V CMOS inputs)
and the
TTL_LEVEL
keyword (for TTL or 3.3-V CMOS inputs) available in
the PLDasm design language supported by PLDshell Plus.
TTL_LEVEL
is
the default condition for PLDasm.
from Macrocell
to PIA
VCC
OE1
OE2
GND
OE Control
Local LA B Output
Enable Signals
Open-Drain
Output Option
Altera Corporation 277
FLASHlogic Programmable Logic Device Family Data Sheet
Output
Configuration
FLASHlogic device outputs can be configured to meet a variety of system-
level requirements.
3.3-V or 5.0-V Operation
The pins in an I/O control block can operate at 3.3 V or 5.0 V. This
functionality enables the designer to mix 3.3-V outputs and 5.0-V inputs if
the appropriate V
CCO
pins are tied to a 3.3-V power supply. FLASHlogic
devices require a V
CC
of 5.0 V for normal operation. However, the V
CCO
pin associated with each LAB pair can be connected to either a 5.0-V or
3.3-V power supply to control the output voltages of the I/O pins of that
LAB pair. This feature allows FLASHlogic devices to be used in mixed-
voltage systems. For example, the devices can be used as an interface
between a 3.3-V CPU and 5.0-V peripheral logic.
Power sequencing is required when any or all LABs operate at 3.3-V
levels. Thus, the voltage levels of the 5.0-V source must be greater than or
equal to the 3.3-V source during power-up and power-down.
Open-Drain Output Option
FLASHlogic devices can be configured to provide an optional open-drain
output for each I/O pin. If desired, complex equations can be
implemented using multiple open-drain outputs with an externally
supplied pull-up resistor to emulate an additional
OR
plane.
CMOS-Compatible Outputs
A weak pull-up resistor is provided for CMOS-compatible outputs. This
resistor is always active in both 3.3-V and 5.0-V modes.
I/O Pull-Up Resistor
EPX8160 devices contain active-weak pull-up resistors on the I/O pins
that hold the I/O at a logic high during power-up, reconfiguration, and
erase/program cycles. This resistor is disabled during normal device
operation to reduce power consumption. Dedicated inputs do not have
active pull-up resistors.
278 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
High Drive Outputs
EPX880 and EPX8160 output buffers are designed specifically for
applications requiring high drive current. These buffers enable the
devices to drive a bus (including PCI), and concurrently provide 10-ns
pin-to-pin performance, which eliminates the need for external buffers
and their associated delays.
PCI Compliance
EPX880 and EPX8160 5.0-V output buffers are designed to meet the
current-vs.-voltage specifications for PCI. EPX880-10 and EPX8160-10
devices also offer a predictable, 10-ns pin-to-pin propagation delay, a 6-ns
clock-to-signal valid delay, and a 6.5-ns synchronous setup time to meet
the timing demands of PCI applications. To support bidirectional PCI
signals, two output enable product terms are provided in each LAB, for a
total of 16 product terms for EPX880 devices and 32 product terms for
EPX8160 devices.
fGo to Application Note 41 (PCI Bus Applications in Altera Devices) for more
information on using EPX8160 devices in PCI applications.
JTAG Operation FLASHlogic devices support JTAG IEEE Std. 1149.1-1990 boundary-scan
testing (BST). The JTAG BST architecture enables fault-isolation testing of
board designs at the device level, enhances production testing and field
repair, and is ideal for fault-tolerant applications.
FLASHlogic BST support consists of an instruction register, a data
register, scan cells, and associated logic, all of which are accessed through
the test access port (TAP). The TAP interface consists of three inputs—test
mode select (TMS), test data input (TDI), and test clock input (TCK)—and
one output, test data output (TDO).
An EPX880 device contains one JTAG TAP controller. An EPX8160 device
contains two JTAG TAP controllers, each of which can operate
independently or simultaneously for reconfiguration, reprogramming,
and boundary-scan testing. Figure 8 shows the internal connection of the
JTAG TAP controllers.
Altera Corporation 279
FLASHlogic Programmable Logic Device Family Data Sheet
Figure 8. JTAG TAP Controller Connections
5.0 or 12.0 V 3.3 or 5.0 V
0.1 µF
VPP0
VPP VCCO0/2
TAP Controller
(LABs 0 to 7)
TDO TDI
TMS TCK
0.1 µF
JTAG Interface
5.0 or 12.0 V 3.3 or 5.0 V
0.1 µF
VPP1 VCCO8/10
VPP
TAP Controller
(LABs 8 to 15)
TDO TDI
TMS TCK
0.1 µF
TDO TMS TDI
TCK
VCCO0/2
VCCO8/10
TDO TDI
TMS TCK
JTAG Interface
TDO TCK TDITMS
VCCO0VPP
Note (1)
3.3 or 5.0 V
0.1 µF
VPP
0.1 µF
VCCO0
TAP Controller
(LABs 0 to 7)
EPX880
EPX8160
Note:
(1) 5.0 or 12.0 V for EPX880 devices.
280 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
In FLASHlogic devices, the boundary-scan I/O pins are linked to form a
shift register chain for all active pins. This chain provides a path that can
be used to shift boundary-scan data into and out of the device.
For example, a continuity test can be performed between two JTAG
devices on a circuit board by placing a known value on the output buffers
of one device and observing the input buffers of the other device. The
same technique can also be used to perform in-circuit functional testing of
FLASHlogic devices for prototyping new system designs.
The 4-pin JTAG test interface is also used for standard programming, ICR,
and ISP.
Boundary-Scan Instructions
The FLASHlogic boundary-scan instruction register (IR) supports the
JTAG instructions used for the Program/Verify modes. See Table 5.
fGo to Application Note 39 (JTAG Boundary-Scan Testing in Altera Devices) for
more information about JTAG operation.
Table 5. Boundary-Scan Instructions
Name Instruction Code
(MSB..LSB) Description
EXTEST 00000 The EXTEST instruction drives the output pins to the values
contained in the boundary-scan cells. The instruction tests the
external circuitry used for printed circuit board interconnects.
BYPASS 11111 The BYPASS instruction selects the one-bit bypass register
(BPR) to be connected to TDI and TDO, which allows BST data
to pass synchronously through the selected device to adjacent
devices during normal device operation.
SAMPLE/PRELOAD 00001 The SAMPLE/PRELOAD instruction allows a snapshot of the
values of the device pins to be captured and examined during
normal device operation, and to preload data onto the device
pins that are driven to the system circuit board when executing
the EXTEST instruction.
IDCODE 00010 The IDCODE instruction selects the ID code register and places
it between TDI and TDO, allowing the ID code to be serially
shifted out of TDO.
UESCODE 10110 The UESCODE instruction selects the user electronic signature
(UES) register and places it between TDI and TDO, allowing the
UES register to be serially shifted out of TDO.
HIZ 11101 The HIZ instruction sets all I/O pins to a high-impedance state.
Altera Corporation 281
FLASHlogic Programmable Logic Device Family Data Sheet
ICR & ISP FLASHlogic devices support in-circuit reconfigurability (ICR). Using the
4-pin JTAG test port, a new configuration can be downloaded to the
SRAM by simply shifting the new data into the device. Device
reconfiguration can be repeated as many times as desired during
prototyping. During ICR, all I/O pins on the device are tri-stated.
Once the design is finalized, it can be programmed into the nonvolatile
shadow FLASH cells. FLASHlogic devices support in-system
programmability (ISP), allowing devices to be programmed while
mounted on a printed circuit board. ISP allows devices to be programmed
in-system using the JTAG test port and the programming voltage pins
(VPP). FLASH-based devices can be programmed up to 100 times. During
ISP, all I/O pins on the device are tri-stated.
During ICR and ISP, the I/O pins of FLASHlogic devices are tri-stated. In
addition, the I/O pins for an EPX8160 device have a weak pull-up
transistor. Refer to the “Pin Descriptions” on page 298 section of this data
sheet for more information.
fFor more information on ICR and ISP, go to the following documents:
■Product Information Bulletin 19 (ICR & ISP: In-Circuit Reconfigurability
& In-System Programmability)
■Application Note 45 (Configuring FLASHlogic Devices)
■Application Brief 145 (Designing for In-System Programmability in
MAX 7000S Devices)
Design Security FLASHlogic devices contain a programmable security bit that controls
access to the data programmed into the device. Once this security bit is set,
the design cannot be read from the nonvolatile cells or the SRAM. The
state of the nonvolatile security bit at power-up determines whether data
programmed into the device can be accessed and changed by in-circuit
reconfiguration.
Generic Testing FLASHlogic devices are fully functionally tested. Complete testing of
each programmable FLASH bit and all internal logic elements ensures
100% programming yield. AC test measurements are taken under
conditions equivalent to those shown in Figure 9. Test patterns can be
used and erased during early stages of the device production flow.
282 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
Figure 9. FLASHlogic AC Test Conditions
Software
Support
FLASHlogic devices are supported by industry-standard PC- and
workstation-based EDA tools, including the Altera PLDshell Plus
development system and the FLASHlogic Download Cable. In addition,
MAX+PLUS II provides programming and configuration support. See the
MAX+PLUS II Programmable Logic Development System & Software Data
Sheet in this data book for more information.
fGo to the PLDshell Plus/PLDasm User’s Guide for information on
programming and configuring FLASHlogic devices using PLDshell Plus.
Table 6 lists the third-party vendors that provide software support.
VCC
to Test
System
C1 (includes JIG
capacitance)
Device input
rise and fall
times < 3 ns
165 Ω
Device
Output
100 Ω
Power-supply transients can affect AC
measurements. For accurate
measurements, avoid simultaneous
transitions of multiple outputs. Do not
perform threshold tests under AC
conditions. Large-amplitude, fast
ground-current transients normally occur
as the device outputs discharge the load
capacitances. When these transients flow
through the parasitic inductance between
the device ground pin and the test system
ground, they can significantly reduce
observable noise immunity.
Altera Corporation 283
FLASHlogic Programmable Logic Device Family Data Sheet
Simulation models are provided by the following vendors:
■Synopsys Logic Modeling SmartModel—Device model support for
behavioral simulation through a variety of simulators.
■Viewlogic ViewSim—Simulation model for Viewlogic verification
tools.
Device
Programming
FLASHlogic devices can be programmed with MAX+PLUS II software on
486- and Pentium-based PCs using an Altera Logic Programmer card, the
Master Programming Unit (MPU), and the appropriate device adapter.
The MPU performs continuity checking to ensure adequate electrical
contact between the adapter and the device. See the Altera Programming
Hardware Data Sheet in this data book for more information.
FLASHlogic devices can also be programmed in-system with the
MAX+PLUS II software using the BitBlaster serial download cable, and
with the PLDshell Plus software using the Altera FLASHlogic Download
Cable. Data I/O and other programming hardware manufacturers also
provide programming support for FLASHlogic devices. See Programming
Hardware Manufacturers in this data book for more information.
Table 6. Third-Party Software Support
Vendor Software Description
Data I/O
Corporation ABEL Design software that describes and
implements logic designs.
Synario 2.0 Integrated text and graphic design
and simulation environment.
Logical Devices,
Inc. CUPL High-level, universal design software
package.
MINC, Inc. PLDesigner-XL(R) Design tool for all types of
programmable logic with automatic
device selection, automatic
partitioning, and functional
simulation.
OrCAD Systems
Corporation PLD Tools (PLD) and
Schematic Design Tool
(SDT)
Design tools that Include schematic
entry, test vector generation, and
multiple forms of input.
Verification and
Simulation Tool (VST) Series of software tools for
performing timing-based simulation
of designs.
Viewlogic
Systems, Inc. Workview, PRO Series,
and Powerview Integrated schematic capture and
simulation environments.
284 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
FLASHlogic Device Absolute Maximum Ratings Note (1)
FLASHlogic Device Recommended Operating Conditions
FLASHlogic Device DC Operating Conditions Note (3)
Symbol Parameter Conditions Min Max Unit
VCC Supply voltage With respect to GND,
Note (2)
–2.0 7.0 V
VPP Programming supply voltage: EPX880 & EPX8160 –2.0 12.6 V
VIDC input voltage –0.5 VCC + 0.5 V
TSTG Storage temperature No bias –65 150 ° C
TAMB Ambient temperature Under bias –10 85 ° C
TJJunction temperature Plastic packages, under bias 135
Symbol Parameter Conditions Min Max Unit
VCC Supply voltage: 5.0 V 4.75 5.25 V
VCCO Output supply voltage: 5.0 V 4.75 5.25 V
VCCO Output supply voltage: 3.3 V 3.0 3.6 V
VIInput voltage 0 VCC V
VO Output voltage 0 VCCO V
TAOperating temperature For commercial use 0 70 ° C
TAOperating temperature For industrial use –40 85 ° C
tRInput rise time 500 ns
tFInput fall time 500 ns
Symbol Parameter Conditions Min Max Unit
VIH High-level input voltage 2.0 VCC + 0.3 V
VIL Low-level input voltage –0.3 0.8 V
VOH 5.0-V TTL high-level output
current EPX880 & EPX8160: IOH = –16.0 mA DC, VCCO = min.,
Note (4)
2.4 V
5.0-V CMOS high-level
output current EPX880 & EPX8160: IOH = –100 µA DC, VCCO = min.,
Note (4)
VCCO – 0.2 V
3.3-V high-level output
current EPX880 & EPX8160: IOH = –100 µA DC, VCCO = min.,
Note (4)
VCCO – 0.2 V
VOL 5.0-V low-level output
current EPX880 & EPX8160: IOL = 24 mA DC, VCCO = min.,
Note (4)
0.45 V
3.3-V low-level output
current EPX880 & EPX8160: IOL = 12 mA DC, VCCO = min.,
Note (4)
0.2 V
IIInput leakage current VCCO = max., GND < VIN < VCCO,
Note (5)
–10 10 µA
IOZ Output leakage current EPX880 & EPX8160: VCCO = max., VOUT = VCCO –50 50 µA
EPX880 & EPX8160: VCCO = max., VOUT = GND –100 100 µA
ISC Output short circuit current,
Note (6)
VCCO = max., VOUT = 0.5 V –30 –120 mA
Altera Corporation 285
FLASHlogic Programmable Logic Device Family Data Sheet
FLASHlogic Device Programming Conditions
Notes (3), (7)
FLASHlogic Device Capacitance
Notes (8), (9)
FLASHlogic Device I
CC
Supply Current Values
Note (8)
Notes to tables:
(1) See
Operating Requirements for Altera Devices Data Sheet
in this data book.
(2) The minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 7.0 V for
periods of less than 20 ns under no-load conditions.
(3) Operating conditions: T
A
= 0
°
C to 70
°
C, V
CC
= 5.0 V
±
5
%
for commercial use.
T
A
= –40
°
C to 85
°
C, V
CC
= 5.0 V
±
5
%
for industrial use.
(4) The I
OH
parameter refers to high-level TTL output current. The I
OL
parameter refers to low-level TTL output
current.
(5) Input leakage current on JTAG pins is tested at
±
20
µ
A.
(6) No more than 1 output should be tested at a time. The duration of the test should not exceed 1 second.
(7) Typical values are for T
A
= 25
°
C, V
CC
= 5.0 V, V
PP
= 12.0 V.
(8) Typical values are for T
A
= 25
°
C, V
CC
= 5.0 V.
(9) Capacitance is measured at 25
°
C, and is sample-tested only.
(10) Measured with a 20-bit, loadable, enabled, up/down counter programmed into each LAB pair.
Symbol Parameter Conditions Min Typ Max Unit
V
PP
Programming voltage: EPX880 & EPX8160 11.4 12 12.6 V
I
PP1
V
PP
read current, IC current, or standby current V
PP
> V
CC
90 200
µ
A
V
PP
≤
V
CC
15 40
µ
A
I
PP2
V
PP
programming or program verify current:
EPX880 & EPX8160 V
PP
= V
PPH
Programming in progress 30 60 mA
I
PP3
V
PP
erase and erase verify current V
PP
= V
PPH
30 60 mA
E
CNT
Erase and reprogram count limit 100 –
Symbol Parameter Conditions Typ Max Unit
C
IN
Input pin capacitance V
IN
= 2 V, f = 1.0 MHz 10 12 pF
C
I/O
I/O pin capacitance V
OUT
= 2 V, f = 1.0 MHz 12 15 pF
C
CLK
Clock pin capacitance V
OUT
= 2 V, f = 1.0 MHz 15 18 pF
C
VPP
V
PP
pin capacitance f = 1.0 MHz 12 15 pF
Symbol Parameter Conditions EPX880 EPX8160 Unit
I
CC1
V
CC
supply current (standby, typical) V
CC
= max.,
V
IN
= V
CC
or GND,
standby mode,
Note (10)
11mA
I
CC
V
CC
supply current (active, typical) V
IN
= V
CC
or GND, no
load,
Note (10)
1.5 2.5 mA/
MHz
286 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
Figure 10 shows the typical output drive characteristics for FLASHlogic
devices.
Figure 10. Output Drive Characteristics of FLASHlogic Devices
Timing Model FLASHlogic devices have fixed internal delays that allow the user to
determine the worst-case timing for any design. Device timing can be
analyzed with a variety of industry-standard EDA simulators and timing
analyzers, or with the timing model shown in Figure 11.
0.45
VO Output Voltage (V)
12345
40
80
120
200
160
VCCO = 3.3 V
IOL
IOH
Room Temp.
IO Output Current (mA) Typ.
60
100
140
20
3.3
180
0.45
VO Output Voltage (V)
12345
40
80
120
200
160
VCCO = 5.0 V
IOL
IOH
Room Temp.
IO Output Current (mA) Typ.
60
100
180
140
20
Altera Corporation 287
FLASHlogic Programmable Logic Device Family Data Sheet
Figure 11. FLASHlogic Timing Model
Industry-standard EDA tools provide timing simulation, point-to-point
delay prediction, and detailed analysis for system-level performance
evaluation. External timing parameters represent pin-to-pin timing
delays. Switching waveforms for these timing parameters (including
SRAM read and SRAM write cycles) are shown in Figure 12.
fGo to Application Note 79 (Understanding FLASHlogic Timing) for more
information on FLASHlogic timing parameters.
Input
Delay
t
IN
Control Delay
t
SOE
t
LAC
t
IC
t
AA
t
IDD
t
WASU
t
WAH
t
WDSU
t
WDH
t
WP
SRAM Delay
Feedback
Delay
t
FD
Logic Arra y
Delay
t
LAD
t
ICOMP
I/O Delay
t
IO
PIA
Delay
t
PIA
Output
Delay
t
OD
t
XZ
t
ZX
Global Clock
Delay
t
GLOB
t
DGLOB
Register
Delay
t
ISU
t
IH
t
IASU
t
IAH
t
RD
t
COMB
t
PRE
t
CLR
t
SISU
t
SIH
288 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
Figure 12. Switching Waveforms (Part 1 of 3)
Array Clock Mode
Input or I/O Pin
Clock into PIA
Clock into
Logic Array
Clock at
Register
Data from
Logic Array
Register to PIA
to Logic Array
Register Output
to Pin
t
F
t
R
t
ACH
t
ACL
t
IASU
t
IN
, t
IO
t
RD
t
PIA
t
CLR
, t
PRE
t
IAH
t
PIA
t
IC
t
PIA
t
OD
t
OD
t
LAC
, t
ICOMP
Combinatorial Mode
Input Pin
I/O Pin
PIA Delay
Logic Array
Input
Logic Array
Output
Output Pin
t
IN
t
PIA
t
OD
t
IO
t
COMB
Global Clock Mode
Global
Clock Pin
Global Clock
at Register
Data or Enable
(Logic Array Output)
t
F
t
CH
t
CL
t
R
t
IN
t
GLOB
t
ISU
t
IH
Altera Corporation 289
FLASHlogic Programmable Logic Device Family Data Sheet
Figure 12. Switching Waveforms (Part 2 of 3)
Data-in/out
Address
tWP
tAS
out in
/WE
/BE
/OE
tWR
SRAM Write Cycle 1 (/WE-Controlled Timing)
/OE
/BE tOLZ
Address
tRC
tBHZ
tBLZ
SRAM Read Cycle
tOHZ tDW
tAW
tWC
tDH
Data-out
tOH
tABE
tOE
tAA
WE
Address
CLK
Data-out
Register SRAM Read
a0
d3
tSSU
a1 a2 a3
d2
tSH
d1
tCO1
tCP
290 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
Figure 12. Switching Waveforms (Part 3 of 3)
FLASHlogic Device AC Operating Conditions
External Timing Parameters
EPX880-10
EPX8160-10
EPX880-12
EPX8160-12
Combinatorial Mode
Symbol Parameter Conditions Min Max Min Max Unit
tPD1 Input to nonregistered output C1 = 35 pF 10 12 ns
tPD2 I/O to nonregistered output CF = 35 pF 10 12 ns
tPZX Input or I/O to output enable C1 = 35 pF 12 14 ns
tPXZ Input or I/O to output disable C1 = 5 pF 12 14 ns
tCLR Array output clear time 15 18 ns
tCOMP Comparator input or I/O feedback to output valid 10 12 ns
SRAM Write Cycle 2 (/BE-Controlled Timing)
Data-in/out
Address
tBW
tAS
tDW
out in
/WE
/BE
/OE
tWR
tOHZ tDH
tAW
tWC
Altera Corporation 291
FLASHlogic Programmable Logic Device Family Data Sheet
External Timing Parameters
EPX880-10
EPX8160-10
EPX880-12
EPX8160-12
Register Mode—Global Clock
Symbol Parameter Conditions Min Max Min Max Unit
f
MAX
Maximum frequency
Note (1)
100 83.3 MHz
t
SU
Input setup time 6.5 8 ns
t
H
Input hold time 0 0 ns
t
CH
Clock high time 4.5 5.5 ns
t
CL
Clock low time 4.5 5.5 ns
t
CP
Clock period 10 12 ns
t
CO
Clock-to-output delay C1 = 35 pF 6 7.5
t
ODH
Output data hold time after clock C1 = 35 pF
Note (2)
11ns
t
CNT
Minimum clock period 12.5 15.5
f
CNT
Maximum internal frequency
Note (3)
80 64.5 MHz
External Timing Parameters
EPX880-10
EPX8160-10
EPX880-12
EPX8160-12
Register Mode—Delayed Global Clock
Symbol Parameter Conditions Min Max Min Max Unit
f
MAX
Maximum frequency
Note (1)
95.2 80 MHz
t
DSU
Input setup time 5 6 ns
t
DH
Input hold time 2 2 ns
t
CH
Clock high time 4.5 5.5 ns
t
CL
Clock low time 4.5 5.5 ns
t
CP
Clock period 10.5 12.5 ns
t
DCO
Clock-to-output delay C1 = 35 pF 8 9.5 ns
t
ODH
Output data hold time after clock C1 = 35 pF
Note (2)
11ns
t
DCNT
Minimum clock period 13 15.5 ns
f
DCNT
Maximum internal frequency
Note (3)
76.9 64.5 MHz
292 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
External Timing Parameters
EPX880-10
EPX8160-10
EPX880-12
EPX8160-12
Register Mode—Array Clock
Symbol Parameter Conditions Min Max Min Max Unit
f
AMAX
Maximum frequency
Note (1)
80 66.7 MHz
t
ASU
Input setup time 2 2.5 ns
t
AH
Input hold time 5 6 ns
t
ACH
Clock high time 5 5.5 ns
t
ACL
Clock low time 5 5.5 ns
t
ACP
Clock period 12.5 15 ns
t
ACO
Clock-to-output delay C1 = 35 pF 12 14.5 ns
t
ODH
Output data hold time after clock C1 = 35 pF
Note (2)
11ns
t
ACNT
Minimum clock period 14 17 ns
f
ACNT
Maximum internal frequency
Note (3)
71.4 58.8 MHz
External TIming Parameters
EPX880-10
EPX8160-10
EPX880-12
EPX8160-12
SRAM Read
Note (4)
Symbol Parameter Conditions Min Max Min Max Unit
t
RC
Read cycle time 15 18 ns
t
AA
Address access time 15 18 ns
t
ABE
Block enable access time 12 15 ns
t
OE
Output enable to output delay
Note (5)
12 15 ns
t
OH
Output hold from address change 2 3 ns
t
BLZ
Block enable to output in low impedance
Note (5)
34ns
t
BHZ
Block disable to output in high impedance C1 = 5 pF
Note (5)
12 15 ns
t
OLZ
Output enable to output in low impedance
Note (5)
34ns
External Timing Parameters
EPX880-10
EPX8160-10
EPX880-12
EPX8160-12
Register SRAM Read—Global
Note (4)
Symbol Parameter Conditions Min Max Min Max Unit
t
SSU
Input or I/O setup time to clock 11 13 ns
t
SH
Input or I/O hold time from clock 0 0 ns
t
CO1
Clock-to-output delay 6 7.5 ns
t
CL
Clock low time 4.5 5.5 ns
t
CH
Clock high time 4.5 5.5 ns
t
CP
Clock period 15 17 ns
Altera Corporation 293
FLASHlogic Programmable Logic Device Family Data Sheet
External Timing Parameters
EPX880-10
EPX8160-10
EPX880-12
EPX8160-12
Register SRAM Read—Delayed Global
Note (4)
Symbol Parameter Conditions Min Max Min Max Unit
t
SSU
Input or I/O setup time to clock 10 11 ns
t
SH
Input or I/O hold time from clock 2 2 ns
t
CO1
Clock-to-output valid 8 9.5 ns
t
CL
Clock low time 4.5 5.5 ns
t
CH
Clock high time 4.5 5.5 ns
t
CP
Clock period 15.5 17.5 ns
External Timing Parameters
EPX880-10
EPX8160-10
EPX880-12
EPX8160-12
SRAM Write
Note (4)
Symbol Parameter Conditions Min Max Min Max Unit
t
WC
Write cycle time 15 18 ns
t
BW
Block enable to end of write 10 12 ns
t
AW
Address valid to end of write 13 15 ns
t
AS
Address set-up time 3 4 ns
t
WP
Write pulse width 10 12 ns
t
WR
Write recovery time 2 3 ns
t
DW
Data valid to end of write 10 12 ns
t
DH
Data hold time 2 3 ns
t
OHZ
Output disable to valid data-in C1
=
5 pF
Notes (5), (6)
12 15 ns
294 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
Internal Timing Parameters
EPX880-10
EPX8160-10
EPX880-12
EPX8160-12
Combinatorial & Register Mode
Symbol Parameter Conditions Min Max Min Max Unit
t
IN
Input pad & buffer delay 1 1 ns
t
IO
I/O input pad & buffer delay 1 1 ns
t
FD
Register feedback delay 2 2 ns
t
LAD
Logic array delay 6 8 ns
t
ICOMP
Identity comparator delay 6 8 ns
t
LAC
Logic control array delay 8 10.5 ns
t
SOE
SRAM output enable delay 8 11.5 ns
t
OD
Output buffer & pad delay 1 1 ns
t
ZX
Output buffer enable delay 2 1.5 ns
t
XZ
Output buffer disable delay 2 1.5 ns
t
ISU
Register setup time,
Note (7)
2.5
(3) 3.5
(3.5) ns
t
IH
Register hold time,
Note (7)
5
(4) 4.5
(4.5) ns
t
IASU
Array clock register setup time 4 2.5 ns
t
IAH
Array clock register hold time 2.5 6 ns
t
RD
Register delay 1 1 ns
t
COMB
Combinatorial delay 1 1 ns
t
GLOB
Global clock delay 3 4.5 ns
t
DGLOB
Delayed global clock delay 5 6.5 ns
t
IC
Array clock delay 8 10.5 ns
t
PRE
Register preset time 4 4.5 ns
t
CLR
Register clear time 4 4.5 ns
t
PIA
Programmable interconnect array delay 1 1 ns
Altera Corporation 295
FLASHlogic Programmable Logic Device Family Data Sheet
Notes to tables:
(1) The fMAX values represent the highest frequency for pipelined data.
(2) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
(3) Measured with a 10-bit loadable, enabled, up/down binary counter programmed into each LAB.
(4) Operating conditions: TA = 0° C to 70° C, VCC = 5.0 V ± 5% for commercial use.
T
A
= –40° C to 85° C, VCC = 5.0 V ± 5% for industrial use.
(5) These signals are measured at ± 0.5 V from steady-state voltage as driven by specified output load. Enable values
are measured starting from 1.5 V on output.
(6) These specifications do not apply when separate data-in and data-out buses are used.
(7) When using the delay clock, calculate the timing with the values in parentheses.
Power
Consumption
Supply power (P) versus frequency (fMAX in MHz) for FLASHlogic
devices is calculated with the following equation:
P = PINT + PIO
P = ICCACTIVE × VCC + PIO
The PIO value, which depends on the device output load characteristics
and switching frequency, can be calculated using the guidelines provided
in Application Note 74 (Evaluating Power for Altera Devices) in this data book.
The ICCACTIVE value depends on the switching frequency and the
application logic. The ICCACTIVE value is calculated with the following
equation:
ICCACTIVE = A × MC + C × MC × fMAX × togLC
Internal Timing Parameters
EPX880-10
EPX8160-10
EPX880-12
EPX8160-12
SRAM Mode
Symbol Parameter Conditions Min Max Min Max Unit
t
AA
SRAM address access delay 11 14 ns
t
DD
SRAM data-in to data-out delay ns
t
WASU
SRAM write address setup time 3 4 ns
t
WAH
SRAM write address hold time 2 3 ns
t
WDSU
SRAM write data setup time 10 12 ns
t
WDH
SRAM write data hold time 2 3 ns
t
SISU
SRAM internal register setup time,
Note (7)
2
(3) 2.5
(2.5) ns
t
SIH
SRAM internal register hold time 9 10.5 ns
t
WP
SRAM write pulse width 10 12 ns
296 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
The parameters in this equation are as follows:
MC = Number of macrocells used in the design
fMAX = Highest clock frequency to the device
togLC = Average ratio of logic cells toggling at each clock
(typically 0.125)
A, C = Constants, shown in Table 7
The formula for calculating ICCACTIVE provides an estimate based on typical
conditions using a typical pattern of a 20-bit, loadable, enabled, up/down
binary counter with no output load in each pair of LABs. Actual ICC
values should be verified during operation because this measurement is
sensitive to the actual pattern in the device and the environmental
operating conditions.
Figure 13 shows typical ICC supply current versus frequency curves for
FLASHlogic devices.
Figure 13. I
CC
vs. Frequency for FLASHlogic Devices
Table 7. FLASHlogic I
CC
Equation Constants
Device Constant A Constant C
EPX880 0.0125 0.150
EPX8160 0.0062 0.125
VCC = 5.0 V
Room Temp.
0
Frequency (MHz)
ICC Active (mA) Typ.
60
80
40
20 40 80 100
120
160
200 83 MHz
80
VCC = 5.0 V
Room Temp.
0
Frequency (MHz)
ICC Active (mA) Typ.
60
20 40 100
83 MHz
80
120
100
40
60
20
140
EPX880 EPX8160
Altera Corporation 297
FLASHlogic Programmable Logic Device Family Data Sheet
Power-Up Cycle Because VCC rise times can vary significantly from one application to
another, the device power-up cycle time varies. For a monotonic VCC rise
(1 ms/V minimum), the power-up cycle begins when VCC reaches its
minimum value and ends 100 µs after VCC reaches the minimum value.
Internal power-up reset circuits ensure that all flipflops are reset to a logic
low after the device has powered up. Also, the JTAG TAP controller is put
into the test-logic-reset state. During power-up, EPX880 I/O pins are tri-
stated; EPX8160 I/O pins are held high by an active-weak pull-up resistor.
Upon completion of the power-up cycle, the outputs on an
unprogrammed EPX880 device are placed in a high-impedance state. The
outputs on an unprogrammed EPX8160 device are placed in a high-
impedance state if VPP is held below 2.0 V; the outputs are tri-stated if VPP
is held above 2.0 V.
Power-On
Reset (POR)
FLASHlogic device configuration data can be reloaded from FLASH
memory at any time by issuing a JTAG RESET instruction. For EPX880
and EPX8160 devices, the device configuration data from FLASH memory
can also be reloaded by holding VPP at a logic low (0.8 V maximum) for a
minimum of 300 ns. By holding VPP low during power-up, the power-up
cycle can be delayed. The power-up cycle is completed within a delay of
tRESET after VPP reaches 2.0 V (see Table 8). During normal operation, VPP
must be held at a logic high (2.4 V minimum) or tied to the VPP supply
(12.0 V) for EPX8160 devices.
During reconfiguration or reprogramming, the JTAG RESET instruction
is automatically issued by the PENGN or JED2JTAG software utilities
provided with PLDshell Plus. It is not necessary to pull VPP low for a
reconfiguration or reprogram cycle.
fFor more information on configuring or programming FLASHlogic
devices using the JTAG interface, go to the following documents:
■Application Note 45 (Configuring FLASHlogic Devices)
■Application Note 39 (JTAG Boundary-Scan Testing in Altera Devices
Table 8. Reset Characteristics
Symbol Parameter Value Conditions
tRESET JTAG reset time 150 µs maximum Software control
VPP ≥ 2.0 V
298 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
Pin
Descriptions
Table 9 describes the pin names and descriptions for FLASHlogic devices.
Note:
(1) Proper power decoupling is required on all power pins. A 0.1-µF decoupling
capacitor is recommended between each power pin and ground.
Table 9. Pins Descriptions
Pin Name Description
VCC,
Note (1)
Supply voltage. Must be connected to 5.0 V.
GND Ground connection.
VPP,
Note (1)
Programming voltage. When programming FLASHlogic
devices, 12.0 V must be supplied to this pin. When the EPX880
and EPX8160 devices are not in programming mode, VPP must
be connected to VCC or VPP. The EPX880 and EPX8160
devices will reset themselves if VPP is held below 0.8 V for a
minimum of 300 ns.
IN
n
Input-only pins. These pins are not available in all packages.
Unused inputs should be connected to VCC or GND.
TDI Test data input. This pin is the boundary-scan serial data input
to FLASHlogic devices. JTAG instructions and data are shifted
into FLASHlogic devices on the TDI input pin on the rising edge
of TCK. TDI can be left floating if unused.
TDO Test data output. This is the boundary-scan serial data output
from FLASHlogic devices. JTAG instructions and data are
shifted out of FLASHlogic devices on the TDO output pin on the
falling edge of TCK.
TCK Test clock input. This input provides the boundary-scan clock
for FLASHlogic devices. TCK clocks shift information and data
into and out of the FLASHlogic devices during boundary-scan or
programming modes. The maximum operating frequency of the
BST clock is 8 MHz. TCK can be left floating if unused.
TMS Test control input. This input provides the BST mode select for
FLASHlogic devices. TMS can be left floating if unused.
VCC0
n
,
Note (1)
Supply voltage for the outputs of the LABs. Connecting these
pins to 5.0 V causes the LAB to output 5.0-V signals.
Connecting these pins to 3.3 V causes the LAB to output 3.3-V
signals. These pins must always be connected to the desired
output drive voltage.
CLK
n
Global clock signals.
I/O
n
Pins configurable as inputs or outputs. Unused I/O pins should
be connected as shown in the Report File. The reserved pins
must be left unconnected. During ICR and ISP, the I/O pins of
FLASHlogic devices are tri-stated. In addition, the I/O pins for
an EPX8160 device has a weak pull-up transistor.
Altera Corporation 299
FLASHlogic Programmable Logic Device Family Data Sheet
Device
Pin-Outs
Tables 10 through 13 show the pin names and numbers for the pins in each
device FLASHlogic device package.
Table 10. EPX880 Pin-Outs
Pin Name 84-Pin PLCC 132-Pin PQFP
CLK1 3 118
CLK2 45 52
TDI 11 132
TDO 10 131
TMS 52 65
TCK 53 66
VPP 4 119
VCCIO0 25 117
VCCIO1 2 116
VCCIO2 24 19
VCCIO3 67 86
VCCIO4 25 20
VCCIO5 66 85
VCCIO6 44 50
VCCIO7 67 51
VCCINT 26, 68 21, 87
GND 17, 23, 29, 38, 46, 59,
65, 71, 80 11, 17, 18, 27, 44, 53, 59,
77, 83, 84, 93, 110, 125
Dedicated Inputs – 1, 2, 3, 4, 5, 33, 34, 35, 36,
37, 38, 67, 68, 69, 70, 71,
99, 100, 101, 102, 103,
104
300 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
Table 11. EPX880 I/O Pin-Outs (Part 1 of 2) Note (1)
LAB MC 84-Pin
J-Lead 132-Pin
PQFP LAB MC 84-Pin
J-Lead 132-Pin
PQFP
0 0 5 120 1 10 1 115
0 1 – 121 1 11 84 114
0 2 – 122 1 12 83 113
0 3 6 123 1 13 82 112
0 4 – 124 1 14 81 111
0 5 7 126 1 15 79 109
0 6 – 127 1 16 78 108
0 7 8 128 1 17 77 107
0 8 – 129 1 18 76 106
0 9 9 130 1 19 75 105
2 20 22 16 3 30 69 88
2 21 21 15 3 31 – 89
2 22 20 14 3 32 – 90
2 23 19 13 3 33 70 91
2 24 18 12 3 34 – 92
2 25 16 10 3 35 72 94
22615 9336– 95
22714 83377396
22813 7338– 97
22912 63397498
Altera Corporation 301
FLASHlogic Programmable Logic Device Family Data Sheet
Note:
(1) A dash (–) indicates that the macrocell is buried.
44027225506482
441 –235516381
442 –245526280
44328255536179
444 –265546078
44530285555876
446 –295565775
44731305575674
448 –315585573
44932325595472
66043497704754
6614248771 –55
6624147772 –56
66340467734857
6643945774 –58
66537437754960
6663642776 –61
66735417775062
6683440778 –63
66933397795164
Table 11. EPX880 I/O Pin-Outs (Part 2 of 2) Note (1)
LAB MC 84-Pin
J-Lead 132-Pin
PQFP LAB MC 84-Pin
J-Lead 132-Pin
PQFP
302 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
Table 12. EPX8160 Pin-Outs
Pin Name 208-Pin PQFP
CLK1 184
CLK2 181
CLK3 77
CLK4 80
TDI 1
TDO 208
TMS 105
TCK 104
VPP0 182
VPP1 79
VCCIO0/VCCIO2 204
VCCIO1/VCCIO3 161
VCCIO4/VCCIO6 13
VCCIO5/VCCIO7 144
VCCIO8/VCCIO10 57
VCCIO9/VCCIO11 100
VCCIO12/VCCIO14 40
VCCIO13/VCCIO15 117
VCCINT 14, 39, 118, 143
GND 7, 15, 21, 32, 38, 46, 67, 78, 90, 111, 119, 125, 136, 142,
150, 171,183, 194
Dedicated Inputs 52, 53, 54, 55, 56, 59, 61, 63, 65, 69, 71, 73, 75, 82, 84,
86, 88, 92, 94, 96, 98, 101, 102, 103, 156, 157, 158, 159,
160, 163, 165, 167, 169, 173, 175, 177, 179, 186, 188,
190, 192, 196, 198, 200, 202, 205, 206, 207
Altera Corporation 303
FLASHlogic Programmable Logic Device Family Data Sheet
Table 13. EPX8160 I/O Pin-Outs (Part 1 of 3) Note (1)
LAB MC 208-Pin
PQFP LAB MC 208-Pin
PQFP
0 0 185 1 10 180
0 1 187 1 11 178
0 2 189 1 12 176
0 3 191 1 13 174
0 4 193 1 14 172
0 5 195 1 15 170
0 6 197 1 16 168
0 7 199 1 17 166
0 8 201 1 18 164
0 9 203 1 19 162
2 20 6 3 30 151
221–331–
222–332–
2 23 5 3 33 152
224–334–
2 25 4 3 35 153
226–336–
2 27 3 3 37 154
228–338–
2 29 2 3 39 155
4 40 8 5 50 149
4 41 9 5 51 148
4 42 10 5 52 147
4 43 11 5 53 146
4 44 12 5 54 145
4 45 16 5 55 141
4 46 17 5 56 140
4 47 18 5 57 139
4 48 19 5 58 138
4 49 20 5 59 137
304 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
6 60 26 7 70 131
661–771–
662–772–
6 63 25 7 73 132
664–774–
6 65 24 7 75 133
666–776–
6 67 23 7 77 134
668–778–
6 69 22 7 79 135
8 80 76 9 90 81
8 81 74 9 91 83
8 82 72 9 92 85
8 83 70 9 93 87
8 84 68 9 94 89
8 85 66 9 95 91
8 86 64 9 96 93
8 87 62 9 97 95
8 88 60 9 98 97
8 89 58 9 99 99
10 100 47 11 110 110
10 101 – 11 111 –
10 102 – 11 112 –
10 103 48 11 113 109
10 104 – 11 114 –
10 105 49 11 115 108
10 106 – 11 116 –
10 107 50 11 117 107
10 108 – 11 118 –
10 109 51 11 119 106
Table 13. EPX8160 I/O Pin-Outs (Part 2 of 3) Note (1)
LAB MC 208-Pin
PQFP LAB MC 208-Pin
PQFP
Altera Corporation 305
FLASHlogic Programmable Logic Device Family Data Sheet
Note:
(1) A dash (–) indicates that the macrocell is buried.
12 120 45 13 130 112
12 121 44 13 131 113
12 122 43 13 132 114
12 123 42 13 133 115
12 124 41 13 134 116
12 125 37 13 135 120
12 126 36 13 136 121
12 127 35 13 137 122
12 128 34 13 138 123
12 129 33 13 139 124
14 140 27 15 150 130
14 141 – 15 151 –
14 142 – 15 152 –
14 143 28 15 153 129
14 144 – 15 154 –
14 145 29 15 155 128
14 146 – 15 156 –
14 147 30 15 157 127
14 148 – 15 158 –
14 149 31 15 159 126
Table 13. EPX8160 I/O Pin-Outs (Part 3 of 3) Note (1)
LAB MC 208-Pin
PQFP LAB MC 208-Pin
PQFP
306 Altera Corporation
FLASHlogic Programmable Logic Device Family Data Sheet
Pin-Out
Diagrams
Figures 14 and 15 show the package pin-out diagrams for FLASHlogic
devices.
Figure 14. EPX880 Package Pin-Out Diagram
Package outlines not drawn to scale. See Tables 10 and 11 for pin-out information.
I/O
I/O
I/O
GND
I/O
I/O
VCC
VCCO3/VCCO7
VCCO5
GND
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
132-Pin PQFP
Pin 34
Pin 67
EPX880
Pin 100
Pin 1
84-Pin J-Lead
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
GND
VCCO2
VCCO0/VCCO4
VCC
I/O
I/O
GND
I/O
I/O
I/O
TDI
TDO
I/O
I/O
I/O
I/O
I/O
VPP
CLK1
VCCO1
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
11
10
9
8
7
6
5
4
3
2
1
84
83
82
81
80
79
78
77
76
75
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCCO6
CLK2
GND
I/O
I/O
I/O
I/O
I/O
TMS
TCK
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
EPX880
Copyright ©
1995, 1996 Altera Corporation, 2610 Orchard Parkway,
San Jose, California 95134, USA, all rights reserved.
By accessing any information on this CD-ROM, you agree to be
bound by the terms of Altera’s Legal Notice.
