W3E64M72S-266SBI - Microsemi Corp.

W3E64M72S-XSBX

1White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

September 2007

Rev. 3

White Electronic Designs Corp. reserves the right to change products or speciﬁ cations without notice.

64Mx72 DDR SDRAM

FEATURES

 Data rate = 200, 250, 266 and 333Mbs**

 Package:

• 219 Plastic Ball Grid Array (PBGA), 25 x 32mm

 2.5V ±0.2V core power supply

 2.5V I/O (SSTL_2 compatible)

 Differential clock in puts (CK and CK#)

 Commands entered on each positive CK edge

 Internal pipelined double-data-rate (DDR)

ar chi tec ture; two data accesses per clock cy cle

 Programmable Burst length: 2,4 or 8

 Bidirectional data strobe (DQS) transmitted/

re ceived with data, i.e., source-syn chro nous data

capture (one per byte)

 DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

 DLL to align DQ and DQS transitions with CK

 Four internal banks for concurrent operation

 Data mask (DM) pins for masking write data

(one per byte)

 Auto precharge option

 Auto Refresh and Self Refresh Modes

 Commercial, Industrial and Military

TemperatureRang es

 Organized as 64M x 72

 Weight: W3E64M72S-XSBX - 4.5 grams typical

* This product is subject to change without notice. This product has been qualiﬁ ed

for commercial and industrial temperature ranges.

** For 333Mbs operation of Industrial temperature CL = 2.5, at Military temperature

CL = 3.

BENEFITS

 66% Space Savings vs. TSOP

 Re duced part count

 55% I/O reduction vs TSOP

 Reduced trace lengths for lower parasitic

capacitance

 Suitable for hi-reliability applications

 Laminate interposer for optimum TCE match

GENERAL DESCRIPTION

The 512MByte (4Gb) DDR SDRAM is a high-speed CMOS,

dy nam ic ran dom-access, memory using 9 chips containing

536,870,912 bits. Each chip is internally configured as a

quad-bank DRAM.

The 512MB DDR SDRAM uses a double data rate

ar chi tec ture to achieve high-speed operation. The

double data rate ar chi tec ture is essentially a 2n-prefetch

architecture with an in ter face designed to transfer two data

words per clock cycle at the I/O pins. A single read or write

access for the 512MB DDR SDRAM effectively consists

of a single 2n-bit wide, one-clock-cycle data tansfer at the

internal DRAM core and two cor re spond ing n-bit wide,

one-half-clock-cycle data transfers at the I/O pins.

A bi-directional data strobe (DQS) is transmitted

externally, along with data, for use in data capture at the

receiver.strobe transmitted by the DDR SDRAM during

READs and by the memory contoller during WRITEs. DQS

is edge-aligned with data for READs and center-aligned

with data for WRITEs. Each chip has two data strobes, one

for the lower byte and one for the upper byte.

The 512MB DDR SDRAM operates from a differential clock

(CK and CK#); the crossing of CK going HIGH and CK#

going LOW will be referred to as the positive edge of CK.

Com mands (ad dress and control signals) are registered

at every positive edge of CK. Input data is registered on

both edg es of DQS, and out put data is ref er enced to both

edges of DQS, as well as to both edges of CK.

W3E64M72S-XSBX

2White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

September 2007

Rev. 3

White Electronic Designs Corp. reserves the right to change products or speciﬁ cations without notice.

DENSITY COMPARISONS

Read and write accesses to the DDR SDRAM are burst

ori ent ed; accesses start at a selected location and continue

for a pro grammed number of locations in a programmed

sequence. Accesses begin with the registration of an

AC TIVE command, which is then followed by a READ or

WRITE command. The address bits registered coincident

with the ACTIVE command are used to select the bank

and row to be accessed. The ad dress bits registered

coincident with the READ or WRITE com mand are used

to select the bank and the starting column location for the

burst access.

The DDR SDRAM provides for programmable READ

or WRITE burst lengths of 2, 4, or 8 locations. An auto

precharge func tion may be enabled to provide a self-

timed row precharge that is initiated at the end of the

burst access.

The pipelined, multibank architecture of DDR SDRAMs al lows

for concurrent operation, thereby providing high ef fec tive

band width by hiding row precharge and activation time.

An auto refresh mode is provided, along with a power-

saving power-down mode. All inputs are compatible with

the Jedec Standard for SSTL_2. All full drive options

outputs are SSTL_2, Class II compatible.

FUNCTIONAL DE SCRIP TION

Read and write accesses to the DDR SDRAM are burst

ori ent ed; accesses start at a selected location and continue

for a pro grammed number of locations in a pro grammed

se quence. Ac cess es begin with the registration of an

AC TIVE com mand which is then followed by a READ or

WRITE com mand. The address bits registered coincident

with the AC TIVE command are used to select the bank and

row to be accessed (BA0 and BA1 select the bank, A0-12

select the row). The address bits registered coincident

with the READ or WRITE com mand are used to select the

start ing column location for the burst access.

Prior to normal operation, the DDR SDRAM must be

initialized. The following sections provide detailed

information cov er ing device initialization, register deﬁ nition,

command de scrip tions and de vice operation.

Discrete Approach

SAVINGS – Area: 66% – I/O Count: 55%

Area = 800mm2

Area: 9 x 265mm2 = 2,385mm2

I/O Count = 219 Balls

I/O Count: 9 x 54 pins = 486 pins

11.9 11.9 11.9 11.9 11.9 11.9 11.9 11.9 11.9

22.3

TSOP

ACTUAL SIZE

White Electronic Designs

W3E64M72S-XSBX

3White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

September 2007

Rev. 3

White Electronic Designs Corp. reserves the right to change products or speciﬁ cations without notice.

FIGURE 1 – PIN CONFIGURATION

NOTE: DNU = Do Not Use.

Top View

1 2345678910111213141516

DQ1

DQ3

DQ6

DQ7

CAS0#

CS0#

VSS

CLK3#

DQ56

DQ57

DQ60

DQ62

VSS

DQ30

DQ28

DQ25

DQ24

CLK1

CKE1

VCC

CS2#

CAS2#

DQ39

DQ38

DQ35

DQ33

VCC

DQ0

DQ2

DQ4

DQ5

DQML0

WE0#

RAS0#

VSS

CKE3

CLK3

DQMH3

DQ58

DQ59

DQ61

DQ63

DQ31

DQ29

DQ27

DQ26

DQMH1

CLK1#

VCCQ

RAS2#

WE2#

DQML2

DQ37

DQ36

DQ34

DQ32

DQ14

DQ12

DQ10

DQ8

VCC

DQ55

DQ53

DQ51

DQ49

DQ17

DQ19

DQ21

DQ23

VSS

Vss

VSS

DQ40

DQ42

DQ44

DQ46

DQ15

DQ13

DQ11

DQ9

DQMH0

CLK0

CKE0

VCCQ

CS3#

CAS3#

WE3#

DQ54

DQ52

DQ50

DQ48

DQ16

DQ18

DQ20

DQ22

DQML1

WE1#

CS1#

VSS

CKE2

CLK2

DQMH2

DQ41

DQ43

DQ45

DQ47

VSS

VCC

VCCQ

DQSH3

DQSL3

CLK0#

VSS

DQSL4

RAS3#

DQML3

VSS

VCC

VCCQ

VCC

VSS

VREF

RAS1#

CAS1#

VCC

CLK2#

DQSL2

CS4#

DQSH2

VCC

VSS

A12

DQSH0

DNU

DQSL1

WE4#

DQ70

DQ68

DQ66

DQ64

A10

DNU

BA0

CLK4

A11

DNU

BA1

CAS4#

DQ71

DQ69

DQ67

DQ65

VSS

VCC

VCCQ

DQSL0

CKE4

CLK4#

VSS

VCC

VCCQ

VCC

VSS

DQSH1

RAS4#

DQML4

VCC

VSS

W3E64M72S-XSBX

4White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

September 2007

Rev. 3

White Electronic Designs Corp. reserves the right to change products or speciﬁ cations without notice.

FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM

0-12

0-1

CK0

#CK#

CKE

DQML

IC1

0-12

0-1

CK1

#CK#

IC0

CKE

DQML

DQM

IC2

0-12

0-1

CK2

#CK#

CKE

DQML

DQM

IC3

0-12

0-1

CK3

#CK#

CKE

DQML

DQM

IC4

0-12

0-1

CK4

#CK#

CKE

DQML

DQM

CK0

CKE

DQMH

#CS#

RAS

CAS

WE# RAS# CAS#

# CS#

CK1

#CK#

CKE

DQMH

DQM

#CS#

RAS

CAS

WE# RAS# CAS#

# CS#

CK2

#CK#

CKE

DQMH

DQM

#CS#

RAS

CAS

WE# RAS# CAS#

# CS#

CK3

#CK#

CKE

DQMH

DQM

#CS#

RAS

CAS

WE# RAS# CAS#

# CS#

RAS

CAS

WE# RAS# CAS#

0-12

0-1

CK#

CK0

CK1

CK2

CK3

CK4

CK0

CK1

CK2

CK3

CKE

DQM

IC6

0-12

0-1

IC5

IC7

0-12

0-1

IC8

0-12

0-1

CS#

WE# RAS# CAS#

W3E64M72S-XSBX

5White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

September 2007

Rev. 3

White Electronic Designs Corp. reserves the right to change products or speciﬁ cations without notice.

INITIALIZATION

DDR SDRAMs must be powered up and initialized in a

pre deﬁ ned manner. Operational procedures other than

those speciﬁ ed may result in undeﬁ ned operation. Power

must ﬁ rst be applied to VCC and VCCQ simultaneously, and

then to VREF (and to the system VTT). VTT must be applied

after VCCQ to avoid device latch-up, which may cause

per ma nent dam age to the device. VREF can be applied any

time after VCCQ but is expected to be nominally coincident

with VTT. Except for CKE, inputs are not recognized as

valid until after VREF is applied. CKE is an SSTL_2

input but will detect an LVCMOS LOW level after VCC is

applied. After CKE passes through VIH, it will transition to

an SSTL_2 signal and remain as such until power is cycled.

Maintaining an LVCMOS LOW level on CKE during power-

up is required to ensure that the DQ and DQS outputs will

be in the High-Z state, where they will remain until driven

in normal operation (by a read ac cess). After all power

supply and reference voltages are stable, and the clock

is stable, the DDR SDRAM requires a 200μs delay prior

to applying an executable com mand.

Once the 200μs delay has been satisﬁ ed, a DESELECT

or NOP command should be applied, and CKE should

be brought HIGH. Following the NOP command, a

PRECHARGE ALL command should be applied. Next a

LOAD MODE REG IS TER command should be issued for

the extended mode register (BA1 LOW and BA0 HIGH)

to enable the DLL, fol lowed by another LOAD MODE

both LOW) to reset the DLL and to program the operating

parameters. Two-hundred clock cy cles are required

between the DLL reset and any READ command. A

PRECHARGE ALL command should then be applied,

placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must

be performed (tRFC must be satisﬁ ed.) Additionally, a LOAD

MODE REGISTER command for the mode register with

the reset DLL bit deactivated (i.e., to program operating

pa ram e ters without resetting the DLL) is required.

Following these requirements, the DDR SDRAM is ready

for normal op er a tion.

MODE REGISTER

The Mode Register is used to deﬁ ne the speciﬁ c mode of

op er a tion of the DDR SDRAM. This deﬁ nition includes the

selection of a burst length, a burst type, a CAS latency,

and an op er at ing mode, as shown in Figure 3. The Mode

Reg is ter is programmed via the MODE REG IS TER SET

command (with BA0 = 0 and BA1 = 0) and will retain

the stored in for ma tion until it is pro grammed again or

the device loses power. (Ex cept for bit A8 which is self

clearing).

Reprogramming the mode register will not alter the contents

of the memory, provided it is performed correctly. The Mode

Reg is ter must be load ed (reloaded) when all banks are

idle and no bursts are in progress, and the con trol ler must

wait the spec i ﬁ ed time be fore ini ti at ing the sub se quent

op er a tion. Vi o lat ing either of these re quire ments will result

in un spec i ﬁ ed operation.

Mode register bits A0-A2 specify the burst length, A3

spec i ﬁ es the type of burst (sequential or in ter leaved),

A4-A6 spec i fy the CAS latency, and A7-A12 specify the

op er at ing mode.

BURST LENGTH

Read and write ac cess es to the DDR SDRAM are burst

ori ent ed, with the burst length being programmable,

as shown in Fig ure 3. The burst length determines

the maximum num ber of column lo ca tions that can be

accessed for a given READ or WRITE command. Burst

lengths of 2, 4 or 8 lo ca tions are avail able for both the

sequential and the in ter leaved burst types.

Reserved states should not be used, as unknown op er a tion

or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of

col umns equal to the burst length is effectively selected.

All accesses for that burst take place within this block,

mean ing that the burst will wrap within the block if a

boundary is reached. The block is uniquely selected by

A1-Ai when the burst length is set to two; by A2-Ai when the

burst length is set to four (where Ai is the most signiﬁ cant

column address for a given conﬁ guration); and by A3-Ai

when the burst length is set to eight. The remaining (least

sig niﬁ cant) ad dress bit(s) is (are) used to select the starting

lo ca tion within the block. The pro grammed burst length

ap plies to both READ and WRITE bursts.

W3E64M72S-XSBX

6White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

September 2007

Rev. 3

White Electronic Designs Corp. reserves the right to change products or speciﬁ cations without notice.

BURST TYPE

Accesses within a given burst may be pro grammed to be

either se quen tial or interleaved; this is re ferred to as the

burst type and is selected via bit M3.

The ordering of accesses within a burst is de ter mined by

the burst length, the burst type and the start ing column

address, as shown in Table 1.

READ LATENCY

The READ latency is the delay, in clock cycles, between

the reg is tra tion of a READ command and the avail abil i ty

of the ﬁ rst bit of output data. The latency can be set to 2

or 2.5 clocks.

If a READ command is registered at clock edge n, and the

latency is m clocks, the data will be available by clock edge

n+m. Table 2 below indicates the op er at ing fre quen cies at

which each CAS latency setting can be used.

Reserved states should not be used as unknown operation

or incompatibility with future versions may result.

OPERATING MODE

The normal operating mode is selected by issuing a MODE

zero, and bits A0-A6 set to the desired values. A DLL reset

is initiated by issuing a MODE REGISTER SET command

with bits A7 and A9-A12 each set to zero, bit A8 set to one,

and bits A0-A6 set to the desired values. Although not

re quired, JEDEC speciﬁ cations recommend when a LOAD

MODE REG IS TER command is issued to reset the DLL, it

should always be followed by a LOAD MODE REGISTER

command to se lect nor mal op er at ing mode.

All other combinations of values for A7-A12 are reserved

for future use and/or test modes. Test modes and reserved

states should not be used because unknown operation or

incompatibility with future versions may result.

EXTENDED MODE REGISTER

The extended mode register controls functions beyond

those controlled by the mode register; these additional

functions are DLL enable/disable, output drive strength,

and QFC. These functions are controlled via the bits shown

in Figure 5. The extended mode register is programmed

via the LOAD MODE REGISTER command to the mode

stored information until it is programmed again or the

device loses power. The enabling of the DLL should always

be followed by a LOAD MODE REGISTER command to the

mode register (BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when all

banks are idle and no bursts are in progress, and the

controller must wait the speciﬁ ed time before initiating

any sub se quent operation. Violating either of these

requirements could result in unspeciﬁ ed operation.

TABLE 2 – CAS LATENCY

ALLOWABLE OPERATING FREQUENCY (MHz)

SPEED

CAS LATENCY = 2 CAS LATENCY = 2.5 CAS LATENCY = 3

-200 ≤ 75 ≤ 100 —

-250 ≤ 100 ≤ 125 —

-266 ≤ 100 ≤ 133 —

-333 IND ≤ 100 ≤ 166 ≤ 166

-333 MIL ≤ 100 ≤ 133 ≤ 166

OUTPUT DRIVE STRENGTH

The normal full drive strength for all outputs are speciﬁ ed to

be SSTL2, Class II. The DDR SDRAM supports an option

for reduced drive. This option is intended for the support

of the lighter load and/or point-to-point environments. The

selection of the reduced drive strength will alter the DQs

and DQSs from SSTL2, Class II drive strength to a reduced

drive strength, which is approximately 54 percent of the

SSTL2, Class II drive strength.

DLL ENABLE/DISABLE

When the part is running without the DLL enabled, device

functionality may be altered. The DLL must be enabled for

normal operation. DLL enable is required during power-

up initialization and upon re turn ing to normal operation

after having disabled the DLL for the purpose of debug or

evaluation. (When the device exits self refresh mode, the

DLL is enabled automatically.) Any time the DLL is enabled,

200 clock cycles with CKE high must occur be fore a READ

command can be issued.

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7White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

September 2007

Rev. 3

White Electronic Designs Corp. reserves the right to change products or speciﬁ cations without notice.

COMMANDS

The Truth Table provides a quick reference of available

com mands. This is followed by a written de scrip tion of

each command.

DESELECT

The DESELECT function (CS# High) prevents new

com mands from be ing ex e cut ed by the DDR SDRAM.

The SDRAM is ef fec tive ly de se lect ed. Op er a tions already

in progress are not af fect ed.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform

a NOP to the selected DDR SDRAM (CS# is LOW while

RAS#, CAS#, and WE# are high). This prevents unwanted

commands from being registered during idle or wait states.

Operations already in progress are not affected.

LOAD MODE REGISTER

The Mode Registers are loaded via inputs A0-12. The

LOAD MODE REGISTER command can only be issued

when all banks are idle, and a subsequent executable

com mand cannot be issued until tMRD is met.

ACTIVE

The ACTIVE command is used to open (or activate) a

row in a particular bank for a subsequent access. The

value on the BA0, BA1 inputs se lects the bank, and the

address pro vid ed on inputs A0-12 selects the row. This row

remains active (or open) for ac cess es until a PRECHARGE

com mand is issued to that bank. A PRECHARGE

command must be issued before opening a different row

in the same bank.

READ

The READ command is used to initiate a burst read

access to an active row. The value on the BA0, BA1 inputs

selects the bank, and the address provided on inputs A0-9

se lects the starting column location. The value on input

A10 de ter mines whether or not AUTO PRECHARGE is

used. If AUTO PRECHARGE is selected, the row being

accessed will be precharged at the end of the READ burst;

if AUTO PRECHARGE is not selected, the row will remain

open for subsequent ac cess es.

WRITE

The WRITE command is used to initiate a burst write

access to an active row. The value on the BA0, BA1 inputs

selects the bank, and the address provided on inputs A0-9

se lects the starting column location. The value on input A10

de ter mines whether or not AUTO PRECHARGE is used. If

AUTO PRECHARGE is selected, the row being accessed

will be precharged at the end of the WRITE burst; if AUTO

PRECHARGE is not selected, the row will remain open

for sub se quent accesses. Input data appearing on the DQ

is written to the memory array subject to the DQM input

logic level ap pear ing co in ci dent with the data. If a given

DQM signal is reg is tered LOW, the cor re spond ing data

will be written to mem o ry; if the DQM signal is reg is tered

HIGH, the cor re spond ing data inputs will be ignored, and a

WRITE will not be executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the

open row in a particular bank or the open row in all banks.

The bank(s) will be available for a subsequent row access

a speciﬁ ed time (tRP) after the PRECHARGE command is

is sued. Except in the case of concurrent auto precharge,

where a READ or WRITE command to a different bank is

allowed as long as it does not interrupt the data transfer

in the current bank and does not violate any other timing

pa ram e ters. Input A10 de ter mines wheth er one or all

banks are to be precharged, and in the case where only

one bank is to be precharged, in puts BA0, BA1 select the

bank. Oth er wise BA0, BA1 are treated as “Don’t Care.”

Once a bank has been precharged, it is in the idle state and

must be ac ti vat ed pri or to any READ or WRITE commands

being is sued to that bank. A PRECHARGE com mand will

be treat ed as a NOP if there is no open row in that bank

(idle state), or if the previously open row is already in the

pro cess of precharging.

AUTO PRECHARGE

AUTO PRECHARGE is a feature which performs the

same in di vid u al-bank PRECHARGE function de scribed

above, but with out re quir ing an explicit command. This is

ac com plished by using A10 to enable AUTO PRECHARGE

in conjunction with a spe ciﬁ c READ or WRITE command.

A precharge of the bank/row that is ad dressed with the

READ or WRITE com mand is au to mat i cal ly performed

upon com ple tion of the READ or WRITE burst. AUTO

PRECHARGE is non per sis tent in that it is either en abled

W3E64M72S-XSBX

8White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

September 2007

Rev. 3

White Electronic Designs Corp. reserves the right to change products or speciﬁ cations without notice.

TABLE 1 – BURST DEFINITION

Burst

Length Starting Column

Address Order of Accesses With in a Burst

Type = Sequential Type = In ter leaved

0 0-1 0-1

1 1-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2

1 0 2-3-0-1 2-3-0-1

1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

NOTES:

1. For a burst length of two, A1-Ai select two-data-element block; A0

selects the starting column within the block.

2. For a burst length of four, A2-Ai select four-data-element block; A0-1

select the starting column within the block.

3. For a burst length of eight, A3-Ai select eight-data-element block;

A0-2 select the starting column within the block.

4. Whenever a boundary of the block is reached within a given

sequence above, the following access wraps within the block.

FIGURE 3 – MODE REGISTER DEFINITION

M3 = 0

Reserved

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

0 0 Valid

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

Burst LengthCAS Latency BT

Mode Register (Mx)

Address Bus

M6-M0

M8 M7

Operating Mode

* M14 and M13

(BA0 and BA1 must be

"0, 0" to select

the base mode register

(vs. the extended

mode register).

Reserved Reserved

Reserved

M10

M11

M12

14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

or dis abled for each in di vid u al READ or WRITE command.

The device sup ports concurrent auto precharge if the

com mand to the oth er bank does not in ter rupt the data

transfer to the current bank.

AUTO PRECHARGE ensures that the precharge is

initiated at the earliest valid stage within a burst. This

“earliest valid stage” is determined as if an explicit

precharge command was is sued at the earliest possible

time, without violating tRAS (MIN).The user must not is sue

an oth er com mand to the same bank until the precharge

time (tRP) is com plet ed.

BURST TERMINATE

The BURST TERMINATE command is used to truncate

READ bursts (with auto precharge disabled). The most

recently registered READ command prior to the BURST

TERMINATE command will be truncated. The open page

which the READ burst was terminated from remains

open.

AUTO REFRESH

AUTO REFRESH is used during normal op er a tion of the

DDR SDRAM and is analogous to CAS-BEFORE-RAS

(CBR) RE FRESH in con ven tion al DRAMs. This com mand

is non per sis tent, so it must be issued each time a refresh

is required. All banks must be idle before an AUTO

REFRESH command is issued.

The addressing is generated by the internal refresh

con trol ler. This makes the address bits “Don’t Care”

during an AUTO RE FRESH command. Each DDR SDRAM

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COMMAND READ NOP NOP NOP

CL = 2.5

DON'T CARE

TRANSITIONING DATA

DQS

T0 T1 T2 T2n T3 T3n

COMMAND READ NOP NOP NOP

CL = 2

DQS

CLK

T0 T1 T2 T2n T3 T3n

Burst Length = 4 in the cases shown

Shown with nominal tAC and nominal tDSDQ

DATA

CLK

FIGURE 4 – CAS LATENCY FIGURE 5 – EXTENDED MODE REGISTER

DEFINITION

DLL

Enable

Disable

A9A7A6A5A4A3

A8A2A1A0

Extended Mode

Address Bus

A10

A11

BA0

BA1

Drive Strength

Normal

Reserved

Operating Mode

Reserved

E1, E0

Valid

E12

E10

A12

E11

1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)

2. The QFC# function is not supported.

14131211109876543210

DLL

Operating Mode

requires AUTO RE FRESH cycles at an average interval

of 7.8125μs (maximum).

To allow for improved efficiency in scheduling and

switch ing between tasks, some ﬂ exibility in the absolute

refresh interval is provided. A maximum of eight AUTO

REFRESH commands can be posted to any given DDR

SDRAM, mean ing that the maximum absolute interval

between any AUTO REFRESH command and the next

AUTO REFRESH command is 9 x 7.8125μs (70.3μs). This

maximum absolute interval is to allow future support for

DLL updates internal to the DDR SDRAM to be restricted

to AUTO REFRESH cycles, without allowing excessive

drift in tAC between updates.

Although not a JEDEC requirement, to provide for future

func tion al ity features, CKE must be active (High) during

the AUTO REFRESH period. The AUTO REFRESH period

begins when the AUTO REFRESH command is registered

and ends tRFC later.

SELF REFRESH*

The SELF REFRESH command can be used to retain

data in the DDR SDRAM, even if the rest of the system is

powered down. When in the self refresh mode, the DDR

SDRAM re tains data with out external clocking. The SELF

RE FRESH com mand is ini ti at ed like an AUTO REFRESH

com mand except CKE is dis abled (LOW). The DLL is

automatically disabled upon entering SELF REFRESH and

is automatically enabled upon exiting SELF REFRESH (A

DLL reset and 200 clock cycles must then oc cur before a

READ command can be issued). Input sig nals except CKE

are “Don’t Care” during SELF REFRESH. VREF voltage is

also required for the full duration of SELF REFRESH.

The procedure for exiting self refresh requires a sequence

of commands. First, CK and CK# must be stable prior

to CKE going back HIGH. Once CKE is HIGH, the DDR

SDRAM must have NOP commands is sued for tXSNR,

be cause time is required for the com ple tion of any internal

refresh in progress.

A simple algorithm for meeting both refresh and DLL

re quire ments is to apply NOPs for tXSNR time, then a DLL

Reset and NOPs for 200 additional clock cycles before

applying any other command.

* Self refresh available in commercial and industrial temperatures only.

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NOTES:

1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0-12 deﬁ ne the op-code to be written to the selected Mode Register. BA0, BA1

select either the mode register (0, 0) or the extended mode register (1, 0).

3. A0-12 provide row address, and BA0, BA1 provide bank address.

4. A0-9 provide column address; A10 HIGH enables the auto precharge feature (non

persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide

bank address.

5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks

precharged and BA0, BA1 are “Don’t Care.”

TRUTH TABLE – COMMANDS (NOTE 1)

NAME (FUNCTION) CS# RAS# CAS# WE# ADDR

DESELECT (NOP) (9) H X X X X

NO OPERATION (NOP) (9) L H H H X

ACTIVE (Select bank and activate row) ( 3) L L H H Bank/Row

READ (Select bank and column, and start READ burst) (4) L H L H Bank/Col

WRITE (Select bank and column, and start WRITE burst) (4) L H L L Bank/Col

BURST TERMINATE (8) L H H L X

PRECHARGE (Deactivate row in bank or banks) ( 5) L L H L Code

AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7) L L L H X

LOAD MODE REGISTER (2) L L L L Op-Code

TRUTH TABLE – DM OPERATION

NAME (FUNCTION) DM DQs

WRITE ENABLE (10) L Valid

WRITE INHIBIT (10) H X

6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is

LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t

Care” except for CKE.

8. Applies only to read bursts with auto precharge disabled; this command is

undeﬁ ned (and should not be used) for READ bursts with auto precharge enabled

and for WRITE bursts.

9. DESELECT and NOP are functionally interchangeable.

10. Used to mask write data; provided coincident with the corresponding data.

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ABSOLUTE MAXIMUM RATINGS

Parameter Unit

Voltage on VCC, VCCQ Supply relative to Vss -1 to 3.6 V

Voltage on I/O pins relative to Vss -0.5V to VCCQ +0.5V V

Operating Temperature TA (Mil) -55 to +125 °C

Operating Temperature TA (Ind) -40 to +85 °C

Storage Temperature, Plastic -55 to +125 °C

Maximum Junction Temperature 125 °C

NOTE: Stress greater than those listed under "Absolute Maximum Ratings" may cause per ma nent damage to the device. This is a stress rating only and func tion al op er a tion of

the device at these or any other conditions greater than those in di cat ed in the operational sections of this speciﬁ cation is not implied. Exposure to ab so lute maximum rating

con di tions for extended periods may affect reliability.

CAPACITANCE (NOTE 13)

Parameter Symbol Max Unit

Input Capacitance: CK/CK# CI1 8 pF

Addresses, BA0-1 Input Capacitance CA 38 pF

Input Capacitance: All other input-only pins CI2 9pF

Input/Output Capacitance: I/Os CIO 8 pF

BGA THERMAL RESISTANCE

Description Symbol Max Units Notes

Junction to Ambient (No Airﬂ ow) Theta JA 10.1 °C/W 1

Junction to Ball Theta JB 10.6 °C/W 1

Junction to Case (Top) Theta JC 2.5 °C/W 1

Refer to "PBGA Thermal Resistance Correlation" (Application Note) at www.whiteedc.com in the application notes section for modeling conditions.

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DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1-5, 16)

VCC, VCCQ = +2.5V ± 0.2V; -55°C ≤ TA ≥ +125°C

Parameter/Condition Symbol Min Max Units

Supply Voltage (36, 41) VCC 2.3 2.7 V

I/O Supply Voltage (36, 41, 44) VCCQ 2.3 2.7 V

Input Leakage Current: Any input 0V ≤ VIN ≤ VCC (All other pins not under test = 0V) II -2 2 μA

Input Leakage Address Current (All other pins not under test = 0V) II -18 18 μA

Output Leakage Current: I/Os are disabled; 0V ≤ VOUT ≤ VCCQ IOZ -5 5 μA

Output Levels: Full drive option (37, 39)

High Current (VOUT = VCCQ - 0.373V, minimum VREF, minimum VTT)

Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)

IOH -12 - mA

IOL 12 - mA

I/O Reference Voltage (6,44) VREF 0.49 x VCCQ 0.51 x VCCQ V

I/O Termination Voltage (7, 44) VTT VREF - 0.04 VREF + 0.04 V

AC INPUT OPERATING CONDITIONS

VCC, VCCQ = +2.5V ± 0.2V; -55°C £ TA £ +125°C

Parameter/Condition Symbol Min Max Units

Input High (Logic 1) Voltage VIH V

REF +0.310 — V

Input Low (Logic 0) Voltage VIL —V

REF -0.310 V

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Parameter/Condition

MAX

Symbol 333Mbs 250MHz

266MHz 200MHz Units

OPERATING CURRENT: One bank; Active-Precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS

inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles; (22,

47)

ICC0 1,170 1,170 1,035 mA

OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN);

IOUT = 0mA; Address and control inputs changing once per clock cycle (22, 47)

ICC1 1,440 1,440 1,305 mA

PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK

(MIN); CKE = LOW; (23, 32, 49)

ICC2P 45 45 45 mA

IDLE STANDBY CURRENT: CS = HIGH; All banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other

control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM (50)

ICC2F 405 405 360 mA

ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN);

CKE = LOW (23, 32, 49)

ICC3P 315 315 270 mA

ACTIVE STANDBY CURRENT: CS = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS

(MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other

control inputs changing once per clock cycle (22)

ICC3N 450 450 405 mA

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control

inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA (22, 47)

ICC4R 1,485 1,485 1,305 mA

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control

inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock

cycle (22)

ICC4W 1,755 1,440 1,215 mA

AUTO REFRESH CURRENT tREFC = tRC (MIN) (49) ICC5 2,610 2,610 2,610 mA

tREFC = 7.8125μs (27, 49) ICC5A 90 90 90 mA

SELF REFRESH CURRENT: CKE 0.2V Standard (11) ICC6 45 45 45 mA

OPERATING CURRENT: Four bank interleaving READs (BL=4) with auto precharge, tRC =tRC (MIN); tCK =

tCK (MIN); Address and control inputs change only during Active READ or WRITE commands. (22, 48)

ICC7 3,645 3,645 3,645 mA

ICC SPECIFICATIONS AND CONDITIONS (NOTES 1-5, 10, 12, 14, 46)

VCC, VCCQ = +2.5V ± 0.2V; -55°C ≤ TA ≥ +125°C

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333 MHz CL 3 (53)

266 MHz CL2.5 266 MHz CL 2.5

200 CL 2 (53) 250 MHz CL2.5

200 MHz CL2 200 MHz CL2.5

150 MHz CL2

Parameter Symbol Min Max Min Max Min Max Min Max Units

Access window of DQs from CK/CK# tAC -0.70 +0.70 -0.75 +0.75 -0.8 +0.8 -0.8 +0.8 ns

CK high-level width (30) tCH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK

CK low-level width (30) tCL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 tCK

Clock cycle time

CL = 3 (45, 51) tCK (3) 613 ns

CL = 2.5 (45, 51) tCK (2.5) 7.5 13 7.5 13 8 13 10 13 ns

CL = 2 (45, 51) tCK (2) 10 13 10 13 10 13 13 15 ns

DQ and DM input hold time relative to DQS (26, 31) tDH 0.45 0.5 0.6 0.6 ns

DQ and DM input setup time relative to DQS (26, 31) tDS 0.45 0.5 0.6 0.6 ns

DQ and DM input pulse width (for each input) (31) tDIPW 1.75 1.75 2 2 ns

Access window of DQS from CK/CK# tDQSCK -0.6 +0.6 -0.75 +0.75 -0.8 +0.8 -0.8 +0.8 ns

DQS input high pulse width tDQSH 0.35 0.35 0.35 0.35 tCK

DQS input low pulse width tDQSL 0.35 0.35 0.35 0.35 tCK

DQS-DQ skew, DQS to last DQ valid, per group, per access (25, 26) tDQSQ 0.45 0.5 0.6 0.6 ns

Write command to ﬁ rst DQS latching transition tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK

DQS falling edge to CK rising - setup time tDSS 0.2 0.2 0.2 0.2 tCK

DQS falling edge from CK rising - hold time tDSH 0.2 0.2 0.2 0.2 tCK

Half clock period (34) tHP tCH,tCL tCH,tCL tCH,tCL tCH,tCL ns

Data-out high-impedance window from CK/CK# (18, 42) tHZ +0.70 +0.75 +0.8 +0.8 ns

Data-out low-impedance window from CK/CK# (18, 42) tLZ -0.70 -0.75 -0.8 -0.8 ns

Address and control input hold time (fast slew rate) tIHF0.75 0.90 1.1 1.1 ns

Address and control input setup time (fast slew rate) tISF0.75 0.90 1.1 1.1 ns

Address and control input hold time (slow slew rate) (14) tIHS 0.8 1 1.1 1.1 ns

Address and control input setup time (slow slew rate) (14) tISS0.8 1 1.1 1.1 ns

LOAD MODE REGISTER command cycle time tMRD 12 15 16 16 ns

DQ-DQS hold, DQS to ﬁ rst DQ to go non-valid, per access (25, 26) tQH tHP-tQHS tHP-tQHS tHP-tQHS tHP-tQHS ns

Data hold skew factor tQHS 0.55 0.75 1 1 ns

ACTIVE to PRECHARGE command (35) tRAS 42 70,000 40 120,000 40 120,000 40 120,000 ns

ACTIVE to READ with Auto precharge command tRAP 15 20 20 20 ns

ACTIVE to ACTIVE/AUTO REFRESH command period tRC 60 65 70 70 ns

AUTO REFRESH command period (49) tRFC 72 75 80 80 ns

ACTIVE to READ or WRITE delay tRCD 15 20 20 20 ns

PRECHARGE command period tRP 15 20 20 20 ns

DQS read preamble (43) tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCK

DQS read postamble (43) tRPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK

ACTIVE bank a to ACTIVE bank b command tRRD 12 15 15 15 ns

DQS write preamble tWPRE 0.25 0.25 0.25 0.25 tCK

DQS write preamble setup time (20, 21) tWPRES 0000ns

DQS write postamble (19) tWPST 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK

Write recovery time tWR 15 15 15 15 ns

Internal WRITE to READ command delay tWTR 1111t

Data valid output window (25) na tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ tQH - tDQSQ ns

REFRESH to REFRESH command interval (23) (Commercial & Industrial only) tREFC 70.3 70.3 70.3 70.3 μs

REFRESH to REFRESH command interval (23) (Military temperature only)* tREFC 35 35 35 35 μs

Average periodic refresh interval (23) (Commercial & Industrial only) tREFI 7.8 7.8 7.8 7.8 μs

Average periodic refresh interval (23) (Military temperature only)* tREFI 3.9 3.9 3.9 3.9 μs

Terminating voltage delay to VDD tVTD 0000ns

Exit SELF REFRESH to non-READ command tXSNR 75 75 80 80 ns

Exit SELF REFRESH to READ command tXSRD 200 200 200 200 tCK

* Self refresh available in commercial and industrial temperatures only.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS

Notes 1-5, 14-17, 33

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NOTES:

1. All voltages referenced to VSS.

2. Tests for AC timing, ICC, and electrical AC and DC characteristics may be

conducted at nominal reference/supply voltage levels, but the related speciﬁ cations

and device operation are guaranteed for the full voltage range speciﬁ ed.

3. Outputs measured with equivalent load:

4. AC timing and ICC tests may use a VIL-to-VIH swing of up to 1.5V in the test

environment, but input timing is still referenced to VREF (or to the crossing point for

CK/CK#), and parameter speciﬁ cations are guaranteed for the speciﬁ ed AC input

levels under normal use conditions. The minimum slew rate for the input signals

used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC).

5. The AC and DC input level speciﬁ cations are as deﬁ ned in the SSTL_2 Standard

(i.e., the receiver will effectively switch as a result of the signal crossing the AC

input level, and will remain in that state as long as the signal does not ring back

above [below] the DC input LOW [HIGH] level).

6. VREF is expected to equal VCCQ/2 of the transmitting device and to track variations

in the DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may

not exceed ±2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed ±25mV

for DC error and an additional ±25mV for AC noise. This measurement is to be

taken at the nearest VREF by-pass capacitor.

7. VTT is not applied directly to the device. VTT is a system supply for signal

termination resistors, is expected to be set equal to VREF and must track variations

in the DC level of VREF.

8. VID is the magnitude of the difference between the input level on CK and the input

level on CK#.

9. The value of VIX and VMP are expected to equal VCCQ/2 of the transmitting device

and must track variations in the DC level of the same.

10. ICC is dependent on output loading and cycle rates. Speciﬁ ed values are obtained

with minimum cycle time with the outputs open.

11. Enables on-chip refresh and address counters.

12. ICC speciﬁ cations are tested after the device is properly initialized, and is averaged

at the deﬁ ned cycle rate.

13. This parameter is not tested but guaranteed by design. tA = 25°C, F= 1 MHz

14. For slew rates less than 1V/ns and greater than or equal to 0.5 V.ns. If the slew

rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50 ps per

each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that

is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain.

15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at

which CK# and CK# cross; the input reference level for signals other than CK/CK#

is VREF.

16. Inputs are not recognized as valid until VREF stabilizes. Once initialized, including

SELF REFRESH mode, VREF must be powered within speciﬁ ed range. Exception:

during the period before VREF stabilizes, CKE £ 0.3 x VCCQ is recognized as LOW.

17. The output timing reference level, as measured at the timing reference point

indicated in Note 3, is VTT.

18. tHZ and tLZ transitions occur in the same access time windows as valid data

transitions. These parameters are not referenced to a speciﬁ c voltage level, but

specify when the device output is no longer driving (HZ) or begins driving (LZ).

19. The intent of the Don't Care state after completion of the postamble is the DQS-

driven signal should either be high, low, or high-Z and that any signal transition

within the input switching region must follow valid input requirements. That is, if

DQS transitions high (above VIHDC(MIN) then it must not transition low (below

VIHDC) prior to tDQSH(MIN).

20. This is not a device limit. The device will operate with a negative value, but system

performance could be degraded due to bus turnaround.

21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE

command. The case shown (DQS going from High-Z to logic LOW) applies when

no WRITEs were previously in progress on the bus. If a previous WRITE was in

progress, DQS could be HIGH during this time, depending on tDQSS.

22. MIN (tRC or tRFC) for ICC measurements is the smallest multiple of tCK that meets

the minimum absolute value for the respective parameter. tRAS (MAX) for ICC

measurements is the largest multiple of tCK that meets the maximum absolute

value for tRAS.

23. The refresh period 64ms. (32ms for Military grade) This equates to an average

refresh rate of 7.8125μs. However, an AUTO REFRESH command must be

asserted at least once every 70.3μs; (35μs for Military grade) burst refreshing or

posting by the DRAM controller greater than eight refresh cycles is not allowed.

24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this

maximum amount for any given device.

25. The valid data window is derived by achieving other speciﬁ cations - tHP (tCK/2),

tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional

with the clock duty cycle and a practical data valid window can be derived. The

clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain

when operating beyond a 45/55 ratio. The data valid window derating curves are

provided below for duty cycles ranging between 50/50 and 45/55.

160

140

120

100

0.0 0.5 1.0 1.5 2.0 2.5

OUT

(V)

OUT

(mA)

Maximum

Nominal high

Nominal low

Minimum

50Ω

Reference

Point

30pF

Output

(VOUT)

VTT

FIGURE A FULL DRIVE PULL-DOWN

CHARACTERISTICS FIGURE B FULL DRIVE PULL-UP

CHARACTERISTICS

-20

-40

-60

-80

-100

-120

-140

-160

-180

-200

0.0 0.5 1.0 1.5 2.0 2.5

CCQ -

OUT

(V)

OUT

(mA)

Maximum

Nominal high

Nominal low

Minimum

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26. Referenced to each output group: DQSL with DQ0-DQ7; and DQSH with DQ8-

DQ15 of each chip.

27. This limit is actually a nominal value and does not result in a fail value. CKE is

HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e.,

during standby).

28. To maintain a valid level, the transitioning edge of the input must:

a) Sustain a constant slew rate from the current AC level through to the target AC

level, VIL(AC) or VIH(AC).

b) Reach at least the target AC level.

c) After the AC target level is reached, continue to maintain at least the target DC

level, VIL(DC) or VIH(DC).

29. The Input capacitance per pin group will not differ by more than this maximum

amount for any given device.

30. CK and CK# input slew rate must be £ 1V/ns (£2V/ns differentially).

31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the

DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be

added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rate exceeds

4V/ns, functionality is uncertain.

32. VCC must not vary more than 4% if CKE is not active while any bank is active.

33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to

vary by the same amount.

34. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device

CK and CK# inputs, collectively during bank active.

35. READs and WRITEs with auto precharge are not allowed to be issued until

tRAS(MIN) can be satisﬁ ed prior to the internal precharge command being issued.

36. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or

2.9 volts, whichever is less. Any negative glitch must be less than

1/3 of the clock cycle and not exceed either -300mV or 2.2 volts, whichever is more

positive. The average cannot be below the 2.5V minimum.

37. Normal Output Drive Curves:

a) The full variation in driver pull-down current from minimum to maximum

process, temperature and voltage will lie within the outer bounding lines of the

V-I curve of Figure A.

b) The variation in driver pull-down current within nominal limits of voltage and

temperature is expected, but not guaranteed, to lie within the inner bounding

lines of the V-I curve of Figure A.

c) The full variation in driver pull-up current from minimum to maximum process,

temperature and voltage will lie within the outer bounding lines of the V-I curve

of Figure B.

d) The variation in driver pull-up current within nominal limits of voltage and

temperature is expected, but not guaranteed, to lie within the inner bounding

lines of the V-I curve of Figure B.

e) The full variation in the ratio of the maximum to minimum pull-up and pull-down

current should be between .71 and 1.4, for device drain-to-source voltages from

0.1V to 1.0 Volt, and at the same voltage and temperature.

f) The full variation in the ratio of the nominal pull-up to pull-down current should

be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 Volt.

38. Reduced Output Drive Curves:

a) The full variation in driver pull-down current from minimum to maximum

process, temperature and voltage will lie within the outer bounding lines of the

V-I curve of Figure C.

b) The variation in driver pull-down current within nominal limits of voltage and

temperature is expected, but not guaranteed, to lie within the inner bounding

lines of the V-I curve of Figure C.

c) The full variation in driver pull-up current from minimum to maximum process,

temperature and voltage will lie within the outer bounding lines of the V-I curve

of Figure D.

d) The variation in driver pull-up current within nominal limits of voltage and

temperature is expected, but not guaranteed, to lie within the inner bounding

lines of the V-I curve of Figure D.

e) The full variation in the ratio of the maximum to minimum pull-up and pull-down

current should be between .71 and 1.4, for device drain-to-source voltages from

0.1V to 1.0 V, and at the same voltage and temperature.

f) The full variation in the ratio of the nominal pull-up to pull-down current should

be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 V.

39. The voltage levels used are derived from a minimum VCC level and the referenced

test load. In practice, the voltage levels obtained from a properly terminated bus

will provide signiﬁ cantly different voltage values.

40. VIH overshoot: VIH(MAX) = VCCQ+1.5V for a pulse width £ 3ns and the pulse width

can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a

pulse width £ 3ns and the pulse width cannot be greater than 1/3 of the cycle rate.

41. VCC and VCCQ must track each other.

42. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will

prevail over tDQSCK (MIN) + tRPRE (MAX) condition.

43. tRPST end point and tRPRE begin point are not referenced to a speciﬁ c voltage level

but specify when the device output is no longer driving (tRPST), or begins driving

(tRPRE).

44. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V.

Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ are 0

volts, provided a minimum of 42 ohms of series resistance is used between the VTT

supply and the input pin.

45. The current part operates below the slowest JEDEC operating frequency of 83 MHz.

As such, future die may not reﬂ ect this option.

46. When an input signal is HIGH or LOW, it is deﬁ ned as a steady state logic HIGH or

LOW.

47. Random addressing changing: 50% of data changing at every transfer.

48. Random addressing changing: 100% of data changing at every transfer.

49. CKE must be active (high) during the entire time a refresh command is executed.

That is, from the time the AUTO REFRESH command is registered, CKE must be

active at each rising clock edge, until tRFC has been satisﬁ ed.

50. ICC2N speciﬁ es the DQ, DQS, and DQM to be driven to a valid high or low logic

level. ICC2Q is similar to ICC2F except ICC2Q speciﬁ es the address and control inputs

to remain stable. Although ICC2F, ICC2N, and ICC2Q are similar, ICC2F is “worst case.”

51. Whenever the operating frequency is altered, not including jitter, the DLL is

required to be reset followed by 200 clock cycles before any READ command.

52. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20

MHz. Any noise above 20 MHz at the DRAM generated from any source other than

that of the DRAM itself may not exceed the DC coltage range of 2.6V ± 100mV.

53. For 333Mbs operation of Industrial temperature CL = 2.5, at Military temperature

CL = 3.

W3E64M72S-XSBX

17 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

September 2007

Rev. 3

White Electronic Designs Corp. reserves the right to change products or speciﬁ cations without notice.

ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES

BOTTOM VIEW

PACKAGE DIMENSION: 219 PLASTIC BALL GRID ARRAY (PBGA)

32.1 (1.264) MAX

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

25.1 (0.988)

MAX

19.05 (0.750)

NOM

1.27 (0.050)

NOM

19.05 (0.750) NOM

2.96 (0.116)

MAX

0.61

(0.024)

NOM

219 x Ø 0.762 (0.030) NOM

W3E64M72S-XSBX

18 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

September 2007

Rev. 3

White Electronic Designs Corp. reserves the right to change products or speciﬁ cations without notice.

ORDERING INFORMATION

WHITE ELECTRONIC DESIGNS CORP.

DDR SDRAM

CONFIGURATION, 64M x 72

2.5V Power Supply

DATA RATE (Mbs)

200 = 200Mbs

250 = 250Mbs

266 = 266Mbs

333 = 333Mbs

PACKAGE:

SB = 219 Plastic Ball Grid Array (PBGA)

DEVICE GRADE:

M = Military -55°C to +125°C

I = In dus tri al -40°C to +85°C

C = Com mer cial 0°C to +70°C

W 3 E 64M 72 S - XXX SB X

W3E64M72S-XSBX

19 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

White Electronic Designs

September 2007

Rev. 3

White Electronic Designs Corp. reserves the right to change products or speciﬁ cations without notice.

Document Title

64M x 72 DDR SDRAM 219 PBGA Multi-Chip Package

Revision History

Rev # History Release Date Status

Rev 0 Initial Release June 2005 Advanced

Rev 1 Changes (All pages)

1.1 Change status to preliminary

1.2 Change part number package disignation to 'SB'

May 2006 Preliminary

Rev 2 Changes (All Pages)

2.1 Change status to ﬁ nal

2.2 Update capacitance values

2.3 Clarify CAS Latency values of Table 2 for 333Mbs

operation

September 2006 Final

Rev 3 Changes (Pg. 1, 11, 12, 19)

3.1 Remove programmable IOL/IOH reference

3.2 Add thermal resistance data

3.3 Correct VIH and VIL voltages

September 200 Final