Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
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XRK49911
3.3V HIGH-SPEED (110 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
JUNE 2005 REV. 1.0.0
FUNCTIONAL DESCRIPTION
The XRK49911 is a 3.3V High-Speed Low-Voltage
Programmable Skew Clock Buffer. It is intended for
high-performance computer systems and offers user
selectable control over system clock functions to
optimize timing. Eight outputs, arranged in four
banks, can each drive 50Ω terminated transmission
lines while delivering minimal and specified output
skews and full-swing Low Voltage TTL logic levels.
Each bank (two outputs per bank) can be individually
selected for one of nine delay or function
configurations through two dedicated tri-level inputs.
These outputs are able to lead or lag the CLKIN input
reference clock by up to 6 time units from their
nominal “zero” skew position. The integrated PLL
allows external load and transmission line delay
effects to be canceled achieving zero delay capability.
Combining the zero delay capability with the
selectable output skew functions, output-to-output
delays of up to ±12 time units can be created.
The XRK49911’s divide functions (divide-by-two and
divide-by-four) allow distribution of a low-frequency
clock that can be multiplied by two or four at the clock
destination. This feature facilitates clock distribution
while allowing maximum system clock flexibility.
FEATURES
•3.75- to 110-MHz output operation
•All output pair skew <100 ps typical
•Three skew grades
-2 : tSKEW0<250ps
-5 : tSKEW0<500ps
-7 : tSKEW0<700ps
•Selectable output functions
Skew adjustments of +/- 6tU (up to 18 ns)
Inverted and non-inverted
Operation at 1/2 and 1/4 input frequency
Operation at 2x and 4x input frequency
•Cycle-Cycle Jitter
< 25 ps (rms)
< 200 ps (pk-pk)
•Zero input-to-output delay
•50% duty-cycle outputs
•LVTTL outputs drive 50Ω terminated lines
•Operates from a single 3.3V supply
•32-pin PLCC package
•Green packaging
•Lead free lead frame available
FIGURE 1. BLOCK DIAGRAM OF THE XRK49911
PLL
CLKIN
FB_ IN
FSEL*
PLL_BYPASS*
Bank “SKEW”
Control
QA0
QA1
QB0
QB1
QC0
QC1
QD0
QD1
SELA[1:0]*
SELB[1:0]*
SELC[1:0]*
SELD[1:0]*
* Tri-Level inputs
L
M
H
Ref
Feedback
2
2
2
2
XRK49911
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PRODUCT ORDERING INFORMATION
PRODUCT NUMBER ACCURACY TEMPERATURE RANGE LEAD FREE
XRK49911IJ-2 250 ps -40°C to +85°C
XRK49911CJ-2 250 ps 0°C to +70°C
XRK49911IJ-2F 250 ps -40°C to +85°C √
XRK49911CJ-2F 250 ps 0°C to +70°C √
XRK49911IJ-5 500 ps -40°C to +85°C
XRK49911CJ-5 500 ps 0°C to +70°C
XRK49911CJ-7 750 ps 0°C to +70°C
XRK49911IJ-5F 500 ps -40°C to +85°C √
XRK49911CJ-5F 500 ps 0°C to +70°C √
XRK49911CJ-7F 750 ps 0°C to +70°C √
FIGURE 2. PIN OUT OF THE XRK49911
QC1
QC0
VCCN
FB_IN
VCCN
QB1
QB0
XRK49911
SELC0
FSEL
VCCQ
CLKIN
GND
PLL_BYPASS
SELB1
SELC1
SELD0
SELD1
VCCQ
VCCN
QD1
QDO
GND
GND
5
6
7
8
9
10
11
12
13
SELB0
GND
SELA1
SELA0
VCCN
QA0
QA1
GND
GND
29
28
27
26
25
24
23
22
21
14 15 16 17 18 19 20
4 3 2 1 323130
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3.3V HIGH-SPEED (110 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
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PIN DESCRIPTIONS
PIN NAME PIN # TYPE DESCRIPTION
CLKIN 1 I Reference clock input.
FB_IN 17 IPLL’s feedback input. (Normally connected to one of the eight outputs)
FSEL 3 I Tri-level frequency range select. See Table 1
PLL_BYPASS 31 ITri-level select. See PLL_BYPASS section.
SELA0
SELA1
26
27
ITri-level select inputs for Bank A outputs (QA0, QA1). See Table 2.
SELB0
SELB1
29
30
ITri-level select inputs for Bank B outputs (QB0, QB1). See Table 2.
SELC0
SELC1
4
5
ITri-level select inputs for Bank C outputs (QC0, QC1). See Table 2.
SELD0
SELD1
6
7
ITri-level select inputs for Bank D outputs (QD0, QD1). See Table 2.
QA0
QA1
24
23
OBank A output pair. See Table 2.
QB0
QB1
20
19
OBank B output pair. See Table 2.
QC0
QC1
15
14
OBank C output pair. See Table 2.
QD0
QD1
11
10
OBank D output pair. See Table 2.
VCCN 9
16
18
25
PWR Power supply for output drivers.
VCCQ 2
8
PWR Power supply for internal circuitry.
GND 12
13
21
22
28
32
PWR Ground.
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SKEW SELECT CONTROL
The skew select control consists of four independent banks. Each bank has two low-skew, high-fanout drivers
(Qx0, Qx1), and two corresponding tri-level function select (SELx0, SELx1) inputs. The nine possible output
states for each bank are shown in Table 2 as determined by each bank’s select inputs. All timing
measurements are made with respect to the CLKIN input with the output connected to the FB_IN input
configured for 0 tU operation.
NOTES:
1. For all tri-level (three-state) inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and
MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2.
2. The level to be set on FSEL is determined by the “normal” operating frequency (fNOM) of the PLL. Nominal
frequency (fNOM) always appears at QA0 and the other outputs when they are operated in their undivided modes
(see Table 2). The frequency appearing at the CLKIN and FB_IN inputs will be fNOM when the output connected to
FB_IN is undivided. The frequency of the CLKIN and FB_IN inputs will be fNOM ÷ 2 or fNOM ÷ 4 when the part is
configured for a frequency multiplication.
3. When the FSEL pin is selected HIGH, the CLKIN input must not transition upon power-up until VCC has reached
2.8V.
TABLE 1: FREQUENCY RANGE SELECT AND tU CALCULATION [1]
fNOM (MHZ)tU = 1 / (fNOM X N) APPROXIMATE
FREQUENCY (MHZ) AT
WHICH tU = 1.0ns
FSEL[2] MIN MAX WHERE N =
LOW 15 30 44 22.7
MID 25 50 26 38.5
HIGH[3] 40 110 16 62.5
TABLE 2: PROGRAMMABLE SKEW CONFIGURATIONS [1]
FUNCTION SELECT INPUTS OUTPUT FUNCTIONS
SELX1SELX0QA[1:0], QB[1:0] QC[1:0] QD[1:0]
LOW LOW -4tU÷ 2 ÷ 2
LOW MID -3tU-6tU-6tU
LOW HIGH -2tU-4tU-4tU
MID LOW -1tU-2tU-2tU
MID MID 0tU0tU0tU
MID HIGH +1tU+2tU+2tU
HIGH LOW +2tU+4tU+4tU
HIGH MID +3tU+6tU+6tU
HIGH HIGH +4tU÷ 4 Inverted
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PLL_BYPASS
The PLL_BYPASS input is a tri-level input. In normal system operation, this pin is connected to ground.
In normal operation (tied LOW) all outputs will function based only on the connection of their own function
select inputs (SELx[1:0]) and the waveform characteristics of the PLL.
If the PLL_BYPASS input is forced to its MID or HIGH state the device will operate in PLL bypass mode, with
the phase locked loop disconnected, and CLKIN waveforms will directly control all outputs. Relative output to
output timing is controlled by the SELx[1:0], the same as in normal mode.
FIGURE 3. TYPICAL OUTPUTS WITH FB_IN CONNECTED TO A ZERO-SKEW OUTPUT
(N/A) LM
LL LH
LM (N/A)
LH ML
ML (N/A)
MM MM
MH (N/A)
HL MH
HM (N/A)
HH HL
(N/A) HM
(N/A) LL/HH
(N/A) HH(D)
-6tU
-4tU
-3tU
-2tU
-1tU
0tU
+1tU
+2tU
+3tU
+4tU
+6tU
DIVIDED
INVERT
SELA[1:0] SELC[1:0]
SELB[1:0] SELD[1:0]
FB_IN
CLKIN
t0-6tU
t0-5tU
t0-4tU
t0-3tU
t0-2tU
t0-1tU
t0
t0+1tU
t0+2tU
t0+3tU
t0+4tU
t0+5tU
t0+6tU
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3.3V HIGH-SPEED (110 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
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ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
OPERATING RANGE
Storage Temperature –65°C to +150°C
Ambient Temperature with Power Applied –55°C to +125°C
Supply Voltage to Ground Potential –0.5V to +7.0V
DC Input Voltage –0.5V to +7.0V
Output Current into Outputs (LOW) 64 mA
Static Discharge Voltage (per MIL-STD-883, Method 3015) >3000V
Latch-Up Current. >200 mA
RANGE AMBIENT TEMPERATURE VCC
Industrial -40°C to +85°C3.3 + 10%
Commercial 0°C to +70°C3.3 + 10%
ELECTRICAL CHARACTERISTICS
OVER THE 3.3V
+
10% OPERATING RANGE
SYMBOL DESCRIPTION MIN MAX UNIT CONDITION
VOH Output HIGH Voltage 2.4 V VCC = Min., IOH = -18mA
VOL Output LOW Voltage 0.45 V VCC = Min., IOL = 35mA
VIH Input HIGH Voltage 2.0 VCC V(CLKIN and FB_IN inputs
only)
VIL Input LOW Voltage -0.5 0.8 V
VIHH tri-level Input HIGH Voltage
(FSEL, SELx[1:0], Test) [4]
0.87*VCC VCC VMin. < VCC < Max.
VIMM tri-level Input MID Voltage
(FSEL, SELx[1:0], Test) [4]
0.47*VCC 0.53 * VCC VMin. < VCC < Max.
VILL tri-level Input LOW Voltage
(FSEL, SELx[1:0], Test) [4]
0.0 0.13 * VCC VMin. < VCC < Max.
IIH Input HIGH Leakage Current
(CLKIN and FB_IN inputs only)
20 µΑ VCC = Max., VIN = Max.
IIL Input LOW Leakage Current
(CLKIN and FB_IN inputs only)
-20 µΑ VCC = Max., VIN = 0.4V
IIHH Input HIGH Current
(FSEL, SELx[1:0], Test)
200 µΑ VIN = VCC
IIMM Input MID Current
(FSEL, SELx[1:0], Test)
-50 50 µAVIN = VCC/2
IILL Input LOW Current
(FSEL, SELx[1:0], Test)
-200 µAVIN = GND
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NOTES:
4. These inputs are normally wired to VCC, GND or left unconnected (actual threshold voltages vary as a percentage
of VCC). Internal termination resistors hold unconnected inputs at VCC/2. If these inputs are switched, the function
and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all data sheet limits
are achieved.
5. XRK49911 should be tested one output at a time, output shorted for less than one second, less than 10% duty
cycle. Room temperature only.
6. Total output current per output pair can be approximated by the following expression that includes device current
plus load current:
XRK49911: ICCN = {(4+0.11F) + [(835-3F)/Z + (.0022FC)]N} x 1.1
Where:
F = frequency in MHz
C = capacitive load in pF
Z = line impedance in ohms
N = number of loaded outputs; 0, 1, or 2
7. Total power dissipation per output pair can be approximated by the following expression that includes device
power dissipation plus power dissipation due to the load circuit:
PD = {(22 + 0.61F) + [(1550 + 2.7F)/Z) + .0125FC]N} x 1.1
See note 6 for variable definition.
8. Applies to CLKIN and FB_IN inputs only.
IOS Short Circuit Current [5] -200 mA VCC = Max,
VOUT = GND (25° only)
ICCQ Operating Current Used by Inter-
nal Circuitry
Com’l 95 mA VCCN = VCCQ = Max.,
All Inputs Selects Open
Ind 100
ICCN Output Buffer Current per Output Pair [6] 19 mA VCCN = VCCQ = Max.,
IOUT = 0 mA
Inputs Selects Open, fMAX
PD Power Dissipation per Output Pair [7] 104 mW VCCN = VCCQ = Max.,
IOUT = 0 mA
Input Selects Open, fMAX
CAPACITANCE
[8
]
SYMBOL DESCRIPTION MAX. UNIT CONDITION
CIN Input Capacitance 10 pF TA = 25°C,
f=1MHz, VCC=3.3V
ELECTRICAL CHARACTERISTICS
OVER THE 3.3V
+
10% OPERATING RANGE
SYMBOL DESCRIPTION MIN MAX UNIT CONDITION
XRK49911
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FIGURE 4. AC TEST LOAD
FIGURE 5. INPUT TEST WAVEFORM
SWITCHING CHARACTERISTICS
OVER THE OPERATING RANGE [2,9
]
SYMBOL DESCRIPTION MIN MAX UNIT
fNOM Operating Clock Frequency in MHz FSEL = LOW [1, 2] 15 30 MHz
FSEL = MID [1, 2] 25 50
FSEL = HIGH [1, 2, 3] 40 110
CLR2
R1
VCC
LOAD
R1 = 1 00
R2 = 1 00
CL= 30pF
(I nc l udes fixt ure and probe c apacit ances )
0.0V
2.0V
Vth = 1.5V
0.8V
2.0V
Vth = 1.5V
0.8V
<1ns <1ns
3.0V
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NOTES:
9. Test measurement levels for the XRK49911 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition
times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise
specified.
10. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the
same tU delay has been selected when all are loaded with 30pF and terminated with 50
Ω
to VCC/2.
SWITCHING CHARACTERISTICS
OVER THE 3.3V + 10% OPERATING RANGE [2,9
]
SYMBOL DESCRIPTION
XRK49911-2 XRK49911-5 XRK49911-7
UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
tRPWH CLKIN Pulse Width HIGH 4 4 4 ns
tRPWL CLKIN Pulse Width LOW 4 4 4 ns
tuProgrammable Skew Unit See Table 1
tSKEWPR Zero Output Matched-Pair Skew
(Qx[1:0]) [10, 11]
0.05 0.2 0.1 0.25 0.1 0.25 ns
tSKEW0 Zero Output Skew (All Outputs) [10, 12] 0.1 0.25 0.25 0.5 0.3 0.75 ns
tSKEW1 Output Skew (Rise-Rise, Fall-Fall,
Same Class Outputs) [10, 13]
0.25 0.5 0.6 0.7 0.6 1ns
tSKEW2 Output Skew (Rise-Fall, Nominal-
Inverted, Divided-Divided) [10, 13]
0.3 10.5 1 1 1.5 ns
tSKEW3 Output Skew (Rise-Rise, Fall-Fall,
Different Class Outputs) [10, 13]
0.25 0.5 0.5 0.7 0.7 1.2 ns
tSKEW4 Output Skew (Rise-Fall, Nominal-
Divided, Divided-Inverted [10, 13]
0.5 0.9 0.5 11.2 1.7 ns
tDEV Device-to-Device Skew [14, 15] 0.75 1.25 1.65 ns
tPD Propagation Delay, CLKIN Rise to
FB_IN Rise
-0.25 00.25 -0.5 00.5 -0.7 00.7 ns
tODCV Output Duty Cycle Variation [16] -0.65 00.65 -1 0 1 -1.2 01.2 ns
tPWH Output HIGH Time Deviation from 50%
[17]
2.0 2.5 3ns
tPWL Output LOW Time Deviation from 50%
[17]
1.5 33.5 ns
tORISE Output Rise Time [17, 18] 0.15 11.2 0.15 11.5 0.15 1.5 2.5 ns
tOFALL Output Fall Time [17, 18] 0.15 11.2 0.15 11.5 0.15 1.5 2.5 ns
tLOCK PLL Lock Time [19] 0.5 0.5 0.5 ms
tJR Cycle-to-Cycle Output
Jitter
RMS [14] 25 25 25 ps
Peak-to-Peak
[14]
200 200 200
XRK49911
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11. t SKEWPR is defined as the skew between a pair of outputs (Qx0 and Qx1) when all eight outputs are selected for
0tU.
12. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or
inverted but not shifted
13. There are three classes of outputs: Nominal (multiple of tU delay), Inverted (QD[1:0] only with SELD0 = SELD1 =
HIGH), and Divided (QC[1:0] and QD[1:0] only in Divide-by-2 or Divide-by-4 mode).
14. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect
these parameters.
15. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient
temperature, air flow, etc.)
16. tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2
and tSKEW4 specifications.
17. Specified with outputs loaded with 30pF for the XRK49911-5 and -7 devices. Devices are terminated through 50
Ω
to VCC/2. tPWH is measured at 2.0V. tPWL is measured at 0.8V.
18. tORISE and tOFALL measured between 0.8V and 2.0V.
19. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is
stable and within normal operating limits. This parameter is measured from the application of a new signal or
frequency at CLKIN or FB_IN until tPD is within specified limits
FIGURE 6. AC TIMING DIAGRAMS
CLKIN
FB_IN
Qxx output
Other Qxx output
Inve rte d Q x x ou tp ut
CLKIN Divided by 2
tREF
tRPWH tRPWL
tPD tODCV tODCV
tJR
tSKEWPR,
tSKEW0, 1
tSKEWPR,
tSKEW0, 1
tSKEW2 tSKEW2
CLKIN Divided by 4
tSKEW3, 4 tSKEW3, 4 tSKEW3, 4
tSKEW1, 3, 4 tSKEW2, 4
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PACKAGE DIMENSIONS
B1
B
A
A1
C
D2
e
R
SEATING PLANE
A2
Corner Chamfer
30° x H1
7°±2 deg typ.
E3
D3
1232
D
D1
E
E1
45° x H2
SYMBOL MIN MAX MIN MAX
A 0.120 0.140 3.05 3.56
A1 0.075 0.095 1.91 2.41
A2 0.020 --- 0.51 ---
B 0.013 0.021 0.33 0.53
B1 0.026 0.032 0.66 0.81
C 0.008 0.013 0.19 0.32
D 0.485 0.495 12.33 12.58
D1 0.448 0.454 11.39 11.54
D2 0.400 0.440 10.17 11.18
D3
E 0.585 0.595 14.87 15.11
E1 0.545 0.557 13.85 14.15
E2 0.500 0.540 12.71 13.72
E3
e
H1 0.023 0.029 0.58 0.74
H2 0.042 0.048 1.07 1.22
R 0.025 0.045 0.64 1.14
Note: The control dimension is in inches.
0.050 BSC 1.27 BSC
INCHES MILLIMETERS
10.16 typ.0.400 typ.
0.300 typ. 7.62 typ.
32 LEAD PLASTIC LEADED CHIP CARRIER
(PLCC)
Rev. 1.00
XRK49911
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3.3V HIGH-SPEED (110 MHZ) PROGRAMMABLE SKEW CLOCK BUFFER
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NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2005 EXAR Corporation
Datasheet June 2005.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
REVISION HISTORY
REVISION # DATE DESCRIPTION
1.0.0 June 13, 2005 Initial Production Release
