Flip-Chip4
SOT23-5L
DFN4-1x1
Features
• Ultra low output noise: 6.5 μVRMS
• Operating input voltage range: 1.5 V to 5.5 V
• Output current up to 250 mA
• Very low quiescent current: 12 μA at no-load
• Controlled Iq in dropout condition
• Very low-dropout voltage: 250 mV at 250 mA
• Very high PSRR: 80 dB@100 Hz, 60 dB @ 100 kHz
• Output voltage accuracy: 2% across line, load and temperature
• Output voltage versions: from 1 V to 5 V, with 50 mV step
• Logic-controlled electronic shutdown
• Output discharge feature
• Internal soft-start
• Overcurrent and thermal protections
• Temperature range: from -40 °C to +125 °C
• Packages: Flip-Chip4, DFN4-1x1, SOT23-5L
Applications
• Smartphones/tablets
• Image sensors
• Instrumentation
• VCO and RF modules
Description
The LDLN025 is a 250 mA low-dropout voltage regulator, able to work with an input
voltage range from 1.5 V to 5.5 V.
The typical dropout voltage at 250 mA load is 120 mV.
The very low quiescent current, which is just 12 μA at no-load, extends battery-life of
applications requiring very long standby time.
Thanks to its ultra low noise value and high PSRR, the LDLN025 provides a very
clean output, suitable for ultra-sensitive loads. It is stable with ceramic capacitors.
The enable logic control function puts the device into shutdown mode allowing a total
current consumption lower than 1 μA.
The device also includes short-circuit and thermal protection.
Typical applications are noise sensitive loads such as ADC, VCO in mobile phones
and tablets, wireless LAN devices. The LDLN025 is designed to keep the quiescent
current under control and at a low value also during dropout operation, extending the
operating time of battery-powered devices.
Several small package options are available.
Maturity status link
LDLN025
250 mA ultra low noise LDO
LDLN025
Datasheet
DS11756 - Rev 6 - October 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
1Block diagram
Figure 1. Block diagram
VIN
GND
VOUT
Bia s
genera tor
Bandgap
refere nce
EN
Thermal
prote ction
Ena ble
AMG280620171000MT
LDLN025
Block diagram
DS11756 - Rev 6 page 2/26
2Pin configuration
Figure 2. Pin configuration
Table 1. Pin description
Symbol DFN4-1x1 Flip-Chip4 SOT23-5L Description
VIN 4 A1 1 LDO Supply voltage
VOUT 1 A2 5 LDO Output voltage
GND 2 B2 2 Ground
EN 3 B1 3
Enable input: set VEN = high to turn on the device;
VEN = low to turn off the device
This pin is internally pulled down via 1 MΩ resistor
NC - - 4 Not internally connected: can be connected to GND
Exposed pad Exposed pad - - Must be connected to GND
LDLN025
Pin configuration
DS11756 - Rev 6 page 3/26
3Typical application diagram
Figure 3. Typical application diagram
VIN
GND
VI
EN
CIn
VO
VOUT
COut
LDLN025
OFF
ON
1µF 1µF
AMG010720161412MT
LDLN025
Typical application diagram
DS11756 - Rev 6 page 4/26
4Maximum ratings
Table 2. Absolute maximum ratings
Symbol Parameter Value Unit
VIN Input supply voltage -0.3 to 7 V
VOUT Output voltage -0.3 to VIN +0.3 V
IOUT Output current Internally limited A
EN Enable pin voltage -0.3 to VIN +0.3 V
PDPower dissipation Internally limited W
ESD
Charge device model ±1000
V
Human body model ±2000
TJ-OP Operating junction temperature -40 to 125 °C
TJ-MAX Maximum junction temperature 150 °C
TSTG Storage temperature -55 to 150 °C
Table 3. Thermal data
Symbol Parameter DFN4-1x1 Flip-Chip4 SOT23-5L Unit
Rthja Thermal resistance, junction-to-
ambient 220 210 200 °C/W
LDLN025
Maximum ratings
DS11756 - Rev 6 page 5/26
5Electrical characteristics
(TJ = 25 °C, VIN = VOUT(nom) + 1 V or 1.5 V, whichever is greater; VEN = 1.2 V; CIN = 1 μF; COUT = 1 μF;
IOUT = 1 mA)
Table 4. Electrical characteristics
Symbol Parameter Test conditions Min. Typ. Max. Unit
VIN Operating input voltage
range 1.5 5.5 V
VOUT Output voltage accuracy
(Flip-Chip package)
VOUT + 1 V < VIN < 5.5 V, (1)
1 mA < IOUT < 0.25 A, VOUT ≥ 1.8 V,
-40 °C < TJ < 125 °C
-2.0 +2.0
%
VOUT + 1 V < VIN < 5.5 V,(1)
1 mA < IOUT < 0.25 A, VOUT < 1.8 V,
-40 °C < TJ < 125 °C
-3.0 +3.0
VOUT
Output voltage accuracy
(DFN and SOT23
packages)
VOUT + 1 V < VIN < 5.5 V,(1)
1 mA < IOUT < 0.25 A, VOUT ≥ 1.8 V,
-40 °C < TJ < 125 °C
-2.0 +2.0
%
VOUT + 1 V < VIN < 5.5 V,(1)
1 mA < IOUT < 0.25 A, VOUT < 1.8 V,
-40 °C < TJ < 125 °C
-4.0 +4.0
∆VOUT/
∆VIN
Static line regulation
VOUT + 1 V < VIN < 5.5 V(1) 0.02
%/V
-40 °C < TJ < 125 °C 0.06
Line transient (2) ∆VIN = +/- 0.6 V, trise = tfall = 30 μs -1 +1 mV
∆VOUT/
∆IOUT
Static load regulation
1 mA < IOUT < 0.25 A, VOUT ≥ 1.8 V 0.002
%/mA
-40 °C < TJ < 125 °C, VOUT ≥ 1.8 V 0.007
1 mA < IOUT < 0.25 A, VOUT ˂ 1.8 V 20 mV
Load transient(2) ∆IOUT = 1 mA to 250 mA and back,
trise = tfall = 10 μs -40 +40 mV
∆VOUT Overshoot on startup(2) Percentage of VOUT(nom) 5 %
VDROP Dropout voltage(3)
IOUT = 0.1 A 50
mV
IOUT = 0.25 A 120
IOUT = 0.25 A, -40 °C < TJ < 125 °C
(Flip-Chip4) 200
IOUT = 0.25 A, -40 °C < TJ < 125 °C
(DFN4-1x1) 250
eN Output noise voltage (2)
f = 10 Hz to 100 kHz; IOUT = 1 mA 10
µVRMS
f = 10 Hz to 100 kHz; IOUT = 250 mA 6.5
LDLN025
Electrical characteristics
DS11756 - Rev 6 page 6/26
Symbol Parameter Test conditions Min. Typ. Max. Unit
SVR Supply voltage rejection(2)
f = 100 Hz; IOUT = 20 mA 80
dB
f = 1 kHz; IOUT = 20 mA 80
f = 10 kHz; IOUT = 20 mA 75
f = 100 kHz; IOUT = 20 mA 60
IQ
Quiescent current(4)
IOUT = 0 A 12
µA
IOUT = 0 A; -40 °C < TJ < 125 °C 25
IOUT = 0.25 A 250
µA
IOUT = 0.25 A; -40 °C < TJ < 125 °C 425
Shutdown current VEN = 0 V 0.2 1 µA
ISC Short-circuit current VOUT = 0 V 250 500 mA
RLOW Output discharge
resistance VEN = 0 V 230 Ω
VEN
VIL, enable input logic low
VOUT + 1 V < VIN < 5.5 V -40 °C < TJ
< 125 °C(1)
0.4
V
VIH, enable input logic
high 1.2
IEN Enable pin input current
VIN = VEN = 5.5 V 5.5
µA
VIN = 5.5 V; VEN = 0 V 0.001
tON Turn-on time(2) From VEN > VIH to VOUT = 95 % of
VOUT(nom)
80 150 µs
TSHDN
Thermal shutdown(2) IOUT > 1 mA 160
°C
Hysteresis 20
1. VIN = VOUT + 1 V or 1.5 V, whichever is greater. Not applicable for 5 V output voltage versions.
2. Guaranteed by design.
3. Dropout voltage is the input-to-output voltage difference at which the output voltage is 100 mV below its nominal value.
4. The quiescent current is defined as IIN-IOUT and does not include the EN pin current.
Table 5. Recommended input and output capacitors
Symbol Parameter Test conditions Min. Typ. Max. Unit
CIN Input capacitance
Stability
0.7 1
μF
COUT Output capacitance 0.7 1 10
ESR Output/input capacitance 5 500 mΩ
LDLN025
Electrical characteristics
DS11756 - Rev 6 page 7/26
6Typical characteristics
(The following plots are referred to LDLN025J2925R in the typical application circuit and, unless otherwise noted,
at TA = 25 °C).
Figure 4. Output voltage vs. temperature (VIN = 3.925 V)
2.8
2.82
2.84
2.86
2.88
2.9
2.92
2.94
2.96
2.98
3
-75 -50 -25 0 25 50 75 100 125 150
Output voltag e [V]
Te mperature [°C]
NO LOAD
IOUT 1mA
IOUT 10mA
IOUT 250mA
VIN = VOUT + 1 V, EN = 2 V, IOUT = from 0 to 250 mA, CIN = 1 μF , COUT = 1 μF
AMG010720161030MT
Figure 5. Output voltage vs. temperature (VIN = 5.5 V)
Output voltag e [V]
Te mperature [°C]
AMG010720161031MT
2.8
2.82
2.84
2.86
2.88
2.9
2.92
2.94
2.96
2.98
3
-75 -50 -25 0 25 50 75 100 125 150
NO LOAD
IOUT 1mA
IOUT 10mA
IOUT 250mA
VIN = 5.5 V; IOUT = from 0 to 250 mA, CIN = 1 μF, COUT = 1 μF
Figure 6. Load regulation vs. temperature
Te mperature [°C]
VIN = VOUT + 1 V; IOUT = from 1 mA to 0.25 A, CIN = 1 μF , COUT = 1 μF
AMG010720161032MT
-0.020
-0.015
-0.010
-0.005
0.000
0.005
0.010
0.015
0.020
-75 -50 -25 0 25 50 75 100 125 150
Lo ad re gulation [%/mA]
Figure 7. Line regulation vs. temperature
Te mperature [°C]
VIN = from 3.925 to 5.5 V, IOUT = 1 mA, CIN = 1 μF , COUT = 1 μF
AMG010720161033MT
-0.500
-0.400
-0.300
-0.200
-0.100
0.000
0.100
0.200
0.300
0.400
0.500
-75 -50 -25 0 25 50 75 100 125 150
Line re gulation [%/V]
LDLN025
Typical characteristics
DS11756 - Rev 6 page 8/26
Figure 8. Quiescent current vs. temperature (IOUT = 0 mA)
Quiescent current [µA]
Te mperature [°C]
VIN = VOUT + 1 V, VEN = 1.2 V, IOUT = 0 A, CIN = 1 μF , COUT = 1 μF
AMG010720161034MT
0
2
4
6
8
10
12
14
16
18
20
22
24
-75 -50 -25 0 25 50 75 100 125 150
Figure 9. Quiescent current vs. temperature (IOUT = 250
mA)
Quiescent current [μA]
Te mperature [°C]
VIN = VOUT + 1 V, VEN = 1.2 V, IOUT = 250 mA, CIN = 1 μF , COUT = 1 μF
AMG010720161035MT
100
125
150
175
200
225
250
275
300
325
350
375
400
-75 -50 -25 0 25 50 75 100 125 150
Figure 10. GND current vs. input voltage
GND current [μA]
Input voltage [V]
VIN = EN = from 0 to 6 V, IOUT = 0 A, CIN = 1 μF , COUT = 1 μF
AMG010720161036MT
0
2
4
6
8
10
12
14
16
18
20
22
24
26
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7
Figure 11. Off-state current vs. temperature
Quiescent current [µA]
Te mperature [°C]
VIN = VOUT + 1 V, IOUT = 0 A, CIN = 1 μF , COUT = 1 μF
AMG010720161037MT
0
2
4
6
8
10
-75 -50 -25 0 25 50 75 100 125 150
Figure 12. Quiescent current vs. output current
Quiescent current [μA]
Output current [mA]
VEN = 1.2 V, IOUT = from 0 to 250 mA, CIN = 1 μF , COUT = 1 μF
AMG010720161038MT
0
25
50
75
100
125
150
175
200
225
250
275
300
0 25 50 75 100 125 150 175 200 225 250 275
VIN=5.5V
VIN=3.9V
Figure 13. Quiescent current vs. output current (zoom)
LDLN025
Typical characteristics
DS11756 - Rev 6 page 9/26
Figure 14. Dropout voltage vs. temperature
Dropout voltage [V]
Te mperature [°C]
VOUT = 2.8 V, IOUT = 0.25 A, CIN = 1 μF , COUT = 1 μF
AMG010720161040MT
0
0.025
0.05
0.075
0.1
0.125
0.15
0.175
0.2
0.225
0.25
-75 -50 -25 0 25 50 75 100 125 150
Flip-Chip
DFN4
Figure 15. Dropout voltage vs. load current
VDROP [V]
Output current [A]
VOUT = 2.8 V, CIN = 1 μF , COUT = 1 μF
AMG010720161041MT
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0 0.05 0.1 0.15 0.2 0.25 0.3
Flip-Chip
DFN4
Figure 16. Output voltage vs. input voltage
Output voltag e [V]
Input voltage [V]
VIN = VEN = from 0 to 5.5 V, VOUT = 2.75 V, IOUT = 250 mA, CIN = 1 μF , COUT = 1 μF
AMG010720161042MT
0
0.5
1
1.5
2
2.5
3
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5
125°C
85°C
55°C
25°C
0°C
-25°C
-40°C
Figure 17. Short circuit current vs. dropout voltage
ISC [mA]
Drop voltage [V]
AMG010720161043MT
0
100
600
700
0 0.5 1 1.5 4.5 5 5.5 6 6.5
200
300
400
500
2
2.5
3.5
34
Figure 18. Enable threshold vs. temperature
Enable threshold [V]
Te mperature [°C]
VIN = 3.925 V, IOUT = 1 mA, CIN = 1 μF , COUT = 1 μF
AMG010720161044MT
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
-75 -50 -25 0 25 50 75 100 125 150
VIL
VIH
Figure 19. Stability region vs. COUT and ESR
ESR [Ω]
COUT [μF]
VIN = VOUT + Vdrop(max) to 5.5 V, IOUT = from 1 mA to 250 mA, T= 25 °C, CIN = 1 μF
AMG010720161045MT
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
2.75
3
0.3
0.1 0.47 14.7 10 22 100
Stability Regio n
Ins ta bility Re gion
Not Te ste d Re gion
Not Te ste d Re gion
LDLN025
Typical characteristics
DS11756 - Rev 6 page 10/26
Figure 20. PSRR vs. frequency (VOUT = 2.75 V)
VIN = 3.75 V + Vripple, VOUT = 2.75 V, no CIN, COUT = 1 μF, VEN = 1.2 V
AMG010720161046MT
0
20
40
60
80
100
1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07
S VR [dB]
f [Hz]
1mA
20mA
50mA
100mA
150mA
200mA
250mA
Figure 21. PSRR vs. frequency (VOUT = 1.8 V)
0
20
40
60
80
100
1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07
SVR [dB]
f [Hz]
10mA
20mA
50mA
100mA
250mA
VIN = 2.5 V + Vripple, VOUT = 1.8 V, no CIN, COUT = 1 µF, VEN = 1.2 V
Figure 22. PSRR vs. frequency (VOUT = 5 V)
0
20
40
60
80
100
1.0E+01 1.0E+02 1.0E+03 1.0E+04 1.0E+05 1.0E+06 1.0E+07
SVR [dB]
f [Hz]
10mA
20mA
50mA
100mA
250mA
VIN = 5 V + Vripple, VOUT = 5 V, no CIN, COUT = 1 µF, VEN = 1.2 V
Figure 23. Noise density
VIN = 3.75 V, VOUT = 2.75 V, CIN = COUT = 1 μF
AMG010720161047MT
0.001
0.01
0.1
1
10
1.0E+01 1 .0E+0 2 1.0E+03 1.0E+04 1.0E+05
Vn [uV/S QRT(Hz)]
f [Hz]
0mA
1mA
10mA
100m A
Figure 24. Line transient (IOUT = 1 mA)
VIN = from 3.4 V to 4.4 V, IOUT = 1 mA, tr = 10 μs, CIN = COUT = 1 μF (X7R)
AMG010720161048MT
VIN
VOUT
Figure 25. Line transient (IOUT = 250 mA)
VIN = from 3.4 V to 4.4 V, IOUT = 250 mA, tr = 10 μs, CIN = COUT = 1 μF (X7R)
AMG010720161049MT
VOUT
VIN
VIN
VOUT
LDLN025
Typical characteristics
DS11756 - Rev 6 page 11/26
Figure 26. Load transient
IOUT = from 0 mA to 250 mA, tr = 10 μs, CIN = COUT = 1 μF (X7R)
AMG010720161050MT
VIN
VOUT
VOUT
IOUT
Figure 27. Inrush current
AMG180720161000MT
VIN
VIN = 4 V, IOUT = 0 mA, CIN = COUT = 1 μF (X7R)
VIN
VOUT
IIN
VEN
Figure 28. Enable transient (IOUT = 0 mA)
VIN = 3.925 V, VEN = from 0 V to 3.925 V, IOUT = 0 mA, tr = 1 μs, CIN = COUT = 1 μF (X7R)
AMG010720161052MT
VIN
VOUT
VIN
VOUT
VEN
Figure 29. Enable transient (IOUT = 250 mA)
VIN = 3.925 V, VEN = from 0 V to 3.925 V, IO = 250 mA, tr = 1 μs, CIN = COUT = 1 μF (X7R)
AMG010720161053MT
VIN
VOUT
VIN
VOUT
VEN
LDLN025
Typical characteristics
DS11756 - Rev 6 page 12/26
7Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
7.1 Flip-Chip4 package information
Figure 30. Flip-Chip4 package outline
8387748 option F
LDLN025
Package information
DS11756 - Rev 6 page 13/26
Table 6. Flip-Chip4 mechanical data
Dim.
mm
Min. Typ. Max.
A 0.375 0.410 0.445
A1 0.145 0.160 0.175
A2 0.230 0.250 0.270
b 0.189 0.210 0.231
D 0.598 0.628 0.658
D1 0.350
E 0.598 0.628 0.658
E1 0.350
SD 0.175
SE 0.175
f 0.139
ccc 0.075
Figure 31. Flip-Chip4 recommended footprint
LDLN025
Flip-Chip4 package information
DS11756 - Rev 6 page 14/26
7.2 Flip-Chip4_160304-47_carrier_tape
Figure 32. Flip-Chip4 carrier tape
LDLN025
Flip-Chip4_160304-47_carrier_tape
DS11756 - Rev 6 page 15/26
7.3 DFN4-1x1 package info
Figure 33. DFN4-1x1 package outline
8405587
LDLN025
DFN4-1x1 package info
DS11756 - Rev 6 page 16/26
Table 7. DFN4-1x1 package mechanical data
Dim.
mm
Min. Typ. Max.
A 0.36 0.40
A1 0.00 0.05
A2 0.15 0.25 0.35
A3 0.125
b 0.15 0.20 0.25
D 0.95 1.00 1.05
D2 0.38 0.48 0.58
e 0.65
E 0.95 1.00 1.05
E2 0.38 0.48 0.58
L 0.15 0.25 0.35
K 0.15
N 4
7.4 DFN4_1x1x0.38_pitch_4mm_carrier_tape
Figure 34. DFN4 (1x1x0.38 pitch 4 mm) carrier tape
LDLN025
DFN4_1x1x0.38_pitch_4mm_carrier_tape
DS11756 - Rev 6 page 17/26
7.5 SOT23-5L mechanical data
Figure 35. SOT23-5L package outline
7049676_k
Table 8. SOT23-5L package mechanical data
Dim.
mm
Min. Typ. Max.
A 0.90 1.45
A1 0 0.15
A2 0.90 1.30
b 0.30 0.50
c 0.09 0.20
D 2.95
E 1.60
e 0.95
H 2.80
L 0.30 0.60
θ 0° 8°
LDLN025
SOT23-5L mechanical data
DS11756 - Rev 6 page 18/26
Figure 36. SOT23-5L recommended footprint
Note: Dimensions are in mm
LDLN025
SOT23-5L mechanical data
DS11756 - Rev 6 page 19/26
8Ordering information
Table 9. Order code
Order code Package Output voltage (V) Marking Packing
LDLN025PU12R
DFN4-1x1
1.2 12
Tape and reel
LDLN025PU18R 1.8 18
LDLN025PU25R 2.5 25
LDLN025PU275R 2.75 2Z
LDLN025PU28R 2.8 28
LDLN025PU29R 2.9 29
LDLN025PU30R 3.0 30
LDLN025PU32R 3.2 32
LDLN025PU33R 3.3 33
LDLN025PU50R 5.0 50
LDLN025J12R
Flip-Chip4
1.2 M
LDLN025J18R 1.8 E
LDLN025J25R 2.5 H
LDLN025J28R 2.8 I
LDLN025J29R 2.9 S
LDLN025J2925R 2.925 K
LDLN025J30R (1) 3.0 G
LDLN025J32R 3.2 N
LDLN025J33R 3.3 F
LDLN025J50R 5.0 P
LDLN025M12R
SOT23-5L
1.2 LN12
LDLN025M15R 1.5 LN15
LDLN025M18R 1.8 LN18
LDLN025M25R 2.5 LN25
LDLN025M28R 2.8 LN28
LDLN025M30R 3.0 LN30
LDLN025M33R 3.3 LN33
LDLN025M45R 4.5 LN45
1. Part number in development. Contact our sales office.
LDLN025
Ordering information
DS11756 - Rev 6 page 20/26
8.1 Marking information
Figure 37. Flip-Chip marking composition (marking view)
A1
A2
B1
B2
#
AMG260720161100MT
Note: the symbol # indicates the marking digit, as per Table 9. Order code.
LDLN025
Marking information
DS11756 - Rev 6 page 21/26
Revision history
Table 10. Document revision history
Date Revision Changes
03-Aug-2016 1 First release.
01-Sep-2016 2 Updated Table 8: “Order code”.
Minor text changes.
24-Oct-2016 3 Updated Table 2: "Absolute maximum ratings".
Minor text changes.
17-Nov-2016 4 Updated Section 9: “Ordering information”. Minor text changes.
12-Jul-2017 5
Added SOT23-5L package.
Modified silhouette, features, Figure 1: "Block
diagram", Section 2: "Pin configuration" and Table 4:
"Electrical characteristics".
Added Section 7.5: "SOT23-5L package information".
Updated Table 9: "Order code".
Minor text changes.
09-Oct-2018 6
Added Figure 21. PSRR vs. frequency (VOUT = 1.8 V),
Figure 22. PSRR vs. frequency (VOUT = 5 V), new order codes
LDLN025PU12R and LDLN025J29R in Table 9. Order code.
LDLN025
DS11756 - Rev 6 page 22/26
Contents
1Block diagram .....................................................................2
2Pin configuration ..................................................................3
3Typical application diagram ........................................................4
4Maximum ratings ..................................................................5
5Electrical characteristics...........................................................6
6Typical characteristics .............................................................8
7Package information..............................................................13
7.1 Flip-Chip4 package information..................................................13
7.2 Flip-Chip4 packing information ..................................................14
7.3 DFN4-1x1 package information..................................................15
7.4 DFN4-1x1 packing information ..................................................17
7.5 SOT23-5L package information..................................................17
8Ordering information .............................................................20
8.1 Marking information ...........................................................20
Revision history .......................................................................22
Contents ..............................................................................23
List of tables ..........................................................................24
List of figures..........................................................................25
LDLN025
Contents
DS11756 - Rev 6 page 23/26
List of tables
Table 1. Pin description......................................................................3
Table 2. Absolute maximum ratings .............................................................5
Table 3. Thermal data.......................................................................5
Table 4. Electrical characteristics ...............................................................6
Table 5. Recommended input and output capacitors ..................................................7
Table 6. Flip-Chip4 mechanical data ............................................................ 14
Table 7. DFN4-1x1 package mechanical data ..................................................... 17
Table 8. SOT23-5L package mechanical data ..................................................... 18
Table 9. Order code ....................................................................... 20
Table 10. Document revision history ............................................................. 22
LDLN025
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List of figures
Figure 1. Block diagram ....................................................................2
Figure 2. Pin configuration ...................................................................3
Figure 3. Typical application diagram ...........................................................4
Figure 4. Output voltage vs. temperature (VIN = 3.925 V)..............................................8
Figure 5. Output voltage vs. temperature (VIN = 5.5 V) ...............................................8
Figure 6. Load regulation vs. temperature ........................................................8
Figure 7. Line regulation vs. temperature.........................................................8
Figure 8. Quiescent current vs. temperature (IOUT = 0 mA) ............................................9
Figure 9. Quiescent current vs. temperature (IOUT = 250 mA)...........................................9
Figure 10. GND current vs. input voltage..........................................................9
Figure 11. Off-state current vs. temperature........................................................9
Figure 12. Quiescent current vs. output current .....................................................9
Figure 13. Quiescent current vs. output current (zoom) ................................................9
Figure 14. Dropout voltage vs. temperature ....................................................... 10
Figure 15. Dropout voltage vs. load current ....................................................... 10
Figure 16. Output voltage vs. input voltage ....................................................... 10
Figure 17. Short circuit current vs. dropout voltage .................................................. 10
Figure 18. Enable threshold vs. temperature ...................................................... 10
Figure 19. Stability region vs. COUT and ESR...................................................... 10
Figure 20. PSRR vs. frequency (VOUT = 2.75 V).................................................... 11
Figure 21. PSRR vs. frequency (VOUT = 1.8 V) .................................................... 11
Figure 22. PSRR vs. frequency (VOUT = 5 V) ...................................................... 11
Figure 23. Noise density .................................................................... 11
Figure 24. Line transient (IOUT = 1 mA) .......................................................... 11
Figure 25. Line transient (IOUT = 250 mA) ........................................................ 11
Figure 26. Load transient ................................................................... 12
Figure 27. Inrush current .................................................................... 12
Figure 28. Enable transient (IOUT = 0 mA) ........................................................ 12
Figure 29. Enable transient (IOUT = 250 mA) ...................................................... 12
Figure 30. Flip-Chip4 package outline ........................................................... 13
Figure 31. Flip-Chip4 recommended footprint ..................................................... 14
Figure 32. Flip-Chip4 carrier tape .............................................................. 15
Figure 33. DFN4-1x1 package outline ........................................................... 16
Figure 34. DFN4 (1x1x0.38 pitch 4 mm) carrier tape ................................................. 17
Figure 35. SOT23-5L package outline........................................................... 18
Figure 36. SOT23-5L recommended footprint ..................................................... 19
Figure 37. Flip-Chip marking composition (marking view) ............................................. 21
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