M48T212Y-70MH6E - STMicroelectronics

1/32April 2004

M48T212Y

M48T212V

5.0V or 3.3V TIMEKEEPER® Supervisor

FEAT URES SUMMARY

■INTEGRAT ED RE AL T IME CLOCK, POW ER-

FAIL CONTRO L CIRCUIT, BATTERY AND

CRYSTAL

■CONVERTS L OW POWER SRAM INTO

NVRAMs

■YEAR 2000 COMP LIANT (4-Digit Year)

■BATTERY L OW FLAG

■MICROPROCESSOR POWER-ON RESET

■PROGRAMMABLE ALARM OUTPU T

ACTIVE IN THE BATTERY BACKED-UP

MODE

■WA TCHDOG TIMER

■AUTOMATIC POWER-FAIL CHIP

DESELECT AND WRITE PRO TECTION

■CHOICE OF WRITE PRO TECT VOLTA GE S

(VPFD = Power-fail Deselect Voltage):

– M48T212Y: VCC = 4.5 to 5.5V

4.2V ≤ VPFD ≤ 4.5V

– M48T212V: VCC = 3.0 to 3.6V

2.7V ≤ VPFD ≤ 3.0V

■PACKAGING INCLUDES A 44-LEAD SO IC

AND SNAPHAT® TOP (to be ordered

separately)

Figu re 1. 44- pi n S OI C Package

SOH44 (MH)

SNAPHAT (SH)

Crystal/Battery

M48T212Y, M48T212V

2/32

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. 44-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2. Logi c Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. S OIC Connec tions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. Hardware Hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

A ddress Decod ing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 2. Operati ng Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Table 3. Truth Table for SRAM Bank Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 5. Chip Enable C ontrol and Bank Select Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Table 4. Chip Enable Control and Bank Select Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

READ Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 6. READ Cycle Timing: RT C Control Signal Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 5. RE A D Mode AC Charac teristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

WRITE Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 7. WRITE Cycle Timing: RTC Control Signal Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 6. WRITE Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Data Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

TIMEKEEPER® Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Reading the Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Setting the Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Stopping and Starting the Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 7. TIMEKEEPER® Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Setting the Alarm Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 8. Alarm Interrupt Reset Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 8. A larm Repeat Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Figure 9. Back-up Mode Alarm Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7

VCC Switch Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

Po wer-o n Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8

Figure 10.(RSTIN1 & RSTIN2) Timing Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 9. Reset AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Calibrating th e Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Battery Low Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Initial Power-on Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 10. Default Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 11.Crystal Accuracy Across Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3/32

M48T212Y, M 48T212V

Figure 12.Calibrati on Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

VCC Noise And Negative Going Transients. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 13.Supply Voltage Protect ion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

MAXIMUM RATING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 11. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 12. DC and AC Measurem ent Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 14.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 13. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 14. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 15.Power Down/Up Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 15. Power Down/Up M ode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 16.SOH44 – 44-lead Plastic Small Outline, SNAPHA T, Package Out lin e . . . . . . . . . . . . . . 27

Table 16. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Mechanical Data . . . . . . 27

Figure 17.SH – 4-pin SNAPHAT Housing for 48 mAh Battery & Crystal, Package Outline . . . . . . 28

Table 17. SH – 4-pin SNAPHAT Housing for 48 mAh Battery & Crystal, Package Mech. Data . . . 28

Figure 18.SH – 4-pin SNAPHA T Housing for 120mAh B attery & Crystal, Package Outline . . . . . . 29

Table 18. SH – 4-pin SNAPHA T Housing for 120mAh Battery & Crystal, Package M ech. Data . . . 29

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 19. Ordering Information Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 20. SNAPHAT® Battery Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

REVISIO N HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 21. Document Revisi on History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

M48T212Y, M48T212V

4/32

DESCRIPTION

The M48T212Y/V are self-contained de vices that

include a real time clock (RTC), programmable

alarms, a watchdog timer, and two external chip

enable out puts which prov ide con trol of up t o four

(two in parallel) external low-power static RAMs.

Access to all TIMEKEEPER® functions and the

external RAM is the same as conventional byte-

wid e SRAM. The 16 TIMEKEEPER Registe rs offer

Century, Year, Month, Date, Day, Hour, Minute,

Second, Calibration, Alarm, Watchdog, and Flags.

Externally attached sta tic RAMs are controlled by

the M48T212Y/V via the E1CON and E2CON sig-

nals (see Table 3., page 8).

The 44-pin, 330mil SOIC provides sockets with

gold plated contacts at both ends for direct con-

nection to a separate SNAPHAT® housing con-

taining the battery and crystal. The unique design

allows the SNAPHAT battery package to be

mounted on top of the SOIC package after the

completion of the surface mount process.

Insertion of the SNAPHAT housing after reflow

prevents potential battery and crystal damage due

to the high temperatures required for device sur-

face-mounting. The SNAPHAT housing is keyed

to prevent reverse insertion.

The SOIC and battery/crystal packages are

shipped separately in plastic anti-static tubes or in

Tape & Reel form. For the-44 lead SOIC, the bat-

tery/crystal package (e.g., SNAPHAT) part num-

ber is “M4TXX-BR12SH” (see Table

20., page 30).

Caution: Do not place the SNAPHAT battery/crys-

tal top in conductive foam, as this will drain the lith-

ium button-cell battery.

5/32

M48T212Y, M 48T212V

Figure 2. Logic Diagram Table 1. Signal Names

AI03019

A0-A3

DQ0-DQ7

VCC

M48T212Y

M48T212V

VSS

E2CON

E1CON

RSTIN2

RSTIN1

RST

IRQ/FT

VOUT

WDI

VCCSW

A0-A3 Address Inputs

DQ0-DQ7 Data Inputs/Outputs

RSTIN1 Reset 1 Input

RSTIN2 Reset 2 Input

RST Reset Output (Open Drain)

WDI Watchdog Input

A Bank Select Input

EChip Enable Input

EX External Chip Enable Input

GOutput Enable Input

WWRITE Enable Input

E1CON RAM Chip Enable 1 Output

E2CON RAM Chip Enable 2 Output

IRQ/FT Int/Freq Test Output (Open Drain)

Vccsw VCC Switch Output

VOUT Supply Voltage Output

VCC Supply Voltage

VSS Ground

NC Not Connected internally

M48T212Y, M48T212V

6/32

Figure 3. SOIC Connections

AI03020

VSS

E1CON

VOUT

VCC

M48T212Y

M48T212V

NC EX

VCCSW

WDI

E2CON DQ7

DQ5DQ0

DQ1 DQ3

DQ4

DQ6

RSTIN2

RST

RSTIN1

DQ2

IRQ/FT

7/32

M48T212Y, M 48T212V

Figure 4. Hardware Hookup

Note: 1. See descri ption in Po wer Supply Deco upl i ng and Und ershoot Protection.

2. T races conne cti ng E 1CON and E2CON to external SRAM should be as short as possible.

3. If th e seco nd chip en abl e pin (E2) is unuse d, it should be t i ed to VOUT.

AI03046

A0-A3

DQ0-DQ7

VCC

WDI

RSTIN1

RSTIN2

VSS

E2(3)

VCC

A0-Axx

0.1µF

5V/3.3V

E2CON

RST

IRQ/FT

M48T212Y/V

CMOS

SRAM

VOUT

VCC

CMOS

SRAM

E1CON Note 2

MOTOROLA

MTD20P06HDL

VCCSW

1N5817(1)

A0-A18

A0-Axx

E2(3)

M48T212Y, M48T212V

8/32

OPERATION

Automatic backup and write protection for an ex-

ternal SRAM is provided through VOUT, E1CON

and E2CON pins. (Users are urged to insure that

voltage specifications , for both the SUPERVI SOR

chip and exte rnal SRAM chosen, are similar). The

SNAPHAT® containing the lithium energy source

used to permanently power the real time clock is

also used to retain RAM data in the absence of

VCC power through the VOUT pin.

The chip enable outputs to RAM (E1CON and

E2CON) are controlled during power transients to

prevent dat a corruption. The dat e is autom at ically

adjusted for months with less than 31 days and

corrects for leap years (v alid until 2100) . The inter-

nal watchdog timer provides program ma ble alarm

windows.

The nine clock bytes (Fh-9h and 1h) are not the

actual clock counters, they are memory locations

consisting of BiPORT™ READ/WRITE memory

cells within the static RAM array. Clock circuitry

updates the clock bytes with current information

once per second. T he inform ation c an be ac cess-

ed by the user in the same manner as any other lo-

cation in the static memory array.

Byte 8h is the clock control register. This byte con-

trols user access to the clock information and also

stores the clock calibration setting. Byte 7h con-

tains the watchdog timer setting. The watchdog

timer can generate either a reset or an interrupt,

depending on the state of the W atchdog Stee ring

Bit (WDS). Bytes 6h-2h include bits that, when

programmed, provide for clock al arm functionality.

Alarms are activated when the register content

matches the month, date, hours, minutes, and

seconds of the clock registers. Byte 1h contains

century information. Byte 0h contains additional

flag information pertaining to the watchdog timer,

alarm and battery status.

The M48T212Y/V also has its own Power-Fail De-

tect circuit. This control circuitry constantly moni-

tors the supply voltage for an out of tolerance

condition. When VCC is out of toler ance, the circuit

write protects the TIMEKEEPER® register data

and external SRAM , providing data s ecurity in the

midst of unpredictable system operation. As VCC

falls bel o w V SO, the control circuitry automatically

switches to the battery, maintaining data and clock

operation until valid power is restored.

Address Decoding

The M4 8T212 Y/V acc om mod ates 4 addre ss l ines

(A3-A0) which allow access to the sixteen bytes of

th e TIMEKEEPER cl o ck registe r s. All T IMEKEEP-

ER registers reside in the SUPERVISOR chip it-

self. All TIMEKEEPER registers are accessed by

enabling E (Chip Enabl e).

Table 2. Operating Modes

No te: X = VIH or VIL; VSO = Battery Back- up Switchover Vol tage

1. See Table 14., page 25 for details.

Table 3. Truth Table for SRAM Bank Select

No te: X = VIH or VIL; VSO = Battery Back- up Switchover Vol tage

1. See Table 14., page 25 for details.

Mode VCC E G W DQ7-DQ0 Power

Deselect 4.5V to 5.5V

3.0V to 3.6V

VIH X X High-Z Standby

WRITE VIL XVIL DIN Active

READ VIL VIL VIH DOUT Active

READ VIL VIH VIH High-Z Active

Deselect VSO to VPFD (min)(1) X X X High-Z CMOS Standby

Deselect ≤ VSO(1) X X X High-Z Battery Back-Up

Mode VCC EX AE1CON E2CON Power

Select 4.5V to 5.5V

3.0V to 3.6V

Low Low Low High Active

Low High High Low Active

Deselect High X High High Standby

Deselect VSO to VPFD (min)(1) X X High High CMOS Standby

Deselect ≤ VSO(1) X X High High Ba ttery Back -Up

9/32

M48T212Y, M 48T212V

Figu re 5. Chi p E na b le C o nt rol and Ba nk Selec t Tim i ng

Table 4. Chip Enable Control and Bank Select Characteristics

Symbol Parameter

M48T212Y M48T212V

Unit–70 –85

Min Max Min Max

tEXPD EX to E1CON or E2CON (Low or High) 10 15 ns

tAPD A to E1CON or E2CON (Low or High) 10 15 ns

AI02639

tEXPD tAPD

tEXPD

E1CON

E2CON

M48T212Y, M48T212V

10/32

READ Mode

The M48T212Y/V executes a READ cycle when-

ever W (WRITE Enable) is high and E (Chip En-

able) is low. The unique address specified by the

address inputs (A3-A0) defines which one of the

on-chip TIMEKEEPER® registers is to be access-

ed. When the address presented to the

M48T212Y/V is in the range of 0h-Fh, one of the

on-board TIMEKEEPER registers i s accessed and

valid da ta w ill be available to the e igh t dat a ou tpu t

drivers within tAVQV after the address input signal

is stable, providing that the E an d G access times

are also satisfied.If they are not, then data access

must be measured from the latter occ urring signal

(E or G) and the limiting pa rameter is e ither tELQV

for E or tGLQV for G rather than the address access

time.

When EX input is low, an e xternal S RA M location

will be s ele c t ed .

Note: Care should be taken to avoid taking both E

and EX low simultaneously to avoid bus conten-

tion.

Figure 6. READ Cycle Timing : RTC Control Signal Wavefor m s

Note: EX is as sumed High.

Table 5. READ Mode AC Characteristics

Note: 1. Valid for Am bi ent Op eratin g T em perature: TA = 0 to 7 0°C or –4 0 to 85°C; VCC = 4.5 to 5. 5 V or 3.0 t o 3.6V (except wh ere noted ) .

2. CL = 5pF.

Symbol Parameter(1)

M48T212Y M48T212V

Unit–70 –85

Min Max Min Max

tAVAV Read Cycle Time 70 85 ns

tAVQV Address Valid to Output Valid 70 85 ns

tELQV Chip Enable Low to Output Valid 70 85 ns

tGLQV Output Enable Low to Output Valid 25 35 ns

tELQX(2) Chip Enable Low to Output Transition 5 5 ns

tGLQX(2) Output Enable Low to Output Transition 0 0 ns

tEHQZ(2) Chip Enable High to Output Hi-Z 20 25 ns

tGHQZ(2) Output Enable High to Output Hi-Z 20 25 ns

tAXQX Address Transition to Output Transition 5 5 ns

AI02640

DQ7-DQ0

DATA OUT

VALID

ADDRESS

tAVAV

tELQV

tAVAV tAVAV

READ READ WRITE

DATA IN

VALID

DATA OUT

VALID

tAVQV tWHAXtAVWL

tELQX

tGLQV

tGHQZ

tWLWH

tAXQXtGLQX

11/32

M48T212Y, M 48T212V

WRITE Mode

The M48T212Y/V is in the WRITE Mode whenever

W (WRITE Enable) and E (Chip Enable) are in a

low state aft er the addres s inputs are stable. The

start of a WRITE is referenced fro m the la tter oc-

curring falling edge of W or E . A WRITE is termi-

nated by the earlier rising edge of W or E. The

addresses must be held valid throughout the cy-

cle. E or W must return high for a minimum of tE-

HAX from Chip Enable or tWHAX from WRITE

Enable prior to the initiation of another READ or

WRITE cycl e. Da ta-in must be vali d tDVWH prior to

the end of WRITE and remain valid for tWHDX af-

terward.

G should be kept high during WRITE cycles to

avoid bus contention; although, if the output bus

has b een activated by a l ow o n E and G a low on

W will dis a ble the o utput s tWLQZ af t er W falls.

When E is low during the WRITE, one of the on-

board TIMEKEEPER® registers will be selected

and data will be written into t he device. When EX

is low (and E is high) an external SRAM location is

selected.

Note: Care should be taken to avoid taking both E

and EX low simultaneously to avoid bus conten-

tion.

Figure 7. WRITE Cycle Timing: RTC Control Signal Waveforms

Note: EX is as sumed High.

AI02641

DQ0-DQ7

DATA IN

VALID

ADDRESS

tAVAV

tAVEH

tAVAV tAVAV

WRITE WRITE READ

DATA OUT

VALID

DATA OUT

VALID

tAVWH

tAVQV

tWLWH

tWHDX

tWHAX

tWHQX tWLQZ

tDVWH

tGLQV

tEHQZ tDVEH

DATA IN

VALID

tELEH tEHAX

tAVEL

tEHDX

tAVWL

M48T212Y, M48T212V

12/32

Table 6. WRITE Mode AC Characteristics

Note: 1. Valid for Am bi ent Op eratin g T em perature: TA = 0 to 7 0°C or –4 0 to 85°C; VCC = 4.5 to 5. 5 V or 3.0 t o 3.6V (except wh ere noted ) .

2. CL = 5pF

3. If E goes low simultaneously with W going low, the output s remain in the high im peda nce stat e.

Symbol Parameter(1)

M48T212Y M48T212V

Unit–70 –85

Min Max Min Max

tAVAV Write Cycle Time 70 85 ns

tAVWL Address Valid to Write Enable Low 0 0 ns

tAVEL Address Valid to Chip Enable Low 0 0 ns

tWLWH Write Enable Pulse Width 45 55 ns

tELEH Chip Enable Low to Chip Enable High 50 60 ns

tWHAX Write Enable High to Address Transition 0 0 ns

tEHAX Chip Enable High to Address Transition 0 0 ns

tDVWH Input Valid to Write Enable High 25 30 ns

tDVEH Input Valid to Chip Enable High 25 30 ns

tWHDX Write Enable High to Input Transition 0 0 ns

tEHDX Chip Enable High to Input Transition 0 0 ns

tWLQZ(2,3) Write Enable Low to Output High-Z 20 25 ns

tAVWH Address Valid to Write Enable High 55 65 ns

tAVEH Address Valid to Chip Enable High 55 65 ns

tWHQX(2,3) Write Enable High to Output Transition 5 5 ns

13/32

M48T212Y, M 48T212V

Data Retention Mode

With valid VCC applied, the M48T212Y/V can be

accessed as described above with READ or

WRITE cycles. Should the supply voltage decay,

the M48T212Y /V will autom atically deselect , write

protecting itself (and any external SRAM) when

VCC falls between VPFD (max) and VPFD (min).

This is accomplished by internally inhibiting ac-

cess to the clock registers via the E signal. A t this

time, the Reset pin (RST) is driven ac tive and will

remain a ctive un t il V CC returns to nominal levels.

External RAM access is inhibited in a similar man-

ner by forcing E1CON and E2CON to a hi gh level.

This level is within 0.2 volts of the VBAT. E1CON

and E2CON will remain at this level as long as VCC

remains at an out-of-tolerance condition.

When VCC falls below battery back-up switchover

voltage (VSO), power input is switched from the

VCC pin to the SNAPHAT® battery and the clock

registers and external SRAM are maintained from

the attached battery supply. All outputs become

high impedanc e. The VOUT pin is cap able of sup-

plying 100µA of current to the attached memory

with less than 0.3V drop under this cond ition. On

power up, when VCC returns to a nominal value,

write protection continues for 200ms (max) by in-

hibiting E1CON or E2CON.

The RST signal also remains active during this

time (see Figure 15., pag e 26).

Note: Most low power SRAMs on the market to-

day can be used with the M48T212Y/V TIME-

KEEPER® SUPERVISOR. There are, however

some criteria which should be used in making the

final choice of an SRAM to use. The SRAM must

be designed in a wa y wh ere the chip enabl e input

disables all other inputs to th e S RAM. Thi s allows

inputs to the M48T212Y/V and SRAMs to be

“Don't care” once VCC fall s belo w VPFD(m in). T he

SRAM should also guarantee data retention down

to V CC = 2.0V . The chi p enable acc ess tim e m ust

be sufficient to meet the system needs with the

chip enable output propagation del ays included.

If the SRAM includes a second chip enable pin

(E2), this pin should be tied to VOUT.

If data rete ntion l ifetime is a c ritical pa rameter f or

th e syste m, it i s im portant t o revi ew the dat a rete n-

tion current specifications for the particular

SRAMs being evaluated. Most SRAMs specify a

data retention current at 3.0V. Manufacturers gen-

erally specify a ty pical condition for room temper-

ature along with a wors t case con dition (gen erally

at elevated temperatures). The system level re-

quirements will determine the choice of which val-

ue to use.

The data retention current value of the SRAMs can

then be added to the IBAT value of the M48T212Y/

V to determine the total current requirements for

data retention. The available battery capacity for

the SNAPHAT® of your choice can then be divided

by this current to determine the amount of data re-

tention available (see Table 20., page 30).

For a further more detailed review of lifetime calcu-

lations, please see Application Note AN1012.

M48T212Y, M48T212V

14/32

C LOCK OPERA T ION

TIMEKEEPER® Registers

The M48T212Y/V offers 16 internal registers

which contain TIMEKEEPER®, Alarm, Watchdog,

Flag, and Cont rol data. The se registers a re mem-

ory l ocations which contain external (user accessi-

ble) and internal copies of the data (usually

referred to as BiPORT™ TIMEKEEPER c e ll s).

The external copies are independent of internal

functions except that t hey are updated periodicall y

by the simultaneous transfer of the incremented

in te r n a l copy. TI MEKEEPER and Alar m R e gi sters

store data in BCD. Control, Watchdog and Flags

Registers store data in Binary Format.

Reading the Clock

Updates to the TIMEKEEPER registers should be

halted before clock data is read to prevent reading

data in transition. The BiPORT TIMEKEEPER

cells in the RAM array are only data registers and

not the actual clock counters, so updating the reg-

isters can be halted without distur bing the cloc k it-

self.

Updating is halted when a '1' is written to the

READ Bit , D6 in the Control Register (8h). As long

as a '1' remains in that position, updating is halted.

After a halt is issued, the registers reflect the

count; that is, the day, date, and time that were

current at the moment the halt command was is-

sued.

All of the TIMEKEEPER registers are updated si-

multaneously. A halt will not interrupt an update in

progress. Updating occurs 1 second after the

READ Bit is reset to a '0.'

S ettin g the C l ock

Bit D7 of the Control Register (8h) is the WRITE

Bit. Setting the WRITE Bit to a '1,' like the READ

Bit, halts updates to the TIMEKEEPER registers.

The user can then load them with the correct day,

date, and time data in 24 hour BCD format (see

Table 7., page 15).

Resetti n g t he WRITE Bi t to a ' 0' then transf e rs th e

values of all time registers (Fh-9h, 1h) to the actual

TIMEKEE PER counters and allows normal opera-

tion to resume. After the WRITE Bit is reset, the

next clock update will occur one second later.

Note: Upon power-up following a power failure,

the READ Bit will automatically be set to a '1.' This

will prevent the clock from updating the TIME-

KEEPER registers, and will allow the user to read

the exact time of the power-down event.

Re settin g th e R EAD Bit to a ' 0 ' will a ll o w the cl o c k

to update these registers with the current time.

The WRITE Bit will be reset to a '0' upon power-up.

Stopping and Starting the Oscillator

The oscillator may be stopped at any time. If the

device is going to spend a significant amount of

time on the shelf, the oscillator can be turned off to

minimize current drain on the battery. The STOP

Bit is located at Bit D7 within the S econds Register

(9h). Setting it to a '1' stops the oscillator. When re-

set to a '0,' the M48T212Y/V oscillator starts within

one second.

Note: It is not necessary to set the WRITE Bit

when setting or resetting the FREQUENCY TES T

Bi t ( F T) or th e S TOP Bit (S T) .

15/32

M48T212Y, M 48T212V

Table 7. TIMEKE EPER ® Re g ister Map

Keys : S = Sign Bit

FT = Frequency Test Bit

R = READ Bit

W = WRI T E Bi t

ST = Stop Bit

0 = Must be set to '0'

BL = B at tery Low Flag (Rea d only)

BMB0-BMB4 = Watchdog Multiplie r Bits

AFE = Alarm Flag Enable Flag

RB 0-RB1 = Watchdog R esolut ion Bit s

WDS = Watchdog Steeri ng Bit

ABE = Alarm in Bat te ry Back-Up Mod e Enable Bit

RP T 1-RPT 5 = A l arm Repe at Mode Bits

WDF = Watchdog Fla g (Read only )

AF = A l arm F l ag (Read only)

Y = '1' or '0'

Address Function/Range

BCD Format

D7 D6 D5 D4 D3 D2 D1 D0

Fh 10 Years Year Year 00-99

Eh 0 0 0 10M Month Month 01-12

Dh 0 0 10 Date Date: Day of Month Date 01-31

Ch 0 FT 0 0 0 Day of Week Day 01-7

Bh 0 0 10 Hours Hours (24 Hour Format) Hours 00-23

Ah 0 10 Minutes Minutes Min 00-59

9h ST 10 Seconds Seconds Sec 00-59

8h W R S Calibration Control

7h WDS BMB4BMB3BMB2BMB1BMB0 RB1 RB0Watchdog

6h AFE 0 ABE Al 10M Alarm Month A Month 01-12

5h RPT4 RPT5 AI 10 Date Alarm Date A Date 01-31

4h RPT3 0 AI 10 Hour Alarm Hour A Hour 00-23

3h RPT2 Alarm 10 Minutes Alarm Minutes A Min 00-59

2h RPT1 Alarm 10 Seconds Alarm Seconds A Sec 00-59

1h 1000 Year 100 Year Century 00-99

0hWDFAFYBLYYYYFlag

M48T212Y, M48T212V

16/32

Setting the Alarm Clock

Address locations 6h-2h contain the alarm set-

tings. The alarm can be configured to go off at a

prescribed time on a specific month, date, hour,

minute, or second or repeat every year, month,

day, hour, minute, or second. It can also be pro-

grammed to go of f while the M48T212Y/V is in the

battery back-up to serve as a system wake-up cal l.

Bits RPT5-RPT1 put the alar m in the repeat mode

of operation. Tabl e 8 shows the poss ible configu-

rations. Codes not listed in the table default to the

once per secon d m ode to quickly alert t he user of

an incorrect alarm setting.

Note: User must transition address (or toggle chip

enable) to see Flag Bit change.

When the clock information matches the alarm

clock settings based on the m atch criteria defined

by RPT5-RPT1, the AF (Alarm Flag) is set.

If AFE (Alarm Flag Enable) is also set, the alarm

condition activates the IRQ/FT pin. To disable

alarm, write '0' to the Alarm Date registers and

RPT1-5 . T h e IRQ /FT output is cleared by a READ

to the Flags Register as shown in Figure 8. A sub-

sequent READ of the Flags Regist er is necessary

to see that the value of the Alarm Flag has been

re set to '0 . '

The IRQ/FT pin can also be activated in the bat-

tery back-up mode. The IRQ/FT will go low if an

alarm occurs and both ABE (Alarm in Battery

Back-up Mode Enable) and AFE are set. The ABE

and AFE Bits are reset during power-up, therefore

an alarm generated during power-up will only set

AF. The user can read t he Flag Register at syst em

boot-up to determine if an alarm was generated

while the M48T212Y/V was in the deselect mode

during power-up. Figure 9., page 17 ill ustrat es the

back-up mode alarm timing.

Figure 8. Alarm Interrupt Reset Waveforms

Table 8. Alarm Repeat Modes

RPT5 RPT4 RPT3 RPT2 RPT1 Alarm Setting

11111 Once per Second

11110 Once per Minute

11100 Once per Hour

11000 Once per Day

10000 Once per Month

00000 Once per Year

AI03021

A0-A3

ACTIVE FLAG BIT

ADDRESS 0h

IRQ/FT

HIGH-Z

1h Fh

17/32

M48T212Y, M 48T212V

Figure 9. Back-up Mode Alarm Wavefo rms

Watchdog Timer

The watchdog timer can be used to detect an out-

of-control microprocessor. The us er program s the

watchdog timer by setting the desired amount of

time-out into the Watchdog Register, address 7h.

Bits BMB4-BMB0 store a binary mul tiplier and the

two lower-order bits RB1-RB0 select the resolu-

tion, where 00=1/16 second, 01=1/4 second, 10=1

second, and 11=4 seconds. The amount of time-

out is then determined to be the multiplication of

the five-bit multiplier value with the resolution. (For

example: writing 00 001110 in the Wa tchdo g Reg-

ister = 3*1 or 3 seconds).

Note: Accuracy of timer is within ± the selected

resolution.

If the processor does not reset the t imer within the

specified period, the M48T212Y/V sets the WDF

(Watchdog Flag) and generates a watchdog inter-

rupt or a microprocessor reset. WDF is reset by

reading the Flags Register (Address 0h).

The most significa nt bit of the Watchdog Regi ster

is the Watchdog S teering Bit (WDS). When set to

a '0.' the watchdog will activate the IRQ/FT pin

when timed-out. When WDS is set to a '1,' the

watchdog will output a negat ive pul se on th e RST

pin for 40 to 200 ms. The Watchdog register, AFE,

ABE, and FT Bits w ill reset t o a '0' at t he end of a

Watchdog time-out when the WDS Bit is set to a

'1.'

The watchdog timer can be reset by two methods:

1. a transition (high-to-low or low-to-high) can be

applied to the Watchdog Input pin (WDI) or

2. the microprocessor can perform a WRITE of

the Watchdog Register.

The time-out period then starts over. The WDI pin

should be tied to VSS if not used. The watchdog

will be reset on each transition (edge) seen by the

WDI pin. In the order to perform a software reset

of the watchdog timer, the original time-out period

can be written into the Watchdog Register, effec-

tively restarting the count-down cycle.

Should the watchdog timer time-out, and the WDS

Bit is programmed to output an interrupt, a value of

00h needs to be written to the Watchdog Regi ster

in order to clear the IRQ/FT pi n. This will also dis-

able the watchdog function until it is again pro-

grammed correctly. A READ of the Flags Register

will reset the Watchdog Flag (Bit D7; Register 0h).

The watchdog function is automatically disabled

upon power-down and the Watchdog Register is

cleared. If the watchdog func tion is set to output to

the IRQ /FT pin and the frequency test function is

activated, the watchdog or alarm function prevails

and the frequency test function is denied.

AI03622

VCC

IRQ/FT

HIGH-Z

VPFD (max)

VPFD (min)

AFE Bit/ABE Bit

AF Bit in Flags Register

HIGH-Z

tREC

M48T212Y, M48T212V

18/32

VCC Switch Output

Vccsw output goes low when VOUT switches to

VCC turning on a customer supplied P-Channel

MOSFET (see Figure 4., page 7). The Motorola

MTD20P06HDL is recommended. This MOSFET

in turn con nects VOUT to a s eparate supply when

the current requirement is greater than IOUT1 (see

Table 14., page 25). This output may also be used

simply to indicate the status of the internal battery

switchover co mpa rator, which cont rols the s ource

(VCC or battery) of the VOUT output.

Power-on Reset

The M48T212Y/V continuously monitors VCC.

When VCC falls to the power fail detect trip point,

the RST pulls low ( open drain) and remains low on

power-up for trec after VCC passes VPFD (max).

The RST pin is an open drain output and an appro-

priate pull-up resist or to VCC shoul d be cho se n to

control rise time.

Note: If the RST output is fed back into either of

the R ST IN inputs (for a microprocessor with a bi-

directional reset) then a 1kΩ (max) pull-up resistor

is recommended.

Reset Inputs (RSTIN1 & RSTIN2)

The M48T212Y/V provides two independent in-

puts which can generate an output reset. The du-

ration and function of these resets is identical to a

reset generated by a power cycle. Table 9 and Fig-

ure 10 i llust rate the AC re set ch aracteri stics of thi s

function. During the time RST is enabled (tR1HRH

& tR2HRH), the Reset Inputs are ignored.

Note: RSTIN1 and RSTIN2 are each internally

pulled up to VCC through a 100KΩ resistor .

Figure 10. (RSTIN1 & RSTIN2) Timing Wave forms

Table 9. Reset AC Characteristics

Note: 1. Valid for Am bi ent Op eratin g T em perature: TA = 0 to 7 0°C or –4 0 to 85°C; VCC = 4.5 to 5. 5 V or 3.0 t o 3.6V (except wh ere noted ) .

2. Pulse width less than 50ns will result in no RESET (fo r noise im m unity ).

3. Pulse width less than 20ms will result in no RESET (for n oi se imm unity).

4. CL = 5pF (see Figure 14., page 24).

Symbol Parameter(1) Min Max Unit

tR1(2) RSTIN1 Low to RSTIN1 High 200 ns

tR2(3) RSTIN2 Low to RSTIN2 High 100 ms

tR1HRH(4) RSTIN1 High to RST High 40 200 ms

tR2HRH(4) RSTIN2 High to RST High 40 200 ms

AI02642

RSTIN1

RST

RSTIN2

tR1

tR1HRH

tR2

tR2HRH

19/32

M48T212Y, M 48T212V

Ca libra t ing t he Clock

The M48T212Y/V is driven by a quartz controlled

oscillator with a nominal frequency of 32,768 Hz.

The devices are tested not to exceed ±35 ppm

(parts per million) oscillator frequency error at

25°C, which equates to about ±1.53 minutes per

month (see Figure 11., page 21). When the Cali-

bration circuit is properly employed , accuracy im-

proves to better than +1/–2 ppm at 25°C.

The oscillation rate of crystals changes with tem-

perature. The M48T212Y/V design employs peri-

odic counter correction. The calibration circuit

adds or subtracts counts from the osci llator divider

circuit at the divide by 256 stage, as shown in Fig-

ure 12., page 21. The number of times pulses

which are blanked (subtracted, negative calibra-

tion) or split (added, positive calibration) depends

upon the value loaded into the five Calibration bits

found in the Control Register. Adding counts

speeds the clock up, sub tracting counts slows the

clock down.

The Calibration bits occupy the five lower-order

bits (D4-D0) i n the Control Register 8h. These bits

can be set to repres ent any value between 0 and

31 in binary form. Bit D5 is a Sign Bit; '1' indicates

positive calibration, ‘0' indicates negative calibra-

tion. Calibration occurs within a 64 minute cycle.

The first 62 minutes in the cycle may, once per

minute, have one second either s hort ened by 128

or lengthened by 256 oscillator cycles.

If a binary ‘1' is loaded into the register, only the

first 2 minutes in the 64 minute c ycle will be modi-

fied; if a binary 6 is loaded, the first 12 will be af-

fected, and so on.

Therefore, each calibration step has the effect of

adding 512 or subtracting 256 osc illator cycles for

every 125,829,120 actual oscillator cycles, that is

+4.068 or –2.034 ppm of adjustment per calibra-

tion step i n t he cal ibration register. Ass um ing that

the oscillator is running at exac tly 32,768 Hz, each

of the 31 increm ents in the Calibration byte wou ld

represent +10.7 or –5.35 seconds per month

which corresponds to a total range of +5.5 or –2.75

minutes per month.

Two methods are available for ascertaining how

much calibration a given M48T212Y/V may re-

quire. The first involves setting the clock , letting it

run for a month and comparing it to a known accu-

rate reference and recording deviation over a fixed

period of time. Calibration values, including the

number of s econds los t or gained in a given peri-

od, can be found in Application Note, “AN934,

TIMEKEEPER® Calibration.”

This allows the designer to give the end user the

ability to calibrate the clock as the environment re-

quires, even if the final product is packaged in a

non-user serviceable enclosure. The designer

could provide a simple utility that accesses the

Calibration byte.

The second approach is better suited to a manu-

facturing environment, and involves the use of the

IRQ/FT pin. The pin will t oggle at 512Hz, when the

Stop Bit (ST, D7 of 9h) is '0,' the Frequency Test

Bit (FT, D6 of Ch) is '1,' the Alarm Flag Enabl e Bit

(AFE, D7 of 6h) is '0,' and t he Watchdog S teering

Bit (WDS, D7 of 7h) is '1' or the Watchdog Register

(7h=0) is reset.

Any deviation from 512 Hz indicates the degree

and direction of oscillator frequency shift at the test

temperature. For example, a reading of

512.010124 Hz would indicate a +20 ppm oscilla-

tor frequency error, requiring a –10 (WR001010)

to be loaded into the Calibration Byte for correc-

tion. Note that setting or cha nging the Cali bration

Byte does not affect the Frequency test output fre-

quency.

The IRQ/FT pin is an open d rain output which re-

quires a pull-up resistor to VCC for proper opera-

tion. A 500-10kΩ resistor is recommended in order

to control the rise time. The FT Bit is cleared on

power-up.

M48T212Y, M48T212V

20/32

Batt ery Lo w W arn in g

The M48T212Y/V automatically performs battery

voltage monitoring upo n power-up and at factory-

programmed time intervals of approximately 24

hours. The Battery Low (BL) Bit, Bit D4 of Flags

is found to be less than approximately 2.5V. The

BL Bit will r emain asserted until completion of bat-

tery replacement and subsequent battery low

monitoring tests, either during the next power-up

sequence or the next scheduled 24-hour interval.

If a battery low is generated dur ing a power-up se-

quence, this indicates that the battery i s below ap-

proximately 2.5 volts and may not be able to

maintain data integrity in the SRAM. Data should

be considered suspect and verified as correct. A

fresh battery should be installed.

If a battery low indication is generated during the

24-hour interval check, this indicates that the bat-

tery is n ear end o f life. However, data i s not com-

promised due to the fact that a nominal VCC is

supplied. In order to insure data integrity during

subsequent pe riods of bat tery back-up m ode, the

battery should be replaced. The SNAPHAT® bat-

tery/crystal top should be replaced with VCC pow-

ering the device to avoid data loss.

Note: this will cause the clock to lose time du ring

the time interval the battery c rystal is removed.

The M48T212Y/V only monitors the battery when

a nominal VCC is applied to the device. Thus appli-

cations which require extensive durations in the

battery back-up mode should be powered-up peri-

odically (at least once every few mont hs) in order

for this techniqu e to be beneficial.

Additionally, if a battery low is indicated, data in-

tegrity should be verified upon power-up via a

checksum or other technique.

In it ia l P o we r - on Defau l ts

Upon application of power to the device, the fol-

lowing register bits are set to a ’0' state: WDS,

BMB0-BMB4, RB0-RB1, AFE, ABE, W, and FT

(see Tabel 10).

Table 10. Default Values

No te: 1. WDS, BMB0 -BMB 4, RB0, RB1.

2. St at e of other co ntrol bits undefi ned.

3. St at e of other co ntrol b its remains unchan ged.

4. As suming the se bits set to '1' prior t o power-down.

Condition W R FT AFE ABE WATCHDOG

Initial Power-up

(Battery Attach for SNAPHAT)(2) 00000 0

RESET (3) 00000 0

Power-down (4) 01011 0

Subsequent Power-up 01000 0

21/32

M48T212Y, M 48T212V

Figure 11. Crys tal Accuracy Acro ss Tem p eratur e

Figu re 12 . Cal ib rat i on W avef orm

AI00999

–160

0 10203040506070

Frequency (ppm)

Temperature °C

80–10–20–30–40

–100

–120

–140

–40

–60

–80

–20

∆F= -0.038 (T - T

)

± 10%

Fppm

= 25 °C

AI00594B

NORMAL

POSITIVE

CALIBRATION

NEGATIVE

CALIBRATION

M48T212Y, M48T212V

22/32

VCC Noise And Negative Go ing Transients

ICC transients, including those produced by output

switching, can produce voltage fluctuations, re-

sulting in spikes on the VCC bus. These transients

can be reduced if capacitors are used to store en-

ergy which stabilizes the VCC bus. The energy

stored in the bypass capacitors will be released as

low going spikes are generated or energy will be

absorbed when overshoots occur. A ceramic by-

pass capacitor v alue of 0.1µF (as shown in Figure

13) is recomm ended in order to provide the need-

ed filtering.

In addition to t ransients that are caused by normal

SRAM operation, power cycling can generate neg-

ative voltage s pikes on VCC that drive it to values

below VSS by as much as one volt. These negative

spikes can cause data corruption in the SRAM

while in battery backup mode. To protect from

these voltage spikes, STMicroelectronics recom-

mends connecting a schottky diode from VCC to

VSS (cathode connected to VCC, anode to VSS).

Schottky diode 1N5817 is recommended for

through hole and MBRS120T3 is recommended

for surface mount .

Figure 13. Supply Voltage Protection

AI02169

VCC

0.1µF DEVICE

VCC

VSS

23/32

M48T212Y, M 48T212V

MAXI MUM RA T IN G

Stressing the device ab ove t he rating l isted in t he

“Absolute Maximum Ratings” table may cause

permanent damage to the device. These are

stress ratings only and operation of the device at

these or any other conditions above those indic at-

ed in the Operating sections of this specification is

not impl ied. Exposure to Absol ute Max imum Ra t-

ing conditions for extended periods may affect de-

vice reliability. Refer also to the

STMicroelectronics S URE P rogram and other rel-

evant quality documents.

Table 11. Absolute Maximum Ratings

Note: 1. F or SO pa ck age, st andar d (SnPb) lead finis h: Re flow at peak tem perature of 225°C (t ot al thermal budget not to exceed 180°C for

between 90 to 15 0 s e c o nds).

2. F or SO package, Lead-f ree ( Pb-free) l ead fin i sh: Reflow at p eak tem pera ture of 260 °C (tot al thermal budge t n ot to exceed 245°C

for greater than 30 seconds).

CAUTION: Negativ e undershoots bel ow –0.3V are not allowed on any pin while i n th e Batte ry Back -up m ode.

CAUTION: Do NOT wave sol d er SOIC t o avoid damagi n g S NA PHA T s o c kets.

Symbol Parameter Value Unit

TAAmbient Operating Temperature 0 to 70 °C

TSTG Storage Temperature SNAPHAT®–40 to 85 °C

SOIC –55 to 125 °C

TSLD(1,2) Lead Solder Temperature for 10 seconds 260 °C

VIO Input or Output Voltage –0.3 to VCC + 0.3 V

VCC Supply Voltage M48T212Y –0.3 to 7.0 V

M48T212V –0.3 to 4.6 V

IOOutput Current 20 mA

PDPower Dissipation 1 W

M48T212Y, M48T212V

24/32

DC AND AC PA RAMETERS

This section summarizes the operating and mea-

surement conditions, as well as the DC and AC

characteristics of the device. The parameters in

the following DC and AC Charac teristic tables are

derived from tests pe rformed unde r the Measure-

ment Condition s listed in the relevant tables. De-

signers should check that the operating conditions

in their projects match the measurement condi-

tions when using the quoted parameters.

Table 12. D C and AC Measurem ent Conditions

Note: Output High Z is def i ned as the point where data i s no longer dri ven.

Fi gure 14 . AC Te sting Load Circui t

Note: Excluding open-drain output pins; 50pF for M48T212V.

1. DQ0-DQ7

2. E1CON an d E2 CON

Table 13. Capacitanc e

Note: 1. Ef fective capacit ance measured with po wer su pply at 5V (M 48T212Y) or 3.3 V (M48T212V); sam pl ed only, not 100 % t ested.

2. At 25°C, f = 1MHz .

3. Outputs deselected.

Parameter M48T212Y M48T212V

VCC Supply Voltage 4.5 to 5.5V 3.0 to 3.6V

Ambient Operating Temperature Grade 1 0 to 70°C 0 to 70°C

Grade 6 –40 to 85°C –40 to 85°C

Load Capacitance (CL)100pF 50pF

Input Rise and Fall Times ≤ 5ns ≤ 5ns

Input Pulse Voltages 0 to 3V 0 to 3V

Input and Output Timing Ref. Voltages 1.5V 1.5V

AI03239

CL = 100pF or 5pF

(1)

CL = 30 pF

(2)

645Ω

DEVICE

UNDER

TEST

1.75V

CL includes JIG capacitance

Symbol Parameter(1,2) Min Max Unit

CIN Input Capacitance 10 pF

COUT(3) Input/Output Capacitance 10 pF

25/32

M48T212Y, M 48T212V

Table 14. DC Characteristics

Note: 1. Valid for Am bi ent Op eratin g T em perature: TA = 0 to 7 0°C or –4 0 to 85°C; VCC = 4.5 to 5. 5 V or 3.0 t o 3.6V (except wh ere noted ) .

2. RSTIN1 and RSTI N2 internally pulle d-up t o VCC through 100KΩ resistor. WDI internally pulled-down to VSS through 100KΩ resistor.

3. Outputs deselected.

4. IBAT (OSC ON) = Industrial Tem perat ure Ra nge - Gra de 6 dev i ce.

5. F or IRQ /FT & RST pins (Open Drain).

6. Conditione d out puts (E 1CON - E2CON) ca n only s ustai n CM OS le akag e currents in the ba tt ery back-up mode. H i gher leakage cur -

rents will reduce battery life.

7. External SRAM must match TIMEKEEPER® SU PERV ISOR chi p VCC specification.

Sym Parameter Test Condition(1)

M48T212Y M48T212V

Unit–70 –85

Min Typ Max Min Typ Max

ILI(2) Input Leakage Current 0V ≤ VIN ≤ VCC ±1 ±1 µA

ILO(3) Output Leakage Current 0V ≤ VOUT ≤ VCC ±1 ±1 µA

ICC Supply Current Outputs open 8 15 4 10 mA

ICC1 Supply Current (S tandby)

TTL E = VIH 53mA

ICC2 Supply Current (S tandby)

CMOS E = VCC –0.2 32mA

IBAT

Battery Current OSC ON

VCC = 0V

575 800 575 800 nA

Battery Current OSC

ON(4) 950 1250 950 1250 nA

Battery Current OSC

OFF 100 100 nA

VIL Input Low Voltage –0.3 0.8 –0.3 0.8 V

VIH Input High Voltage 2.2 VCC +

0.3 2.0 VCC +

0.3 V

VOL

Output Low Voltage IOL = 2.1mA 0.4 0.4 V

Output Low Voltage

(open drain) (5) IOL = 10mA 0.4 0.4 V

VOH Output High Voltage IOH = –1.0mA 2.4 2.4 V

VOHB(6) VOH Battery Back-up IOUT2 = –1.0µA 2.0 3.6 2.0 3.6 V

IOUT1(7) VOUT Current (Active) VOUT1 > VCC –0.3 100 70 mA

IOUT2 VOUT Current (Battery

Back-up) VOUT2 > VBAT –0.3 100 100 µA

VPFD Power-fail Deselect

Voltage 4.2 4.35 4.5 2.7 2.9 3.0 V

VSO Battery Back-up

Switchover Voltage 3.0 VPFD –

100mV V

VBAT Battery Voltage 3.0 3.0 V

M48T212Y, M48T212V

26/32

Figure 15. Power Down /U p Mode AC Waveform s

Table 15. Power Down/ Up Mod e AC Characteri stics

Note: 1. Valid for Am bi ent Op eratin g T em perature: TA = 0 to 7 0°C or –4 0 to 85°C; VCC = 4.5 to 5. 5 V or 3.0 t o 3.6V (except wh ere noted ) .

Symbol Parameter(1) Min Max Unit

tFVPFD (max) to VPFD (min) VCC Fall Time 300 µs

tFB VPFD (min) to VSS VCC Fall Time M48T212Y 10 µs

M48T212V 150 µs

tRVPFD (min) to VPFD (max) VCC Rise Time 10 µs

tRB VSS to VPFD (min) VCC Rise Time 1µs

trec VPFD (max) to RST High 40 200 ms

AI02638

VCC

INPUTS

RST

OUTPUTS

DON'T CARE

HIGH-Z

tFB

trectRB

VALID VALID

VPFD (max)

VPFD (min)

VSO

VALID VALID

VCCSW

27/32

M48T212Y, M 48T212V

P ACKAG E MECHANI CAL INFO RMATIO N

Figure 16. SOH44 – 44-lead Plastic Small Outline, SNAPHAT, Package Outline

No te : Drawing is not to scal e.

Table 16. SOH44 – 44-lead Plastic Small Outline, SNAPHAT , Package Mec han ical Data

Symb mm inches

Typ Min Max Typ Min Max

A 3.05 0.120

A1 0.05 0.36 0.002 0.014

A2 2.34 2.69 0.092 0.106

B 0.36 0.46 0.014 0.018

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e0.81– –0.032– –

eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

α0° 8° 0° 8°

N44 44

CP 0.10 0.004

SOH-A

LA1 α

M48T212Y, M48T212V

28/32

Figure 17. SH – 4-pin SNA PH AT Housing for 4 8 mAh Ba tter y & Cryst al, Package Outline

No te : Drawing is not to scal e.

Table 17. SH – 4-pi n SNAPHAT Housing for 48 mAh Batte ry & Cr ystal, Pac kag e Me ch. D ata

Symb mm inches

Typ Min Max Typ Min Max

A 9.78 0.385

A1 6.73 7.24 0.265 0.285

A2 6.48 6.99 0.255 0.275

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 14.22 14.99 0.560 0.590

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

SHTK-A

A1 A

29/32

M48T212Y, M 48T212V

Figure 18. SH – 4-pin SNAPHAT Housing for 120mAh Battery & Crystal, Package Outline

No te : Drawing is not to scal e.

Table 18. SH – 4-pin SNAPHAT Housi ng for 120mAh Battery & Crystal, Package Mech. Data

Symb mm inches

Typ Min Max Typ Min Max

A 10.54 0.415

A1 8.00 8.51 0.315 .0335

A2 7.24 8.00 0.285 0.315

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 17.27 18.03 0.680 .0710

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

SHTK-A

A1 A

M48T212Y, M48T212V

30/32

PART NUMBERING

Table 19. Ordering Information Example

Note: 1. T he SOIC package (SOH44 ) requires the SNA PH A T ® batter y package wh i ch is ord ered s eparat el y und er the part nu m ber

“M4Txx-BR12SH ” i n pl asti c tu be or “M4Txx -BR 12S HTR” in Tape & Re el form (s ee Tabl e 20).

Caution: Do not place the SNAPHAT battery package “M4Txx-BR12SH” in conductive foam as it will drain the lithiu m button-cell bat-

tery.

For other options, or for more information on any aspect of this device, please contact the ST Sales Office

nearest you.

Table 20. SNAPHAT® Bat t ery Tabl e

Example: M48T 212Y –70 MH 1 TR

Device Type

M48T

Supply and Write Protect Voltage

212Y = VCC = 4.5 to 5.5V; 4.2V ≤ VPFD ≤ 4.5V

212V = VCC = 3.0 to 3.6V; 2.7V ≤ VPFD ≤ 3.0V

Speed

–70 = 70ns (for M48T212Y)

–85 = 85ns (for M48T212V)

Package

MH(1) = SOH44

Tem pera ture Rang e

1 = 0 to 70°C

6 = –40 to 85°C

Shipping Method

blank = Tubes (Not for New Design - Use E)

E = Lead-free Package (ECO PACK®), Tubes

F = Lead-free Package (ECO PACK®), Tape & Reel

TR = Tape & Reel (Not for New Design - Use F)

Part Number Description Packag e

M4T28-BR12SH Lithium Battery (48mAh) SNAPHAT SH

M4T32 -BR1 2SH Lithiu m Battery (120m Ah) SNAP HAT SH

31/32

M48T212Y, M 48T212V

REVISION HI STORY

Table 21. Document Revi sion History

Date Rev. # Revision Details

October 1999 1.0 First Issue

01-Mar-00 2.0 Document Layout changed; Default Values table added (Table 10)

21-Apr-00 3.0 From Preliminary Data to Data Sheet

10-Nov-00 3.1 Table 16 changed

30-May-01 3.2 Changed “Controller” references to “SUPERVISOR”

10-Sep-01 4.0 Reformatted; added temp./voltage info. to tables (Table 14, 5, 6, 15, 9); added E2 to

Hookup (Figure 4); Improve text in “Setting the Alarm Clock” section

13-May-02 4.1 Modify reflow time and temperature footnote (Table 11)

16-Jul-02 4.1 Updated DC Characteristics, footnotes (Table 14)

27-Mar-03 5.0 v2.2 template applied; updated test condition (Table 14)

31-Mar-04 6.0 Reformatted; updated with Pb-free information (Table 11, 19)

M48T212Y, M48T212V

32/32

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