9352 025 40112 - Philips Semiconductors / NXP Semiconductors

DATA SH EET

Product speciﬁcation

Supersedes data of November 1994

File under Integrated Circuits, IC03

1995 Jun 27

INTEGRATED CIRCUITS

UMA1018M

Low-voltage dual frequency

synthesizer for radio telephones

1995 Jun 27 2

Philips Semiconductors Product speciﬁcation

Low-voltage dual frequency

synthesizer for radio telephones UMA1018M

FEATURES

•Low current from 3 V supply

•Fully programmable RF divider

•3-line serial interface bus

•Second synthesizer to control first IF or offset loop

frequency

•Independent fully programmable reference dividers for

each loop, driven from external crystal oscillator

•Dual phase detector outputs to allow fast frequency

switching

•Integrated digital-to-analog converter

•Dual power-down modes.

APPLICATIONS

•900 MHz mobile telephones

•Portable battery-powered radio equipment.

GENERAL DESCRIPTION

The UMA1018M BICMOS device integrates prescalers,

programmable dividers, and phase comparators to

implement two phase-locked loops. The device is

designed to operate from 3 NiCd cells, in pocket phones,

with low current and nominal 5 V supplies.

The principal synthesizer operates at RF input frequencies

up to1.25 GHz the auxiliary synthesizer operates at

300 MHz. The auxiliary loop is intended for the first IF or to

transmit offset loop-frequency settings. Each synthesizer

has a fully programmable reference divider. All divider

ratios are supplied via a 3-wire serial programming bus.

Separate power and ground pins are provided to the

analog and digital circuits. The ground leads should be

externally short-circuited to prevent large currents flowing

across the die and thus causing damage. Digital supplies

VDD1 and VDD2 must also be at the same potential. VCC

must be equal to or greater than VDD (i.e. VDD = 3 V and

VCC = 5 V for wider tuning range).

The principal synthesizer phase detector uses two charge

pumps, one provides normal loop feedback, while the

other is only active during fast mode to speed-up

switching. The auxiliary loop has a separate phase

detector. All charge pump currents (gain) are fixed by an

external resistance at pin ISET (pin 14). Only passive loop

filters are used; the charge-pumps function within a wide

voltage compliance range to improve the overall system

performance. An on-chip 7-bit DAC enables adjustment of

an external function, such as the temperature

compensation of a crystal oscillator in Global System for

Mobile communications (GSM).

QUICK REFERENCE DATA

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

VCC, VDD supply voltage VCC ≥VDD 2.7 −5.5 V

ICC +I

DD principal synthesizer supply current auxiliary synthesizer in

power-down mode −7.7 −mA

principal and auxiliary synthesizer

supply current principal and auxiliary

synthesizers ON −10 −mA

ICCPD, IDDPD current in power-down mode per supply −12 −µA

VCO principal input frequency 50 −1250 MHz

fAI auxiliary input frequency 20 −300 MHz

fXTAL crystal reference input frequency 3 −40 MHz

fPPC principal phase comparator frequency −200 −kHz

fAPC auxiliary phase comparator frequency −200 −kHz

Tamb operating ambient temperature −30 −+85 °C

1995 Jun 27 3

Philips Semiconductors Product speciﬁcation

Low-voltage dual frequency

synthesizer for radio telephones UMA1018M

ORDERING INFORMATION

BLOCK DIAGRAM

TYPE NUMBER PACKAGE

NAME DESCRIPTION VERSION

UMA1018M SSOP20 plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1

Fig.1 Block diagram.

1995 Jun 27 4

Philips Semiconductors Product speciﬁcation

Low-voltage dual frequency

synthesizer for radio telephones UMA1018M

PINNING

SYMBOL PIN DESCRIPTION

FAST 1 control input to speed-up main

synthesizer

CPPF 2 principal synthesizer speed-up

charge-pump output

CPP 3 principal synthesizer normal

charge-pump output

VDD1 4 digital power supply 1

VDD2 5 digital power supply 2

PRI 6 1 GHz principal synthesizer

frequency input

DGND 7 digital ground

fXTAL 8 common crystal frequency input from

TCXO

PON 9 principal synthesizer power-on input

DOUT 10 7-bit digital-to-analog output

CLK 11 Programming bus clock input

DATA 12 programming bus data input

E 13 programming bus enable input

(active LOW)

ISET 14 regulator pin to set the charge-pump

currents

AUX 15 auxiliary synthesizer frequency input

AGND 16 analog ground

CPA 17 auxiliary synthesizer charge-pump

output

VCC 18 supply for charge-pump and DAC

circuits

AON 19 auxiliary synthesizer power-on input

LOCK 20 in-lock detect output (main PLL);

test mode output Fig.2 Pin configuration.

FUNCTIONAL DESCRIPTION

Principal synthesizer

Programmable reference and main dividers drive the

principal PLL phase detector. Two charge pumps produce

phase error current pulses for integration in an external

loop filter. A hardwired power-down input PON (pin 9)

ensures that the dividers and phase comparator circuits

can be disabled.

The PRI input (pin 6) drives a pre-amplifier to provide the

clock to the first divider stage. The pre-amplifier has a high

input impedance, dominated by pin and pad capacitance.

The circuit operates with signal levels from 50 mV up to

225 mV (RMS), and at frequencies as high as 1.25 GHz.

The high frequency divider circuits use bipolar transistors,

slower bits are CMOS. Divider ratios (512 to 131071)

allow a 1 MHz phase comparison with a 500 MHz RF

input, and a 10 kHz phase comparison with a 1.25 GHz RF

input.

The reference and main divider outputs are connected to

a phase/frequency detector that controls two charge

pumps. The two pumps have a common bias-setting

current that is set by an external resistance. The ratio

between currents in fast and normal operating modes can

be programmed via the 3-wire serial bus. The low current

pump remains active except in power-down.

1995 Jun 27 5

Philips Semiconductors Product speciﬁcation

Low-voltage dual frequency

synthesizer for radio telephones UMA1018M

The high current pump is enabled via the control input

FAST (pin 1). By appropriate connection to the loop filter,

dual bandwidth loops are provided: short time constant

during frequency switching (FAST mode) to speed-up

channel changes and low bandwidth in the settled state

(on-frequency) to reduce noise and breakthrough levels.

The principal synthesizer speed-up charge pump (CPPF)

is controlled by the FAST input in synchronization with

phase detector operation in such a way that potential

disturbances are minimized. The dead zone (caused by

finite time taken to switch the current sources on or off) is

cancelled by feedback from the normal pump output to the

phase detector thereby improving linearity.

An open drain transistor drives the output pin LOCK

(pin 20). It is recommended that the pull-up resistor from

this pin to VDD is chosen such that the value is high enough

to keep the sink current in the LOW state below 400 µA.

The circuit can be programmed to output either the phase

error in the principal or auxiliary phase detectors or the

combination from both detectors (OR function). The

resultant output will be a current pulse with the duration of

the selected phase error. By appropriate external filtering

and threshold comparison an out-of-lock or an in-lock flag

is generated.

Auxiliary synthesizer

The auxiliary synthesizer has a 14-bit main divider and an

11-bit reference divider. A separate power-down input

AON (pin 19), disables currents in the auxiliary dividers,

phase detector, and charge pump. The auxiliary input

signal is amplified and fed to the main divider. The input

buffer presents a high impedance, dominated by pin and

pad capacitance. First divider stages use bipolar

technology operating at input frequencies up to 300 MHz;

the slower bits are CMOS. The auxiliary loop phase

detector and charge pump use similar circuits to the main

loop low-current phase comparator, including dead-zone

compensation feedback.

The auxiliary reference divider is clocked on the opposite

edge of the principal reference divider to ensure that active

edges arrive at the auxiliary and principal phase detectors

at different times. This minimizes the potential for

interference between the charge pumps of each loop.

Serial programming bus

A simple 3-line unidirectional serial bus is used to program

the circuit. The 3 lines are DATA, CLK and E (enable). The

data sent to the device is loaded in bursts framed by E.

Programming clock edges and their appropriate data bits

are ignored until E goes active LOW. The programmed

information is loaded into the addressed latch when E

returns inactive HIGH. Only the last 21 bits serially clocked

into the device are retained within the programming

is made on the number of clock pulses. The fully static

CMOS design uses virtually no current when the bus is

inactive. It can always capture new programmed data

even during power-down of main and auxiliary loops.

However, when either principal synthesizer or auxiliary

synthesizer or both are powered-on, the presence of a

TCXO signal is required at pin 8 (fXTAL) for correct

programming.

Data format

Data is entered with the most significant bit first.

The leading bits make up the data field, while the trailing

four bits are an address field. The UMA1018M uses 6 of

the 16 available addresses. These are chosen to allow

direct compatibility with the UAA2072M integrated

front-end. The data format is shown in Table 1. The first

entered bit is p1, the last bit is p21.

The trailing address bits are decoded on the inactive edge

of E. This produces an internal load pulse to store the data

in one of the addressed latches. To ensure that the data is

correctly loaded on first power-up, E should be held LOW

and only taken HIGH after having programmed an

appropriate register. To avoid erroneous divider ratios,

the pulse is not allowed during data reads by the frequency

dividers. This condition is guaranteed by respecting a

minimum E pulse width after data transfer.

The corresponding relationship between data fields and

addresses is given in Table 2.

1995 Jun 27 6

Philips Semiconductors Product speciﬁcation

Low-voltage dual frequency

synthesizer for radio telephones UMA1018M

Table 1 Format of programmed data

Table 2 Bit allocation (note 1)

Notes

1. FT = first; LT = last; sPON = software power-up for principal synthesizer (1 = ON); sAON = software power-up for auxiliary synthesizer (1 = ON).

2. The test register should not be programmed with any other value except all zeros for normal operation.

Table 3 Out-of-lock select

LAST IN PROGRAMMING REGISTER BIT USAGE FIRST IN

p21 p20 p19 p18 p17 p16 ../.. p2 p1

ADD0 ADD1 ADD2 ADD3 DATA0 DATA1 ../.. DATA15 DATA16

LATCH ADDRESS LSB DATA COEFFICIENT MSB

FT REGISTER BIT ALLOCATION LT

p1 p2 p3 p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14 p15 p16 p17 p18 p19 p20 p21

dt16 dt15 dt14 dt13 dt12 DATA FIELD dt4 dt3 dt2 dt1 dt0 ADDRESS

TEST BITS(2) 0000

X X X X OLP OLA CR1 CR0 X X sPON sAON X X X X X 0001

PM16 PRINCIPAL MAIN DIVIDER COEFFICIENT PM0 0100

X X X X X X PR10 PRINCIPAL REFERENCE DIVIDER COEFFICIENT PR0 0101

X X X AM13 AUXILIARY MAIN DIVIDER COEFFICIENT AM0 0110

X X X X X X AR10 AUXILIARY REFERENCE DIVIDER COEFFICIENT AR0 0111

X X X X X X X X X 0 DA6 7-BIT DAC DA0 1000

OLP OLA OUT-OF-LOCK ON PIN 20

0 0 output disabled

0 1 auxiliary phase error

1 0 principal phase error

1 1 both auxiliary and principal

1995 Jun 27 7

Philips Semiconductors Product speciﬁcation

Low-voltage dual frequency

synthesizer for radio telephones UMA1018M

Table 4 Fast and normal charge pumps current ratio (note 1)

Note

1. ; common bias current for charge pumps and DAC.

Table 5 Power-down modes

CR1 CR0 ICPA ICPP ICPPF ICPPF :I

CPP

00 4×I

SET 4×ISET 16 ×ISET 4:1

01 4×I

SET 4×ISET 32 ×ISET 8:1

10 4×I

SET 2×ISET 24 ×ISET 12:1

11 4×I

SET 2×ISET 32 ×ISET 16:1

AON PON FAST PRINCIPAL

DIVIDERS AUXILIARY

DIVIDERS PUMP

CPA PUMP

CPP PUMP

CPPF DAC AND BIAS

0 0 X OFF OFF OFF OFF OFF OFF

0 1 0 ON OFF OFF ON OFF ON

0 1 1 ON OFF OFF ON ON ON

1 0 X OFF ON ON OFF OFF ON

1 1 0 ON ON ON ON OFF ON

111 ON ON ONONON ON

SET V14

Rext

-----------

Digital-to-analog converter

The 7-bits loaded via the bus into the appropriate latch

drive a digital-to-analog converter. The internal current is

scaled by the external resistance (Rext) at pin ISET, similar

to the charge pumps. The nominal full-scale current is

2×ISET. The output current is mirrored to produce a

full-scale voltage into a user-defined ground referenced

resistance, thereby allowing optimum swing from power

supply rails within the 2.7 to 5.5 V limits. The band gap

reference voltage at pin ISET is temperature and supply

independent. The DAC signal is monotonic across the full

range of digital input codes to enable fine adjustment of

other system blocks. The typical settling time for full-scale

switching is 400 ns into a 12 kΩ// 20 pF load. DAC

functionality is neither tested nor guaranteed on

UMA1018M versions with the /S1 suffix.

Power-down modes

The action of the control inputs on the state of internal

blocks is defined by Table 5.

It should be noted that in Table 5, PON and AON can be

either the software or hardware power-down signals.

The dividers are ON when both hardware and software

power-down signals are at logic 1.

When either synthesizer is reactivated after power-down

the main and reference dividers of that synthesizer are

synchronized to avoid the possibility of random phase

errors on power-up.

1995 Jun 27 8

Philips Semiconductors Product speciﬁcation

Low-voltage dual frequency

synthesizer for radio telephones UMA1018M

LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 134).

HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is

desirable to take normal precautions appropriate to handling MOS devices.

THERMAL CHARACTERISTICS

SYMBOL PARAMETER MIN. MAX. UNIT

VDD digital supply voltage −0.3 +5.5 V

VCC analog supply voltage −0.3 +5.5 V

∆VCC−DD difference in voltage between VCC and VDD −0.3 +5.5 V

Vnvoltage at pins 1, 6, 8 to 15, 19 and 20 −0.3 VDD + 0.3 V

V2, 3, 17 voltage at pins 2, 3 and 17 −0.3 VCC + 0.3 V

∆VGND difference in voltage between AGND and DGND

(these pins should be connected together) −0.3 +0.3 V

Ptot total power dissipation −150 mW

Tstg storage temperature −55 +125 °C

Tamb operating ambient temperature −30 +85 °C

Tjmaximum junction temperature −95 °C

SYMBOL PARAMETER VALUE UNIT

Rth j-a thermal resistance from junction to ambient in free air 120 K/W

1995 Jun 27 9

Philips Semiconductors Product speciﬁcation

Low-voltage dual frequency

synthesizer for radio telephones UMA1018M

CHARACTERISTICS

VDD1 =V

DD2 = 2.7 to 5.5 V; VCC = 2.7 to 5.5 V; Tamb =25°C; unless otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supply; pins 4, 5 and 18

VDD digital supply voltage VDD1 =V

DD2 2.7 −5.5 V

VCC analog supply voltage VCC ≥VDD 2.7 −5.5 V

IDD principal synthesizer digital supply

current VDD = 5.5 V −6.5 8.5 mA

auxiliary synthesizer digital supply

current VDD = 5.5 V −2.7 4.0 mA

ICC charge pumps and analog supply

current VCC = 5.5 V;

Rext =12kΩ−1.2 2.0 mA

ICCPD,

IDDPD

current in power-down mode per

supply logic levels 0 V or VDD −12 50 µA

RF principal main divider input; pin 6

fVCO RF input frequency 2.7V<V

DD < 3.5 V 50 −1250 MHz

2.7V<V

DD < 5.5 V 50 −1100 MHz

V6(rms) AC-coupled input signal level

(RMS value) Rs=50Ω;

2.7V<V

DD < 3.5 V;

0.5 < fVCO < 1.25 GHz;

Tamb =−20 to +85°C

50 −225 mV

Rs=50Ω;

2.7V<V

DD < 5.5 V;

0.5 < fVCO < 1.1 GHz;

Tamb =−30 to +85°C

100 −300 mV

Rs=50Ω;

2.7V<V

DD < 5.5 V;

50 < fVCO < 500 MHz;

Tamb =−30 to +85°C

150 −300 mV

ZIinput impedance (real part) fVCO = 1 GHz −1−kΩ

CItypical pin input capacitance indicative, not tested −2−pF

Rpm principal main divider ratio 512 −131071

fPPCmax maximum principal phase

comparator frequency −2000 −kHz

fPPCmin minimum principal phase

comparator frequency −10 −kHz

1995 Jun 27 10

Philips Semiconductors Product speciﬁcation

Low-voltage dual frequency

synthesizer for radio telephones UMA1018M

Auxiliary main divider input; pin 15

fAI input frequency 20 −300 MHz

V15(rms) AC-coupled input signal level

(RMS value) Rs=50Ω;

2.7V<V

DD < 4.5 V;

Tamb =−30 to +85°C

50 −500 mV

Rs=50Ω;

2.7V<V

DD < 5.5 V;

Tamb =−20 to +85°C

100 −500 mV

ZIinput impedance (real part) fAI = 100 MHz −1−kΩ

CItypical pin input capacitance indicative, not tested −2−pF

Ram auxiliary main divider ratio 64 −16383

fAPCmax maximum auxiliary phase

comparator frequency −2000 −kHz

fAPCmin minimum auxiliary phase

comparator frequency −10 −kHz

Crystal reference divider input; pin 8

fXTAL crystal reference input frequency 5 −40 MHz

V8(rms) sinusoidal input signal level

(RMS value) 4.0V<V

DD < 5.5 V 50 −500 mV

2.7V<V

DD < 5.5 V 50 −250 mV

ZIinput impedance (real part) fXTAL = 30 MHz −6−kΩ

CItypical pin input capacitance indicative, not tested −2−pF

Rpr principal reference divider ratio 8 −2047

Rar auxiliary reference divider ratio 8 −2047

Charge pump current setting resistor input; pin 14

Rext external resistor from pin 14 to

ground 12 −60 kΩ

V14 regulated voltage at pin 14 Rext =12kΩ−1.15 −V

Charge pump outputs; pins 17, 3 and 2; Rext =12kΩ

Ocp charge pump output current error −25 −+25 %

Imatch sink-to-source current matching Vcp in range −±5−%

Lcp charge pump off leakage current Vcp =1⁄2VCC −5±1+5nA

cp charge pump voltage compliance 0.4 −VCC −0.4 V

Interface logic input signal levels; pins 13, 12, 11 and 1

VIH HIGH level input voltage 0.7VDD −VDD + 0.3 V

VIL LOW level input voltage −0.3 −0.3VDD V

Ibias input bias current logic 1 or logic 0 −5−+5 µA

CIinput capacitance indicative, not tested −2−pF

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

1995 Jun 27 11

Philips Semiconductors Product speciﬁcation

Low-voltage dual frequency

synthesizer for radio telephones UMA1018M

Note

1. ∆I is the change in DAC output current when making the code transitions: 3FH/40H or 1FH/20H.

SERIAL BUS TIMING CHARACTERISTICS

VDD =V

CC =3V; T

amb =25°C unless otherwise speciﬁed.

Note

1. The minimum pulse width (tW) can be smaller than 4 µs provided all the following conditions are satisfied:

a) Principal main divider input frequency

b) Auxiliary main divider input frequency

c) Reference divider input frequency

DAC output signal levels; pin 10; Rext =12to24kΩ

DAC DAC full scale output current 1.5 ×ISET 2×ISET 2.5 ×ISET mA

V10 output voltage compliance all codes 0 −VDD −0.4 V

I10min minimum DAC current 00 code −25µA

monot worst case monotonicity test: note 1 0.1 −1.9

Lock detect output signal; pin 20; open-drain output

VOL LOW level output voltage Isink = 0.4 mA −−0.4 V

SYMBOL PARAMETER MIN. TYP. MAX. UNIT

Serial programming clock; CLK

trinput rise time −10 40 ns

tfinput fall time −10 40 ns

Tcy clock period 100 −−ns

Enable programming; E

tSTART delay to rising clock edge 40 −−ns

tEND delay from last falling clock edge −20 −−ns

tWminimum inactive pulse width 4000(1) −−ns

tSU;E enable set-up time to next clock edge 20 −−ns

tSU;DAT input data to clock set-up time 20 −−ns

tHD;DAT input data to clock hold time 20 −−ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

∆I128

SET

--------------------

fVCO 256

----------

fAI 32

------

fXTAL 3

------

1995 Jun 27 12

Philips Semiconductors Product speciﬁcation

Low-voltage dual frequency

synthesizer for radio telephones UMA1018M

Fig.3 Serial bus timing diagram.

1995 Jun 27 13

Philips Semiconductors Product speciﬁcation

Low-voltage dual frequency

synthesizer for radio telephones UMA1018M

APPLICATION INFORMATION

Fig.4 Typical application block diagram.

1995 Jun 27 14

Philips Semiconductors Product speciﬁcation

Low-voltage dual frequency

synthesizer for radio telephones UMA1018M

Fig.5 Typical test and application diagram.

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BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB

BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB

BBBBBBBBBB

BBBBBBBBBBB

BBBBBBBBB

BBBBBBBBBBB

BBBBBBBBBB

BBBBBBBBBBB

1995 Jun 27 15

Philips Semiconductors Product speciﬁcation

Low-voltage dual frequency

synthesizer for radio telephones UMA1018M

PACKAGE OUTLINE

UNIT A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm 0.15

01.4

1.2 0.32

0.20 0.20

0.13 6.6

6.4 4.5

4.3 0.65 1.0 0.2

6.6

6.2 0.65

0.45 0.48

0.18 10

0.13 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

0.75

0.45

SOT266-1 90-04-05

95-02-25

detail X

vMA

(A )

0.25

110

20 11

pin 1 index

0 2.5 5 mm

scale

SSOP20: plastic shrink small outline package; 20 leads; body width 4.4 mm SOT266-1

max.

1.5

1995 Jun 27 16

Philips Semiconductors Product speciﬁcation

Low-voltage dual frequency

synthesizer for radio telephones UMA1018M

SOLDERING SO or SSOP

Introduction

There is no soldering method that is ideal for all IC

packages. Wave soldering is often preferred when

through-hole and surface mounted components are mixed

on one printed-circuit board. However, wave soldering is

not always suitable for surface mounted ICs, or for

printed-circuits with high population densities. In these

cases reflow soldering is often used.

This text gives a very brief insight to a complex technology.

A more in-depth account of soldering ICs can be found in

our

“IC Package Databook”

(order code 9398 652 90011).

Reﬂow soldering

Reflow soldering techniques are suitable for all SO and

SSOP packages.

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

to the printed-circuit board by screen printing, stencilling or

pressure-syringe dispensing before package placement.

Several techniques exist for reflowing; for example,

thermal conduction by heated belt. Dwell times vary

between 50 and 300 seconds depending on heating

method. Typical reflow temperatures range from

215 to 250 °C.

Preheating is necessary to dry the paste and evaporate

the binding agent. Preheating duration: 45 minutes at

45 °C.

Wave soldering

Wave soldering techniques can be used for all SO

packages if the following conditions are observed:

•A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave) soldering

technique should be used.

•The longitudinal axis of the package footprint must be

parallel to the solder flow.

•The package footprint must incorporate solder thieves at

the downstream end.

SSOP

Wave soldering isnot recommended for SSOP packages.

This is because of the likelihood of solder bridging due to

closely-spaced leads and the possibility of incomplete

solder penetration in multi-lead devices.

If wave soldering cannot be avoided, the following

conditions must be observed:

•A double-wave (a turbulent wave with high upward

pressure followed by a smooth laminar wave)

soldering technique should be used.

•The longitudinal axis of the package footprint must

be parallel to the solder flow and must incorporate

solder thieves at the downstream end.

Even with these conditions, only consider wave

soldering SSOP packages that have a body width of

4.4 mm, that is SSOP16 (SOT369-1) or

SSOP20 (SOT266-1).

METHOD (SO OR SSOP)

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Maximum permissible solder temperature is 260 °C, and

maximum duration of package immersion in solder is

10 seconds, if cooled to less than 150 °C within

6 seconds. Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

Repairing soldered joints

Fix the component by first soldering two diagonally-

opposite end leads. Use only a low voltage soldering iron

(less than 24 V) applied to the flat part of the lead. Contact

time must be limited to 10 seconds at up to 300 °C. When

using a dedicated tool, all other leads can be soldered in

one operation within 2 to 5 seconds at 270 to 320 °C.

1995 Jun 27 17

Philips Semiconductors Product speciﬁcation

Low-voltage dual frequency

synthesizer for radio telephones UMA1018M

DEFINITIONS

LIFE SUPPORT APPLICATIONS

These products are not designed for use in life support appliances, devices, or systems where malfunction of these

products can reasonably be expected to result in personal injury. Philips customers using or selling these products for

use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such

improper use or sale.

Data sheet status

Objective speciﬁcation This data sheet contains target or goal speciﬁcations for product development.

Preliminary speciﬁcation This data sheet contains preliminary data; supplementary data may be published later.

Product speciﬁcation This data sheet contains ﬁnal product speciﬁcations.

Limiting values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or

more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation

of the device at these or at any other conditions above those given in the Characteristics sections of the speciﬁcation

is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the speciﬁcation.

1995 Jun 27 18

Philips Semiconductors Product speciﬁcation

Low-voltage dual frequency

synthesizer for radio telephones UMA1018M

NOTES

1995 Jun 27 19

Philips Semiconductors Product speciﬁcation

Low-voltage dual frequency

synthesizer for radio telephones UMA1018M

NOTES

Philips Semiconductors – a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428)

BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367

Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113,

Tel. (02)805 4455, Fax. (02)805 4466

Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213,

Tel. (01)60 101-1236, Fax. (01)60 101-1211

Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands,

Tel. (31)40 783 749, Fax. (31)40 788 399

Brazil: Rua do Rocio 220 - 5th floor, Suite 51,

CEP: 04552-903-SÃO PAULO-SP, Brazil.

P.O. Box 7383 (01064-970),

Tel. (011)821-2333, Fax. (011)829-1849

Canada: PHILIPS SEMICONDUCTORS/COMPONENTS:

Tel. (800) 234-7381, Fax. (708) 296-8556

Chile: Av. Santa Maria 0760, SANTIAGO,

Tel. (02)773 816, Fax. (02)777 6730

Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17,

77621 BOGOTA, Tel. (571)249 7624/(571)217 4609,

Fax. (571)217 4549

Denmark: Prags Boulevard 80, PB 1919, DK-2300

COPENHAGEN S, Tel. (032)88 2636, Fax. (031)57 1949

Finland: Sinikalliontie 3, FIN-02630 ESPOO,

Tel. (358)0-615 800, Fax. (358)0-61580 920

France: 4 Rue du Port-aux-Vins, BP317,

92156 SURESNES Cedex,

Tel. (01)4099 6161, Fax. (01)4099 6427

Germany: P.O. Box 10 63 23, 20043 HAMBURG,

Tel. (040)3296-0, Fax. (040)3296 213.

Greece: No. 15, 25th March Street, GR 17778 TAVROS,

Tel. (01)4894 339/4894 911, Fax. (01)4814 240

Hong Kong: PHILIPS HONG KONG Ltd., 15/F Philips Ind. Bldg.,

24-28 Kung Yip St., KWAI CHUNG, N.T.,

Tel. (852)424 5121, Fax. (852)480 6960/480 6009

India: Philips INDIA Ltd, Shivsagar Estate, A Block ,

Dr. Annie Besant Rd. Worli, Bombay 400 018

Tel. (022)4938 541, Fax. (022)4938 722

Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4,

P.O. Box 4252, JAKARTA 12950,

Tel. (021)5201 122, Fax. (021)5205 189

Ireland: Newstead, Clonskeagh, DUBLIN 14,

Tel. (01)7640 000, Fax. (01)7640 200

Italy: PHILIPS SEMICONDUCTORS S.r.l.,

Piazza IV Novembre 3, 20124 MILANO,

Tel. (0039)2 6752 2531, Fax. (0039)2 6752 2557

Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108,

Tel. (03)3740 5130, Fax. (03)3740 5077

Korea: Philips House, 260-199 Itaewon-dong,

Yongsan-ku, SEOUL, Tel. (02)709-1412, Fax. (02)709-1415

Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA,

SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880

Mexico: 5900 Gateway East, Suite 200, EL PASO, TX 79905,

Tel. 9-5(800)234-7381, Fax. (708)296-8556

Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB

Tel. (040)783749, Fax. (040)788399

New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND,

Tel. (09)849-4160, Fax. (09)849-7811

Norway: Box 1, Manglerud 0612, OSLO,

Tel. (022)74 8000, Fax. (022)74 8341

Pakistan: Philips Electrical Industries of Pakistan Ltd.,

Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton,

KARACHI 75600, Tel. (021)587 4641-49,

Fax. (021)577035/5874546

Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc,

106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,

Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474

Portugal: PHILIPS PORTUGUESA, S.A.,

Rua dr. António Loureiro Borges 5, Arquiparque - Miraflores,

Apartado 300, 2795 LINDA-A-VELHA,

Tel. (01)4163160/4163333, Fax. (01)4163174/4163366

Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231,

Tel. (65)350 2000, Fax. (65)251 6500

South Africa: S.A. PHILIPS Pty Ltd.,

195-215 Main Road Martindale, 2092 JOHANNESBURG,

P.O. Box 7430, Johannesburg 2000,

Tel. (011)470-5911, Fax. (011)470-5494.

Spain: Balmes 22, 08007 BARCELONA,

Tel. (03)301 6312, Fax. (03)301 42 43

Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM,

Tel. (0)8-632 2000, Fax. (0)8-632 2745

Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,

Tel. (01)488 2211, Fax. (01)481 77 30

Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West

Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978,

TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382

Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,

209/2 Sanpavuth-Bangna Road Prakanong,

Bangkok 10260, THAILAND,

Tel. (662)398-0141, Fax. (662)398-3319

Turkey:Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL,

Tel. (0212)279 27 70, Fax. (0212)282 67 07

United Kingdom: Philips Semiconductors LTD.,

276 Bath Road, Hayes, MIDDLESEX UB3 5BX,

Tel. (0181)730-5000, Fax. (0181)754-8421

United States:811 East Arques Avenue, SUNNYVALE,

CA 94088-3409, Tel. (800)234-7381, Fax. (708)296-8556

Uruguay: Coronel Mora 433, MONTEVIDEO,

Tel. (02)70-4044, Fax. (02)92 0601

Internet: http://www.semiconductors.philips.com/ps/

For all other countries apply to: Philips Semiconductors,

International Marketing and Sales, Building BE-p,

P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands,

Telex 35000 phtcnl, Fax. +31-40-724825

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413061/1500/04/pp20 Date of release: 1995 Jun 27

Document order number: 9397 750 00182