PRELIMINARY CY2281 100MHz Pentium(R)II Clock Synthesizer/Driver with Spread Spectrum for Mobile PCs Features duce EMI in certain high-speed systems. A summary of clock outputs for both devices is shown below. * Mixed 2.5V and 3.3V operation * Complete clock solution for Pentium(R) II, and other similar processor-based motherboards -- Two CPU clocks at 2.5V up to 100 MHz -- Six synchronous PCI clocks, one free-running -- One 3.3V Ref. clock at 14.318 MHz -- One 3.3V USB clock at 48 MHz (-2S only) Spread Spectrum clocking for EMI control (-11S, -2S) 1.5-4.0 ns delay between CPU and PCI clocks Power-down, CPU stop and PCI stop pins Low skew outputs, 175 ps between CPU clocks Factory-EPROM programmable output drive and slew rate for EMI customization * Available in space-saving 28-pin SSOP package * * * * * Functional Description The part possesses power-down, CPU stop, and PCI stop pins for power management control. The signals are synchronized on-chip, and ensure glitch-free transitions on the outputs. When the CPU_STOP input is asserted, the CPU clock outputs are driven LOW. When the PCI_STOP input is asserted, the PCI clock outputs (except the free-running PCI clock) are driven LOW. When the PWR_DWN pin is asserted, the reference oscillator and PLLs are shut down, and all outputs are driven LOW. The CY2281 clock outputs are designed for low EMI emissions. Controlled rise and fall times, unique output driver circuits, and innovative circuit layout techniques enable the CY2281 to have lower EMI than clock devices from other manufacturers. Additionally, factory-EPROM programmable output drive and slew-rate control enable optimal configurations. CY2281 Selector Guide Clock Outputs The CY2281 is a clock synthesizer/driver for Pentium II, or other similar processor-based mobile PCs requiring up to 100 MHz support. The CY2281 outputs two CPU clocks at 2.5V. There are six PCI clocks, running at one-half or one-third the CPU clock frequency of 66.6 MHz and 100 MHz respectively. One of the PCI clocks is free-running. Additionally, the part outputs one 3.3V reference clock at 14.318 MHz. The CY2281-2S also provides one 3.3V USB clock at 48 MHz. The CY2281-11S and CY2281-2S incorporate the Intel(R)-defined spread spectrum feature. They provide a -0.6% downspread on the CPU and PCI clocks, which can help re- -1 -11S -2S CPU (66, 100 MHz) 2 2 2 PCI (CPU/2, CPU/3) 6[1] 6[1] 6[1] 1 1 1 USB (48 MHz) N/A N/A 1 CPU-PCI delay 1.5-4.0 ns 1.5-4.0 ns 1.5-4.0 ns None -0.6% -0.6% REF (14.318 MHz) Spread Spectrum Note: 1. One free-running PCI clock. Pin Configuration Logic Block Diagram 28-Pin SSOP Top View CPU_STOP XTALOUT REF 14.318 MHz OSC. VDDREF STOP LOGIC CPU PLL Divider CPUCLK [0-1] PCICLK_F SEL (-1/-11S only) EPROM VDDPCI Delay STOP LOGIC SEL100 1 28 27 VSS 2 3 26 PCICLK_F 4 REF VDDCPU PCICLK1 5 6 7 8 9 25 24 VDDPCI PCICLK2 PCICLK3 VDDPCI VDDCPU PWR_DWN XTALIN XTALOUT VSS PCI [1-5] VDDREF CPUCLK0 23 22 21 CPUCLK1 VSS PCI_STOP CPU_STOP VSS AVDD PCICLK4 PCICLK5 VSS 10 11 12 20 19 18 17 VDDUSB 13 16 PWR_DWN SEE CHART BELOW VSS 14 15 SEL100 Option Pin 16 -1,-11S SEL VDDPCI SYS PLL CY2281 XTALIN USBCLK (-2S only) VDDUSB PCI_STOP -2S USBCLK Intel and Pentium are registered trademarks of Intel Corporation. Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 July 21, 1999 PRELIMINARY CY2281 Pin Summary Name Pins VDDPCI 6, 9 3.3V Digital voltage supply for PCI clocks VDDREF 27 3.3V Digital voltage supply for REF clocks VDDCPU 25 2.5V Digital voltage supply for CPU clocks VDDUSB 13 3.3V Digital voltage supply for USB clock AVDD 21 Analog voltage supply, 3.3V 3, 12, 14, 20, 22, 28 Ground XTALIN 1 Reference crystal input XTALOUT[2] 2 Reference crystal feedback PCI_STOP 19 Active LOW control input to stop PCI clocks CPU_STOP 18 Active LOW control input to stop CPU clocks PWR_DWN 17 Active LOW control input to power down device SEL 16 CPU frequency select input (-1 and -11S options only) USBCLK 16 USB clock output, 48 MHz fixed (-2S option only) SEL100 15 CPU frequency select input, selects between 100 MHz and 66.6 MHz (see table below) CPUCLK[0:1] 23, 24 CPU clock outputs PCICLK[1:5] 5, 7, 8, 10, 11 PCI clock outputs, at one-half or one-third the CPU frequency of 66.6 MHz or 100 MHz respectively PCICLK_F 4 Free-running PCI clock output REF 26 3.3V Reference clock output VSS [2] Description Function Table SEL100 SEL[4] CPU/PCI Ratio 0 0 2 0 1 1 0 1 1 CPUCLK PCICLK_F PCICLK Hi-Z Hi-Z 2 66.66 MHz 33.33 MHz 3 TCLK/2 TCLK/6 3 100 MHz 33.33 MHz USBCLK[5] REF Hi-Z 48 MHz 14.318 MHz TCLK[3] 48 MHz Notes: 2. For best accuracy, use a parallel-resonant crystal, CLOAD = 18 pF. 3. TCLK supplied on the XTALIN pin in Test Mode. 4. SEL available on options -1 and -11S only. SEL tied HIGH internally on option -2S 5. USBCLK available on option -2S only. 2 14.318 MHz PRELIMINARY CY2281 Actual Clock Frequency Values Clock Output Target Frequency Actual Frequency (MHz) (MHz) PPM CPUCLK 66.67 66.654 -195 CPUCLK 100 99.77 -2346 USB 48 48.008 167 Power Management Logic PWR_DWN CPUCLK PCICLK PCI_STOP X X 0 Low Low Low Low Off 0 0 1 Low Low Running Running Running Running 0 1 1 Low Running Running Running Running Running 1 0 1 Running Low Running Running Running Running 1 1 1 Running Running Running Running Running Running 3 PCICLK_F Other Clocks CPU_STOP Osc. PLLs Off PRELIMINARY CY2281 Storage Temperature (Non-Condensing) ... -65C to +150C Maximum Ratings Max. Soldering Temperature (10 sec) ...................... +260C (Above which the useful life may be impaired. For user guidelines, not tested.) Junction Temperature ............................................... +150C Static Discharge Voltage .......................................... >1700V (per MIL-STD-883, Method 3015, like VDD pins tied together) Supply Voltage ............................................... -0.5V to +7.0V Input Voltage .............................................. -0.5V to VDD+0.5 Operating Conditions[6] Parameter Description Min. Max. Unit AVDD, VDDPCI, Analog and Digital Supply Voltage VDDREF, VDDUSB 3.135 3.465 V VDDCPU CPU Supply Voltage 2.375 2.625 V TA Operating Temperature, Ambient 0 70 C CL Max. Capacitive Load on CPUCLK PCICLK REF f(REF) Reference Frequency, Oscillator Nominal Value pF 20 30 20 14.318 14.318 MHz Electrical Characteristics Over the Operating Range Parameter Description Test Conditions VIH High-level Input Voltage Except Crystal Inputs VIL Low-level Input Voltage Except Crystal Inputs[7] VOH High-level Output Voltage VDDCPU = 2.375V VOL Low-level Output Voltage VOH High-level Output Voltage VDDPCI, AVDD, VDDREF = 3.135V VDDCPU = 2.375V 2.0 Low-level Output Voltage VDDPCI, AVDD, VDDREF = 3.135V V 0.8 IOH = 12 mA CPUCLK IOL = 12 mA CPUCLK IOH = 14.5 mA PCICLK IOH = 16 mA VOL Min. Max. Unit [7] 2.0 V V 0.4 2.4 V V REF, USB IOL = 9.4 mA PCICLK IOL = 9 mA REF, USB 0.4V V +10 A 10 A +10 A IIH Input High Current VIH = V DD IIL Input Low Current VIL = 0V IOZ Output Leakage Current Three-state IDD25 Power Supply Current for 2.5V Clocks VDDCPU = 2.625V, VIN = 0 or VDD, Loaded Outputs, CPU = 66.6 MHz 70 mA IDD25 Power Supply Current for 2.5V Clocks VDDCPU = 2.625V, VIN = 0 or VDD, Loaded Outputs, CPU = 100 MHz 100 mA IDD33 Power Supply Current for 3.3V Clocks VDD = 3.465V, V IN = 0 or VDD, Loaded Outputs 170 mA IDDS Powerdown Current Current draw in powerdown state 500 A -10 -10 Notes: 6. Electrical parameters are guaranteed with these operating conditions. 7. Crystal Inputs have CMOS thresholds. 4 PRELIMINARY CY2281 Switching Characteristics[8] Over the Operating Range Parameter Output Description Test Conditions t1 = t1A / t1B [9] Min. Typ. 45 50 Max. Unit t1 All Output Duty Cycle 55 % t2 CPUCLK CPU Clock Rising and Falling Edge Rate Between 0.4V and 2.0V 0.85 4.0 V/ns t2 PCICLK PCI Clock Rising and Falling Edge Rate Between 0.4V and 2.4V 1.0 4.0 V/ns t2 REF, USB REF Clock Rising and Falling Edge Rate Between 0.4V and 2.4V 0.5 2.0 V/ns t3 CPUCLK CPU Clock Rise Time Between 0.4V and 2.0V 0.4 1.6 ns t4 CPUCLK CPU Clock Fall Time Between 2.0V and 0.4V 0.4 1.6 ns t5 CPUCLK CPU-CPU Clock Skew Measured at 1.25V 175 ps t6 CPUCLK, PCICLK CPU-PCI Clock Skew Measured at 1.25V for 2.5V clocks, and at 1.5V for 3.3V clocks 4.0 ns t7 PCICLK, PCICLK PCI-PCI Clock Skew Measured at 1.5V 250 ps t10 CPUCLK Cycle-Cycle Clock Jitter Measured at 1.25V 550 ps t11 PCICLK Cycle-Cycle Clock Jitter Measured at 1.5V 550 ps t12 CPUCLK, PCICLK Power-up Time CPU and PCI clock stabilization from power-up 3 ms 100 Notes: 8. All parameters specified with loaded outputs. 9. Duty cycle is measured at 1.5V when VDD = 3.3V. When VDD = 2.5V, duty cycle is measured at 1.25V. Switching Waveforms Duty Cycle Timing t1A t1B OUTPUT All Outputs Rise/Fall Time VDD OUTPUT 0V t2 t4 t2 t3 CPU-CPU Clock Skew CPUCLK CPUCLK t5 5 1.5 PRELIMINARY Switching Waveforms (continued) CPU-PCI Clock Skew CPUCLK PCICLK t6 PCI-PCI Clock Skew PCICLK PCICLK t7 CPU_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) CPU_STOP CPUCLK (External) PCI_STOP CPUCLK (Internal) PCICLK (Internal) PCICLK (Free-Running) PCI_STOP PCICLK (External) PWR_DOWN CPUCLK (Internal) PCICLK (Internal) PWR_DWN CPUCLK (External) PCICLK (External) VCO Crystal Shaded section on the VCO and Crystal waveforms indicates that the VCO and crystal oscillator are active, and there is a valid clock. 6 CY2281 PRELIMINARY CY2281 Application Information Clock traces must be terminated with either series or parallel termination, as they are normally done. Application Circuit XTALIN XTALOUT Cx PWR_DWN# CPU_STOP# PCI_STOP# SEL SEL100 PWR_DWN# CPU_STOP# REF PCI_STOP# CPUCLK PCICLK SEL PCICLK_F SEL100 Rs REF CPUCLK PCICLK PCICLK_F VDD 3.3V Cd 0.1F VDDPCI/VDDREF AVDD/VDDUSB VDD 2.5V Cd 0.1F Ct VDDCPU VSS CY2281 28-PIN SSOP Cd = DECOUPLING CAPACITORS Ct = OPTIONAL EMI-REDUCING CAPACITORS Cx = OPTIONAL LOAD MATCHING CAPACITOR Rs = SERIES TERMINATING RESISTORS Summary * A parallel-resonant crystal should be used as the reference to the clock generator. The operating frequency and CLOAD of this crystal should be as specified in the data sheet. Optional trimming capacitors may be needed if a crystal with a different CLOAD is used. Footprints must be laid out for flexibility. * Surface mount, low-ESR, ceramic capacitors should be used for filtering. Typically, these capacitors have a value of 0.1 F. In some cases, smaller value capacitors may be required. * The value of the series terminating resistor satisfies the following equation, where Rtrace is the loaded characteristic impedance of the trace, Rout is the output impedance of the clock generator (specified in the data sheet), and Rseries is the series terminating resistor. Rseries > Rtrace - Rout * Footprints must be laid out for optional EMI-reducing capacitors, which should be placed as close to the terminating resistor as is physically possible. Typical values of these capacitors range from 4.7 pF to 22 pF. * A Ferrite Bead may be used to isolate the Board VDD from the clock generator VDD island. Ensure that the Ferrite Bead offers greater than 50 impedance at the clock frequency, under loaded DC conditions. Please refer to the application note "Layout and Termination Techniques for Cypress Clock Generators" for more details. * If a Ferrite Bead is used, a 10 F-22 F tantalum bypass capacitor should be placed close to the Ferrite Bead. This capacitor prevents power supply droop during current surges. 7 PRELIMINARY CY2281 Test Circuit VDDPCI, AVDD, VDDREF 3, 12, 14, 20, 22, 28 6, 9, 13, 21, 27 0.1 F CY2281-1,-11S, -2S VDDCPU OUTPUTS CLOAD 25 0.1 F Notes: Each supply pin must have an individual decoupling capacitor All capacitors must be placed as close to the pins as is possible. Ordering Information Ordering Code Package Name Operating Range Package Type CY2281PVC-1 O28 28-Pin SSOP Commercial CY2281PVC-11S O28 28-Pin SSOP Commercial CY2281PVC-2S O28 28-Pin SSOP Commercial Document #: 38-00660-C 8 PRELIMINARY CY2281 Package Diagram 28-Lead (210-Mil) Shrunk Small Outline Package O28 51-85079-B (c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.