Si53119-EK - Silicon Labs - Datasheet.Live

Si53119

19-O

UTPUT

PCI

BUFFER

Features

Applications

Description

The Si53119 is a 19-o utput, low -power HC SL differential clock buffer that

meets all of the performance requirements of the Intel DB1200ZL

specification. The device is optimized fo r distributing refere nce clocks for

Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/

Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI)

applications. The VCO of the device is optimized to support 100 MHz and

133 MHz operation. Each differential output can be enabled through I2C

for maximum flexibility and power savings. Measuring PCIe clock jitter is

quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it

for free at www.silabs.com/pcie-learningcenter.

Nineteen 0.7 V low-power, push-

pull HCSL PCIe Gen 3 outputs

100 MHz /133 MHz PLL

operation, supports PCIe and

QPI

PLL bandwidth SW SMBUS

programming overrides the latch

value from HW pin

9 selectable SMBUS addresses

SMBus address configurable to

allow multiple buffers in a single

control network 3.3 V supply

voltage operation

Separate VDDIO for outputs

PLL or bypass mode

Spread spectrum tolerable

1.05 to 3.3 V I/O supply voltage

50 ps output-to-output skew

50 ps cyc-cyc jitter (PLL mode)

Low phase jitter (Intel QPI, PCIe

Gen 1/2/3 common clock

compliant)

Gen 3 SRNS Compliant

100 ps input-to-output delay

Extended Temperature:

–40 to 85 °C

72-pin QFN

For variations of this device ,

contact Silicon Labs

Server

Storage

Data center

Enterprise switches and routers

Patents pending

Ordering Information:

See page 31.

Pin Assignments

Si53119

1VDDA

GNDA

100M_133M

HBW_BYPASS_LBW

PWRGD / PWRDN

GND

VDDR

CLK_IN

SA_0

SDA

SCL

SA_1

FBOUT_NC

GND

DIF_7

DIF_6

GND

VDD

DIF_5

DIF_4

GND

DIF_11

DIF_10

GND

VDD

VDD_IO

DIF_9

DIF_8

VDD_IO

DIF_0

GND

DIF_1

GND

VDD

VDD_IO

DIF_2

DIF_3

VDD_IO

GND

VDD_IO

GND

DIF_12

DIF_13

DIF_14

GND

DIF_15

DIF_16

DIF_17

DIF_18

FBOUT_NC

Si53119

2 Rev. 1.3

Functional Block Diagram

FB_OUT

DIF_[18:0]

S SC Comp a tible

PLL

Control

Logic

SCL

SDA

PWRG D / PWRDN

SA_1

SA_0

HBW_BYPASS_LBW

100M_133

CLK_IN

Si53119

Rev. 1.3 3

TABLE OF CONTENTS

Section Page

1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2.1. CLK_IN, CLK_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2.2. 100M_133M—Frequency Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2.3. SA_0, SA_1—Address Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

2.4. CKPWRGD/PWRDN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

2.5. HBW_BYPASS_LBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

2.6. Miscellaneous Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.1. Input Edge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

3.2. Termination of Differential Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

4. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.1. Byte Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

4.2. Block Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

4.3. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

5. Pin Descriptions: 72-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

6. Power Filtering Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

6.1. Ferrite Bead Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

9. Land Pattern: 72-pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Si53119

4 Rev. 1.3

1. Electrical Specifications

Table 1. DC Operating Characteristics

VDD_A =3.3V±5%, V

DD =3.3V±5%

Parameter Symbol Test Condition Min Max Unit

3.3 V Core Supply Voltage VDD/VDD_A 3.3 V ±5% 3.135 3.465 V

3.3 V I/O Supply Voltage1VDD_IO 1.05 V to 3.3 V ±5% 0.9975 3.465 V

3.3 V Input High Voltage VIH VDD 2.0 VDD+0.3 V

3.3 V Input Low Voltage VIL VSS-0.3 0.8 V

Input Leakage Current2IIL 0 < VIN < VDD –5 +5 µA

3.3 V Input High Voltage3VIH_FS VDD 0.7 VDD+0.3 V

3.3 V Input Low Voltage3VIL_FS VSS–0.3 0.35 V

3.3 V Input Low Voltage VIL_Tri 0 0.9 V

3.3 V Input Med Voltage VIM_Tri 1.3 1.8 V

3.3 V Input High Voltage VIH_Tri 2.4 VDD V

3.3 V Output High Voltage4VOH I

OH =–1mA 2.4 — V

3.3 V Output Low Voltage4VOL IOL =1mA — 0.4 V

Input Capacitance5CIN 2.5 4.5 pF

Output Capacitance5COUT 2.5 4.5 pF

Pin Inductance LPIN —7nH

Ambient Temperature TANo Airflow –40 85 °C

Notes:

1. VDD_IO applies to the low-power NMOS push-pull HCSL compatible outputs.

2. Input Leakage Current does not include inpu ts with pull-up or pull-down resistors. Inputs with resistors should state

current requirements.

3. Internal voltage reference is to be used to guarantee VIH_FS and VIL_FS threshold levels over full operating range.

4. Signal edge is required to be monotonic when transitioning through this region.

5. Ccomp capacitance based on pad metallization and silicon device capacitance. Not including pin capacitance.

Si53119

Rev. 1.3 5

Table 2. SMBus Characteristics

Parameter Symbol Test Condition Min Max Unit

SMBus Input Low Voltage1VILSMB 0.8 V

SMBus Input High Voltage1VIHSMB 2.1 VDDSMB V

SMBus Output Low Voltage1VOLSMB @ IPULLUP 0.4 V

Nominal Bus Voltage1VDDSMB @ VOL 2.7 5.5 V

SMBus sink Current1IPULLUP 3V to 5V +/-10% 4 mA

SCLK/SDAT Rise Time1tRSMB (Max VIL – 0.15) to (Min VIH + 0.15) 1000 ns

SCLK/SDAT Fall Time1tFSMB (Min VIH + 0.15) to (Max VIL – 0.15) 300 ns

SMBus Operating Frequency1,2 fMINSMB Minimum Operating Frequency 100 kHz

Notes:

1. Guaranteed by design and charac terization

2. The differential input clock must be running for the SMBus to be ac tive

Table 3. Current Consumption

TA= -40–85 °C; supply voltage VDD =3.3V ±5%

Parameter Symbol Test Condition Min Typ Max Unit

Operating Current IDDVDD 100 MHz, VDD Rail — 25 35 mA

IDDVDDA 100 MHz, VDDA + VDDR, PLL Mode — 16 20 mA

IDDVDDIO 100 MHz, CL = Full Load, VDD IO Rail — 130 150 mA

Power Down Current IDDVDDPD Power Down, VDD Rail — 1.5 2 mA

IDDVDDAPD Power Down, VDDA Rail — 8 12 mA

IDDVDDIOPD Power Down, VDD_IO Rai l — 0.17 0.5 mA

Si53119

6 Rev. 1.3

Table 4. Clock Input Parameters

TA= -40–85 °C; supply voltage VDD =3.3V ±5%

Parameter Symbol Test Condition Min Typ Max Unit

Input High Voltage VIHDIF Differential Inputs

(singled-ended measurement) 600 700 1150 mV

Input Low Voltage VIHDIF Differential Inputs

(singled-ended measurement) Vss-

300 0300mV

Input Common Mode

Voltage Vcom Common mode input voltage 300 1000 mV

Input Amplitude, CLK_IN Vswing Peak to Peak Value 300 1450 mV

Input Slew Rate, CLK_IN dv/dt Measured differentially 0.4 8 V/ns

Input Duty Cycle Measurement from differential wave

form 45 50 55 %

Input Jitter–Cycle to Cycle JDFin Differential measurement 125 ps

Input Frequ ency Fibyp VDD = 3.3 V, bypass mode 33 150 MHz

FiPLL VDD = 3.3 V, 100 MHz PLL Mode 90 100 110 MHz

FiPLL VDD = 3.3 V, 133.33 MHz PLL Mode 120 133.33 147 MHz

Input SS Modulation Rate fMODIN Triangle wave modulation 30 31.5 33 kHz

Si53119

Rev. 1.3 7

Table 5. Output Skew, PLL Bandwidth and Peaking

TA= -40–85 °C; supply voltage VDD =3.3V ±5%

Parameter Test Condition Min TYP Max Unit

CLK_IN, DIF[x:0] Input-to-Output Delay in PLL Mode

Nominal Value1,2,3,4 –100 18 100 ps

CLK_IN, DIF[x:0] Input-to-Output Delay in Bypass Mode

Nominal Value2,4,5 2.5 3.6 4.5 ns

CLK_IN, DIF[x:0] Input-to-Output Delay Variation in PLL mode

Over Voltage and Temperature2,4,5 –50 20 50 ps

CLK_IN, DIF[x:0] Input-to-Output Delay Variation in Bypass Mode

Over Voltage and Temperature2,4,5 –250 250 ps

DIF[11:0] Output-to-Outpu t Skew across all 19 Outputs

(Common to Bypass and PLL Mode)1,2,3,4,5 0 20 50 ps

PLL Jitter Peaking (HBW_BYPASS_LBW =0)

6— 0.4 2.0 dB

PLL Jitter Peaking (HBW_BYPASS_LBW =1)

6—0.12.5dB

PLL Bandwidth (HBW_BYPASS_LBW =0)

7—0.71.4 MHz

PLL Bandwidth (HBW_BYPASS_LBW =1)

7—24 MHz

Notes:

1. Measured into fixed 2 pF load cap. Input-to-output skew is measured at the first output edge following the

corresponding input.

2. Measured from differential cross-point to differential cross-point.

3. This parameter is deterministic for a given device.

4. Measured with scope averaging on to find mean value.

5. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created

by it.

6. Measured as maximum pass band gain. At frequencies within the loop BW , highest point of magnification is called PLL

jitter peaking.

7. Measured at 3 db down or half power point.

Si53119

8 Rev. 1.3

Table 6. Phase Jitter

Parameter Test Condition Min Typ Max Unit

Phase Jitter

PLL Mode PCIe Gen 1, Common Clock1,2,3 —2586ps

PCIe Gen 2 Low Band, Common Clock

F < 1.5 MHz1,3,4,5 — 2.5 3.0 ps

(RMS)

PCIe Gen 2 High Band, Common Clock

1.5 M Hz < F < Nyquist 1,3,4,5 — 2.5 3.1 ps

(RMS)

PCIe Gen 3, Common Clock

(PLL BW 2–4 MHz, CDR = 10 MHz)1,3,4,5 — 0.5 1.0 ps

(RMS)

PCIe Gen 3 Separate Reference No Sp re ad, SRNS

(PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz)1,3,4,5 — 0.35 0.71 ps

(RMS)

Intel® QPI & Intel SMI

(4.8 Gbps or 6.4 Gb/s, 100 or 133 MHz, 12 UI)1,6,7 — 0.25 0.5 ps

(RMS)

Intel QPI & Intel SMI

(8 Gb/s, 100 MHz, 12 UI)1,6 — 0.15 0.3 ps

(RMS)

Intel QPI & Intel SMI

(9.6 G b/ s, 100 MHz, 12 UI)1,6 — 0.16 0.2 ps

(RMS)

Notes:

1. Post processed evaluation through Intel supplied Matlab* scripts. Defined for a BER of 1E-12. Measured values at a

smaller sample size have to be extrapolated to this BER target.

2. ζ= 0.54 implies a jitter peaking of 3 dB.

3. PCIe* Gen 3 filter characteristics are subject to final ratification by PCISIG. Check the PCI-SIG for the latest

specification.

4. Measured on 100 MHz PCIe output using the template file in the Intel-supplied Clock Ji tter Tool V1.6.3.

5. Measured on 100 MHz output using the template file in the Intel-supplied Clo ck Jitter Tool V1.6.3.

6. Measured on 100 MHz, 133 MHz output using the template file in the Intel-supplie d Clock Jitter Tool V1.6.3.

7. These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be

extrapolated to this BER target.

8. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.9.

9. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.

Si53119

Rev. 1.3 9

Additive Phase Jitter

Bypass Mode PCIe Gen 11,2,3 —10—ps

PCIe Gen 2 Low Band

F < 1.5 MHz1,3,4,5 —1.0—ps

(RMS)

PCIe Gen 2 High Band

1.5 M Hz < F < Nyquist1,3,4,5 —1.0—ps

(RMS)

PCIe Gen 3

(PLL BW 2–4 MHz, CDR = 10 MHz)1,3,4,5 —0.3—ps

(RMS)

PCIe Gen 4, Common Clock

(PLL BW of 2–4 or 2–5 MHz, CDR = 10 MHz)1,4,5,8 —0.3—ps

(RMS)

Intel QPI & Intel® SMI

(4.8 Gbps or 6.4 Gb/s, 100 or 133 MHz, 12 UI)1,6,7 —0.15— ps

(RMS)

Intel QPI & Intel® SMI

(8 Gb/s, 100 MHz, 12 UI)1,6 —0.1—ps

(RMS)

Intel QPI & Intel® SMI

(9.6 G b/ s, 100 MHz, 12 UI)1,6 —0.1—ps

(RMS)

Table 6. Phase Jitter (Continued)

Notes:

1. Post processed evaluation through Intel supplied Matlab* scripts. Defined for a BER of 1E-12. Measured values at a

smaller sample size have to be extrapolated to this BER target.

2. ζ= 0.54 implies a jitter peaking of 3 dB.

3. PCIe* Gen 3 filter characteristics are subject to final ratification by PCISIG. Check the PCI-SIG for the latest

specification.

4. Measured on 100 MHz PCIe output using the template file in the Intel-supplied Clock Ji tter Tool V1.6.3.

5. Measured on 100 MHz output using the template file in the Intel-supplied Clo ck Jitter Tool V1.6.3.

6. Measured on 100 MHz, 133 MHz output using the template file in the Intel-supplie d Clock Jitter Tool V1.6.3.

7. These jitter numbers are defined for a BER of 1E-12. Measured numbers at a smaller sample size have to be

extrapolated to this BER target.

8. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.9.

9. Download the Silicon Labs PCIe Clock Jitter Tool at www.silabs.com/pcie-learningcenter.

Si53119

10 Rev. 1.3

Table 7. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)1

Parameter Symbol CLK 100 MHz, 133 MHz Unit

Min Typ Max

Clock Stabilization Time2TSTAB — 1.5 1.8 ms

Long Term Accuracy3,4,5 LACC — — 100 ppm

Absolute Host CLK Period (100 MHz)3,4,6 TABS 9.94900 — 10.05100 ns

Absolute Host CLK Period (133 MHz)3,4,6 TABS 7.44925 — 7.55075 ns

Slew Rate3,4,7 Edge_rate 1.0 3.0 4.0 V/ns

Rise Time Variation3,8,9 ∆ Trise — — 125 ps

Fall Time Variation3,8,9 ∆ Tfall — — 125 ps

Rise/Fall Matching3,8,10,11 TRISE_MAT/

TFALL_MAT

—720%

Voltage High (typ 0.7 V)3,8,12 VHIGH 660 750 850 mV

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8– 2.0 V to the

time that stable clocks are output from the buffer chip (PLL locked).

3. Test configuration is Rs = 33.2 , 2 pF for 100  transmission line; Rs = 27 , 2 pF for 85  transmission line .

4. Measurement taken from differential waveform.

5. Using frequency counte r with the measurement interval equal or greater than 0.15 s, target frequencies are

99,750,00 Hz, 133,000,000 Hz.

6. The average period over any 1 µs period of time must be greater than the minimum and less than the maximum

specified period.

7. Measure taken from differential waveform on a component test board. The edge (slew) rate is measured from

–150 mV to +150 mV on the differential waveform. Scope is set to average because the scope sample clock is making

most of the dynamic wiggles along the clock edge. Only valid for Rising clock and Falling CLOCK. Signal must be

monotonic through the Vol to Voh region for Trise and Tfall.

8. Measurement taken from single-ended waveform.

9. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.

10. Measured with oscilloscope, averag ing on. The difference between the rising edge rate (average) of clock verses the

falling edge rate (average) of CLOCK.

11. Rise/Fall matching is derived using the following, 2*(Trise – Tfall) / (Trise + Tfall).

12. VHigh is defined as the statistical average High value as obtained by using the Oscilloscope VHigh Math function.

13. VLow is defined as the statistical average Low value as obtained by using the Oscilloscope VLow Math function.

14. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of

CLK.

15. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is

crossing.

16. The crossing point must meet the absolute and relative crossing point specifications simu ltaneously.

17. Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg – 0.700), Vcross(rel)

Max = 0.550 – 0.5 (0.700 – Vhavg), (see Figures 3–4 for further clarification).

18. Vcross is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK. This is the

maximum allowed variance in Vcross for any particular system.

19. Overshoot is defined as the absolute value of the maximum voltage.

20. Undershoot is define d as the absolute value of the minimum voltage.

Si53119

Rev. 1.3 11

Voltage Low (Typ 0.7 V)3,8,13 VLOW –150 15 150 mV

Maximum Voltage8VMAX — 850 1150 mV

Minimum Voltage VMIN –300 — — mV

Absolute Crossing Point Voltages3,8,14,15,16 VoxABS 300 450 550 mV

Total Variation of Vcross Over All Edges3,8,18 Total ∆

Vox —14140 mV

Duty Cycle3,4 DC 45 — 55 %

Maximum Voltage (Overshoot)3,8,19 Vovs ——V

High + 0.3 V

Maximum Voltage (Undershoot)3,8,20 Vuds ——V

Low – 0.3 V

Ringback Voltage3,8 Vrb 0.2 — N/A V

Table 7. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)1 (Continued)

Parameter Symbol CLK 100 MHz, 133 MHz Unit

Min Typ Max

Notes:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8– 2.0 V to the

time that stable clocks are output from the buffer chip (PLL locked).

3. Test configuration is Rs = 33.2 , 2 pF for 100  transmission line; Rs = 27 , 2 pF for 85  transmission line .

4. Measurement taken from differential waveform.

5. Using frequency counte r with the measurement interval equal or greater than 0.15 s, target frequencies are

99,750,00 Hz, 133,000,000 Hz.

6. The average period over any 1 µs period of time must be greater than the minimum and less than the maximum

specified period.

7. Measure taken from differential waveform on a component test board. The edge (slew) rate is measured from

–150 mV to +150 mV on the differential waveform. Scope is set to average because the scope sample clock is making

most of the dynamic wiggles along the clock edge. Only valid for Rising clock and Falling CLOCK. Signal must be

monotonic through the Vol to Voh region for Trise and Tfall.

8. Measurement taken from single-ended waveform.

9. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.

10. Measured with oscilloscope, averag ing on. The difference between the rising edge rate (average) of clock verses the

falling edge rate (average) of CLOCK.

11. Rise/Fall matching is derived using the following, 2*(Trise – Tfall) / (Trise + Tfall).

12. VHigh is defined as the statistical average High value as obtained by using the Oscilloscope VHigh Math function.

13. VLow is defined as the statistical average Low value as obtained by using the Oscilloscope VLow Math function.

14. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of

CLK.

15. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is

crossing.

16. The crossing point must meet the absolute and relative crossing point specifications simu ltaneously.

17. Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg – 0.700), Vcross(rel)

Max = 0.550 – 0.5 (0.700 – Vhavg), (see Figures 3–4 for further clarification).

18. Vcross is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK. This is the

maximum allowed variance in Vcross for any particular system.

19. Overshoot is defined as the absolute value of the maximum voltage.

20. Undershoot is define d as the absolute value of the minimum voltage.

Si53119

12 Rev. 1.3

Table 10. Absolute Maximum Ratings

Table 8. Clock Periods Differential Clock Outputs with SSC Disabled

SSC OFF

Center

Freq, MHz

Measurement Window Unit

1 Clock 1µs 0.1s 0.1s 0.1s 1µs 1 Clock

–C-C

Jitter

AbsPer

Min

–SSC

Short

T erm A VG

Min

–ppm

Long

Term AVG

Min

0ppm

Period

Nominal

+ppm

Long

T erm A VG

Max

+SSC

Short

T erm A VG

Max

+C-C

Jitter

AbsPer

Max

100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns

133.33 7.44925 7.49925 7.50000 7.50075 7.55075 ns

Table 9. Clock Periods Differential Clock Outputs with SSC Enabled

SSC ON

Center

Freq, MHz

Measurement Window Unit

1 Clock 1µs 0.1s 0.1s 0.1s 1µs 1 Clock

–C-C

Jitter

AbsPer

Min

–SSC

Short

T erm A VG

Min

–ppm

Long

Term AVG

Min

0ppm

Period

Nominal

+ppm

Long

T erm A VG

Max

+SSC

Short

T erm A VG

Max

+C-C

Jitter

AbsPer

Max

99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns

133.33 7.44930 7.49930 7.51805 7.51880 7.51955 7.53830 7.58830 ns

Parameter Symbol Min Max Unit

3.3 V Core Supply Voltage1VDD/VDD_A — 4.6 V

3.3 V I/O Supply Voltage1VDD_IO — 4.6 V

3.3 V Input High Voltage1,2 VIH — 4.6 V

3.3 V Input Low Voltage1VIL −0.5 — V

Storage Temperature1ts –65 150 °C

Input ESD protection3ESD 2000 — V

Notes:

1. Consult manufacturer regarding extended operation in excess of normal dc operating parameters.

2. Maximum VIH is not to exceed maximum VDD.

3. Human body model.

Si53119

Rev. 1.3 13

2. Functional Description

2.1. CLK_IN, CLK_IN

The dif ferential input clock is expected to be sourced from a clock synthesizer or PCH.

2.2. 100M_133M—Frequency Selection

The Si53119 is optimized for lowest phase jitter performance at operating frequencies of 100 and 133 MHz.

100M_133M is a hardware input pin, which programs the appropriate output frequency of the differential outputs.

Note that the CLK_IN frequency must be equal to the CLK_OUT frequency; meaning Si53119 is operated in 1:1

mode only. Frequency selection can be enabled by the 100M_133M hardware pin. An external pull-up or pull-do wn

resistor is attached to this pin to select the input/output frequency. The functionality is summarized in Table 11.

Note: All differential outputs transition from 100 to 133 MHz or from 133 to 100 MHz in a glitch free manner .

2.3. SA_0, SA_1—Address Selection

SA_0 and SA_1 are tri-level hardware pins, which program the appropriate address for the Si53119. The two tri-

level input pins that can configure the device to nine different addresses.

Table 11. Frequency Program Table

100M_133M Optimized Frequency (DIF_IN = DIF_x)

0133.33MHz

1100.00MHz

Table 12. SMBUS Address Table

SA_1 SA_0 SMBUS Address

LLD8

LMDA

LHDE

MLC2

MMC4

MHC6

HLCA

HMCC

HHCE

Si53119

14 Rev. 1.3

2.4. CKPWRGD/PWRDN

CKPWRGD is asserted high and deasserted low. Deassertion of PWRGD (pulling the signal low) is equivalent to

indicating a power down condition. CKPWRGD (assertion) is used by the Si53119 to sample initial configurations,

such as frequency select condition and SA selections. After CKPWRGD has been asserted high for the first time,

the pin becomes a PWRDN (Power Down) pin that can be used to shut off all clocks cleanly and instruct the device

to invoke power-saving mode. PWRDN is a completely asynchronous active low input. When entering power-

saving mode, PWRDN should be asserted low prior to shutting of f the input clock or power to ensure all clocks shut

down in a glitch free manner. When PWRDN is asserted low, all clocks will be disabled prior to turning off the VCO.

When PWRDN is deasserted high, all clocks will start and stop without any abnormal behavior and will meet all ac

and dc parameters.

Note: The assertion and deassertion of PWRD N is absolutely asynchronous.

Warning: Disabling of the CLK_IN input clock prior to assertion of PWRDN is an undefined mode and not recommended. Oper-

ation in this mode may result in glitches, excessive frequency shifting, etc.

2.4.1. PWRDN Assertion

When PWRDN is sampled low by two consecutive rising edges of DIF, all differential outputs must be held LOW/

LOW on the next DIF high-to-low transition.

Figure 1. PWRDN Assertion

Table 13. CKPWRGD/PWRDN Functionality

CKPWRGD/

PWRDN DIF_IN/

DINF_IN# SMBus

EN bit DIF-x/

DIF_x# FBOUT_NC/

FBOUT_NC# PLL State

0 X X Low/Low Low/Low OFF

1 Running 0 Low/Low Running ON

1 Running Running ON

PWRDWN

DIF

Si53119

Rev. 1.3 15

2.4.2. CKPWRGD Assertion

The powerup latency is to be less than 1.8 ms. This is the time from a valid CLK_IN input clock and the a ssertion of

the PWRGD signal to the time that stable clocks are output from the device (PLL locked). All differential outputs

stopped in a LOW/LOW condition resulting from power down must be driven high in less than 300 µs of PWRDN

deassertion to a voltage greater than 200 mV.

Figure 2. PWRDG Assertion (Pwrdown—Deassertion)

2.5. HBW_BYPASS_LBW

The HBW_BYPASS_LBW pin is a tri-level function input pin (refer to Table 1 for VIL_Tri, VIM_Tri, and VIH_Tri

signal levels). I t is us ed to se lect be twee n PL L h ig h-ba n dwidth, PLL b ypass mode , o r PLL lo w- ba nd width mode . I n

PLL bypass mode, the input clock is passed directly to the output stage, which may result in up to 50 ps of additive

cycle-to-cycle jitter (50 ps + inpu t jitter ) on th e dif f erential outputs. In PLL mode, the input clock is passed through a

PLL to reduce high-frequency jitter. The PLL HBW, BYPASS, and PLL LBW modes may be selected by asserting

the HBW_BYPASS_LB W input pin to the appropriate level described in Table 14.

The Si53119 has the ability to override the latch value of the PLL operating mode from hardware strap pin 5 via the

use of Byte 18 and bi ts 1 and 0. Byte 18 bit 2 must be set to 1 to allow the u ser to chan ge Bit s 1 and 0, affecting the

PLL. Byte0, Bits 7 and 6 will always read back the original latched value from hardware strap pin5. A warm reset of

the external system will have to be accomplished if the user changes these bits.

Table 14. PLL Bandwidth and Readback Table

HBW_BYPASS_LBW Pin Mode Byte 0, Bit 7 Byte 0, Bit 6

LLBW00

M BYPASS 0 1

HHBW11

Tstable

<1.8 ms

Tdrive_Pwrdn#

<300 µs; > 200 mV

DIF

PWRGD

Si53119

16 Rev. 1.3

2.6. Miscellaneous Requirements

Data Transfer Rate: 100 kbps (standard mode) is the base functionality required. Fast mode (400 kbps)

functionality is optional.

Logic Levels: SMBus logic levels are based on a percentage of VDD for the controller and other devices on the

bus. Assume all devices are based on a 3.3 V supply.

Clock Stretching: The clock buffer must not hold/stretch the SCL or SDA lines low for more than 10 ms. Clock

stretching is discouraged and should only be used as a last resort. Stretching the clock/data lines for longer than

this time puts the device in an error/time-out mode and may not be supported in a ll platforms. It is assumed that all

data transfers can be completed as specified without the use of clock/data stretching .

General Call: It is assumed that the clock buffer will not have to respond to the “general call.”

Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in

Section 3 of the SMBus 2.0 specification.

Pull-Up Resistors: Any internal resistor pull-ups on the SDATA and SCLK inputs must be stated in the individual

datasheet. The use of internal pull-ups on these pins of below 100 K is discouraged. Assume that the board

designer will use a single external pull-up resistor for each line and that these values are in the 5–6 k range.

Assume one SMBus device per DIMM (serial presence detect), one SMBus controller, one clock buffer, one clock

driver plus one/two more SMBus devices on the platfor m for capacitive loading purposes.

Input Glitch Filters: Only fast mode SMBus devices require input glitch filters to suppress bus noise. The clock

buffer is specified as a standard mode device and is not required to supp ort t his fe atur e. However, it is considered

a good design practice to include the filters.

PWRDN: If a clock buffer is placed in PWRDN mode, the SDATA and SCLK inputs must be Tri-stated and the

device must retain all programming information. IDD current due to the SMBus circuitry must be characterized and

in the data sheet.

Si53119

Rev. 1.3 17

3. Test and Measurement Setup

3.1. Input Edge

Input edge rate is based on single-ended measurement. This is the minimum input edge rate at which the Si53119

is guaranteed to meet all performance specifications.

3.1.1. Measurement Points for Differential

Figure 3. Measurement Points for Rise Time and Fall Time

Figure 4. Single-Ended Measurement Points for Vovs, Vuds, Vrb

Table 15. Input Edge Rate

Frequency Min Max Unit

100 MHz 0.35 N/A V/ns

133 MHz 0.35 N/A V/ns

+150 mV

-150 mV

Slew_rise

+150 mV

-150 mV

Slew_fall

0.0 V V_s wing 0 .0 V

Diff

Vovs

VHigh

Vrb

VLow

Vrb

Vuds

Si53119

18 Rev. 1.3

Figure 5. Differential (CLOCK–CLOCK) Measurement Points (Tperiod, Duty Cycle, Jitter)

3.2. Termination of Differential Outputs

All differential outputs are to be tested into a 100  or 85  differential impedance transmission line. Source

terminated clocks have some inherent limitations as to the maximum trace length and frequencies that can be

supported. For CPU outputs, a maximum trace length of 10” and a maximum of 200 MHz are assumed. For SRC

clocks, a maximum trace length of 16” and maximum frequency of 100 MHz is assumed. For frequencies beyond

200 MHz, trace lengths must be restricted to avoid signal integrity problems.

3.2.1. Termination of Differential NMOS Push-Pull Type Outputs

Figure 6. 0.7 V Configuration Test Load Board Termination for NMOS Push-Pull

Table 16. Differential Output Termination

Clock Board Trace Impedance Rs Rp Unit

DIFF Clocks—50  configuration 100 33+5% N/A 

DIFF Clocks—43  configuration 85 27+5% N/A 

TPeriod

Low Duty Cycle %

High Duty Cycle %

Skew measurement

point

0.000 V

T-Line

10" Typical

T-Line

10" Typical

Receiver

2 pF

Source Terminated

Clock

Clock #

Si53119

Rev. 1.3 19

4. Control Registers

4.1. Byte Read/Write

Reading or writing a register in an SMBus slave device in byte mode always involves specifying the register

number.

4.1.1. Byte Read

The standard byte read is as shown in Figure 7. It is an extension of the byte write. The write start condition is

repeated; then, the slave device st arts sending data, and the ma ster acknowledges it until the last byte is sent. The

master terminates the transfer with a NAK, then a stop condition. For byte operation, the 2 x 7th bit of the

command byte must be set. For block operations, the 2 x 7th bit must be reset. If the bit is not set, the next byte

must be the byte transfer count.

Figure 7. Byte Read Protocol

4.1.2. Byte Write

Figure 8 illustrates a simple, typical byte write. For byte operation, the 2 x 7th bit of the command byte must be set.

For block operations, the 2 x 7th bit must be reset. If the bit is not set, the next byte must be the byte tran sfer count.

The count can be between 1 and 32. It is not allowed to be zero or to exce ed 32.

Figure 8. Byte Write Protocol

SlaveTWr ACommand Slave A

Rd Data Byte 0 NP

Command

starT

Condition

Byte Read Protocol

Acknowledge

repeat starT Not ack

stoP

Condition

read

2 x 7 bit = 1

17118 117 11811

Master to

Slave to

SlaveTWr ACommand Data Byte 0A

Command

starT Condition

Byte Write Protocol

Acknowledge

write

2 x 7 bit = 1

17118 1 8 11

Master to

Slave to

stoP Condition

Si53119

20 Rev. 1.3

4.2. Block Read/Write

4.2.1. Block Read

After the slave address is sent with the R/W condition bit set, the command byte is sent with the MSB = 0. The

slave acknowledges the register index in the command byte. The master sends a repeat start function. After the

slave acknowledges this, the slave sends the number of bytes it wants to transfer (>0 and <33). The master

acknowledges each byte except the last and sends a stop function.

Figure 9. Block Read Protocol

4.2.2. Block Write

After the slave addr ess is s en t w ith th e R/W co nd itio n bi t not set, the command byte is sent with the MSB = 0. The

lower seven bits indicate the register at which to start the transfer. If the command byte is 00h, the slave device will

be compatible with existing block mode slave devices. The next byte of a write must be the count of bytes that the

master will transfer to the slave device. The byte count must be greater than zero and less than 33. Following this

byte are the data bytes to be transferred to the slave device. The slave device always acknowledges each byte

received. The transfer is terminated after the slave sends the ACK and the master sends a stop function.

Figure 10. Block Write Protocol

SlaveTWr ACommand Code

Command

starT

Condition

Block Read Protocol

Acknowledge

repeat starT

read

2 x 7 bit = 1

17118

Master to

Slave to

Slave A

11 7 11

Data Byte AData Byte 0 AData Byte 1 N P

8181811

Not acknowledge

stoP Condition

Slave AddressTWr ACommand

Command bit

starT

Condition

Block Write Protocol

Acknowledge

write

2 x 7 bit = 0

1711 8 Master to

Slave to

Data Byte 0 AData Byte 1 A P

181811

stoP Condition

Byte Count = 2 A

Si53119

Rev. 1.3 21

4.3. Control Registers

Table 17. Byte 0: Frequency Select, Output Enable, PLL Mode Control Register

Bit Description If Bit = 0 If Bit = 1 Type Default Output(s)

Affected

0 100M_133M#

Frequency Select 133 MHz 100 MHz R Latched at

power up DIF[11:0]

1 Reserved 0

2 Reserved 0

3 Output Enable DIF 16 Low/Low Enable RW 1 DIF_16

4 Output Enable DIF 17 Low/Low Enable RW 1 DIF_17

5 Output Enable DIF 18 Low/Low Enable RW 1 DIF_18

6 PLL Mode 0 See PLL Operating Mo de

Readback Table R Latched at

power up

7 PLL Mode 1 See PLL Operating Mo de

Readback Table R Latched at

power up

Table 18. Byte 1: Output Enable Control Register

Bit Description If Bit = 0 If Bit = 1 Type Default Output(s)

Affected

0 Output Enable DIF 0 Low/Low Enabled RW 1 DIF[0]

1 Output Enable DIF 1 Low/Low Enabled RW 1 DIF[1]

2 Output Enable DIF 2 Low/Low Enabled RW 1 DIF[2]

3 Output Enable DIF 3 Low/Low Enabled RW 1 DIF[3]

4 Output Enable DIF 4 Low/Low Enabled RW 1 DIF[4]

5 Output Enable DIF 5 Low/Low Enabled RW 1 DIF[5]

6 Output Enable DIF 6 Low/Low Enabled RW 1 DIF[6]

7 Output Enable DIF 7 Low/Low Enabled RW 1 DIF[7]

Si53119

22 Rev. 1.3

Table 19. Byte 2: Output Enable Control Register

Bit Description If Bit = 0 If Bit = 1 Type Default Output(s)

Affected

0 Output Enable DIF 8 Low/Low Enabled RW 1 DIF[8]

1 Output Enable DIF 9 Low/Low Enabled RW 1 DIF[9]

2 Output Enable DIF 10 Low/Low Enabled RW 1 DIF[10]

3 Output Enable DIF 11 Low/Low Enabled RW 1 DIF[11]

4 Output Enable DIF 12 Low/Low Enabled RW 1 DIF[112

5 Output Enable DIF 13 Low/Low Enabled RW 1 DIF[14]

6 Output Enable DIF 14 Low/Low Enabled RW 1 DIF[15]

7 Output Enable DIF 15 Low/Low Enabled RW 1 DIF[16

Table 20. Byte 3: Reserved Control Register

Bit Description If Bit = 0 If Bit = 1 Type Default Output(s)

Affected

0 Reserved 0

1 Reserved 0

2 Reserved 0

3 Reserved 0

4 Reserved 0

5 Reserved 0

6 Reserved 0

7 Reserved 0

Si53119

Rev. 1.3 23

Table 21. Byte 4: Reserved Control Register

Bit Description If Bit = 0 If Bit = 1 Type Default Output(s)

Affected

0 Reserved 0

1 Reserved 0

2 Reserved 0

3 Reserved 0

4 Reserved 0

5 Reserved 0

6 Reserved 0

7 Reserved 0

Table 22. Byte 5: Vendor/Revision Identification Control Register

Bit Description If Bit = 0 If Bit = 1 Type Default Output(s)

Affected

0 Vendor ID Bit 0 R Vendor Specific 0

1 Vendor ID Bit 1 R Vendor Specific 0

2 Vendor ID Bit 2 R Vendor Specific 0

3 Vendor ID Bit 3 R Vendor Specific 1

4 Revision Code Bit 0 R Vendor Specific 0

5 Revision Code Bit 1 R Vendor Specific 0

6 Revision Code Bit 2 R Vendor Specific 0

7 Revision Code Bit 3 R Vendor Specific 0

Si53119

24 Rev. 1.3

Table 23. Byte 6: Device ID Control Register

Bit Description If Bit = 0 If Bit = 1 Type Default Output(s)

Affected

0 Device ID 0 R 0

1 Device ID 1 R 1

2 Device ID 2 R 1

3 Device ID 3 R 1

4 Device ID 4 R 0

5 Device ID 5 R 1

6 Device ID 6 R 1

7 Device ID 7 (MSB) R 1

Si53119

Rev. 1.3 25

Table 24. Byte 7: Byte Count Register

Bit Description If Bit = 0 If Bit = 1 Type Default Output(s)

Affected

0 BC0 - Writing to this register con-

figures how many bytes will be

read back

RW 0

1 BC1 -W riting to this register con-

figures how many bytes will be

read back

RW 0

2 BC2 -W riting to this register con-

figures how many bytes will be

read back

RW 0

3 BC3 -W riting to this register con-

figures how many bytes will be

read back

RW 1

4 BC4 -W riting to this register con-

figures how many bytes will be

read back

RW 0

5 Reserved 0

6 Reserved 0

7 Reserved 0

Table 25. Byte 18: PLL Mode Control Register

Bit Description If Bit = 0 If Bit = 1 Type Default Outputs

Affected

0 PLL_MODE0 If Byte0[3] = 1 allows the user to over-

ride the latch from pin5 via use of

Byte0[2:1]

00 = L ow Ban d width Mode

01 = Bypass Mode

11 = High Bandwidth Mode

R/W 0

1 PLL_MODE1 R/W 0

2 PLL_SW_EN HW Select I2C Select R/W 0

3 Reserved 0

4 Reserved 0

5 Reserved 0

6 Reserved 0

7 Reserved 0

Si53119

26 Rev. 1.3

5. Pin Descriptions: 72-Pin QFN

Si53119

1VDDA

GNDA

100M_133M

HBW_BYPASS_LBW

PWRGD / PWRDN

GND

VDDR

CLK_IN

SA_0

SDA

SCL

SA_1

FBOUT_NC

GND

DIF_7

DIF_6

GND

VDD

DIF_5

DIF_4

GND

DIF_11

DIF_10

GND

VDD

VDD_IO

DIF_9

DIF_8

VDD_IO

DIF_0

GND

DIF_1

GND

VDD

VDD_IO

DIF_2

DIF_3

VDD_IO

GND

VDD_IO

GND

DIF_12

DIF_13

DIF_14

GND

DIF_15

DIF_16

DIF_17

DIF_18

FBOUT_NC

Si53119

Rev. 1.3 27

Table 26. Si53119 72-Pin QFN Descriptions

Pin # N ame Type Description

1VDDA3.3 V 3.3 V power supply for PLL.

2 GNDA GND Ground for PLL.

3 100M_133M I,SE 3.3 V tolerant inputs for input/output frequency selection. An external

pull-up or pull-down resistor is attached to this pin to select the inpu t/

output frequency.

High = 100 MHz output

Low = 133 MHz output

4 HBW_BYPASS_LBW I, SE Tri-Level input for selecting the PLL bandwidth or bypass mode.

High = High BW mode

Med = Bypass mode

Low = Low BW mode

5 PWRGD/PWRDN I 3.3 V LVTTL input to power up or power down the device.

6GNDGND Ground for ou tputs.

7 VDDR VDD 3.3 V power supply for differential input receiver. This VDDR should

be treated as an analog power rail and filtered appropriately.

8 CLK_IN I, DIF 0.7 V Differential input.

9 CLK_IN I, DIF 0.7 V Differential input.

10 SA_0 I,PU 3.3 V LVTTL input selecting the address. Tri-level input.

11 SDA I/O Open collector SMBus data.

12 SCL I/O SMBus slave clock input.

13 SA_1 I,PU 3.3 V LVTTL input selecting the address. Tri-level input.

14 FB OUT / NC I/O Complementary dif ferential feedback output. Do not connect this pin

to anything.

15 FB OUT / NC I/O True differential feedback output. Do not connect this pin to anything.

16 GND GND Ground for outputs.

17 DIF_0 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

18 DIF_0 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

19 DIF_1 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

20 DIF_1 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

21 VDD_IO VDD Power supply for differential outputs.

22 GND GND Ground for outputs.

23 DIF_2 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

24 DIF_2 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

Si53119

28 Rev. 1.3

25 DIF_3 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

26 DIF_3 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

27 GND GND Ground for outputs.

28 VDD 3.3 V 3.3 V power supply for outputs.

29 DIF_4 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

30 DIF_4 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

31 DIF_5 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

32 DIF_5 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

33 VDD_IO VDD Power supply for differential outputs.

34 GND GND Ground for outputs.

35 DIF_6 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

36 DIF_6 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

37 DIF_7 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

38 DIF_7 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

39 GND GND Ground for outputs.

40 VDD_IO VDD Power supply for differential outputs.

41 DIF_8 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

42 DIF_8 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

43 DIF_9 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

44 DIF_9 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

45 VDD 3.3 V 3.3 V power supply for outputs.

46 GND GND Ground for outputs.

47 DIF_10 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

48 DIF_10 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

49 DIF_11 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

50 DIF_11 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

51 GND GND Ground for outputs.

52 VDD_IO VDD Power supply for differential outputs.

53 DIF_12 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

Table 26. Si53119 72-Pin QFN Descriptions (Continued)

Pin # N ame Type Description

Si53119

Rev. 1.3 29

54 DIF_12 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

55 DIF_13 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

56 DIF_13 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

57 VDD_IO VDD Power supply for differential outputs.

58 GND GND Ground for outputs.

59 DIF_14 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

60 DIF_14 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

61 DIF_15 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

62 DIF_15 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

63 GND GND Ground for outputs.

64 VDD 3.3 V 3.3 V power supply for outputs.

65 DIF_16 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

66 DIF_16 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

67 DIF_17 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

68 DIF_17 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

69 VDD_IO VDD Power supply for differential outputs.

70 GND GND Ground for outputs.

71 DIF_18 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

72 DIF_18 O, DIF 0.7 V Differential clock outputs. Default is 1:1.

73 GND GND Ground for outputs.

Table 26. Si53119 72-Pin QFN Descriptions (Continued)

Pin # N ame Type Description

Si53119

30 Rev. 1.3

6. Power Filtering Example

6.1. Ferrite Bead Power Filtering

Recommended ferrite bead filtering equivalent to the following: 600  impedance at 100 MHz, < 0.1  DCR max.,

>400 mA current ra ting .

Figure 11. Schematic Example of the Si53119 Power Filtering

Si53119

Rev. 1.3 31

7. Ordering Guide

Part Number Package Type Temperature

Lead-free

Si53119-A01AGM 72-pin QFN Extended, –40 to 85 C

Si53119-A01AGMR 72-pin QFN—Tape and Reel Extended, –40 to 85 C

Si53119

32 Rev. 1.3

8. Package Outline

Figure 12 illustrates the package details for the Si53119. Table 27 lists the values for the dimensions shown in the

illustration.

Figure 12. 72-Pin Quad Flat No Lead (QFN) Package

Table 27. Package Dimensions

Dimension Min Nom Max Dimension Min Nom Max

A 0.80 0.85 0.90 E2 5.90 6.00 6.10

A1 0.00 0.02 0.05 L 0.30 0.40 0.50

b 0.18 0.25 0.30 aaa 0.10

D 10.00 BSC. bbb 0.10

D2 5.90 6.00 6.10 ccc 0.08

e 0.50 BSC. ddd 0.10

E 10.00 BSC. eee 0.05

Notes:

1. All dimensions shown are in millimeters (mm) unless otherwise noted.

2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.

3. This drawing conforms to JEDEC outline MO-220

4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.

Si53119

Rev. 1.3 33

9. Land Pattern: 72-pin QFN

Figure 13 shows the recommended land p attern det ails for th e Si53119 in a 72-pin QFN package. Table 28 lists the

values for the dimensions shown in the illustration.

Figure 13. 72-pin QFN Land Pattern

Table 28. PCB Land Pattern Dimensions

Dimension mm

C1 9.90

C2 9.90

E0.50

X1 0.30

Y1 0.85

X2 6.10

Y2 6.10



Si53119

34 Rev. 1.3

DOCUMENT CHANGE LIST

Revision 0.9 to Revision 1.0

Corrected specs in Table 6, “Phase Jitter,” on

page 8.

Revision 1.0 to Revision 1.1

Updated Features on page 1.

Updated Description on page 1.

Updated specs in Table 6, “Phase Jitter,” on page 8.

Revision 1.1 to Revision 1.2

February 22, 2016

Corrected specs in Table 1, “DC Operating

Characteristics,” on page 4.

Updated opera tin g cha r act eri stic s in Table 3,

Table 4, and Table 5.

Revision 1.2 to Revision 1.3

November 22, 2017

Removed Gen4 PLL mode jitter spec.

Added Table 25, “Byte 18: PLL Mode Control

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