MIC23450-AAAYML-TR - MICROCHIP TECHNOLOGY

Supertex inc. MD1811

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

Features

►6.0ns rise and fall time

►2.0A peak output source/sink current

►1.8 to 5.0V input CMOS compatible

►5.0 to 12V total supply voltage

►Smart logic threshold

►Low jitter design

►Quad matched channels

►Drives two P- and two N-channel MOSFETs

►Outputs can swing below ground

►Low inductance quad at no-lead package

►High-performance thermally-enhanced QFN

Applications

►Medical ultrasound imaging

►Piezoelectric transducer drivers

►Non-Destructive Testing (NDT)

►PIN diode driver

►Clock driver/buffer

►High speed level translator

General Description

The Supertex MD1811 is a high speed, quad MOSFET driver designed

to drive high voltage P and N-channel MOSFETs for medical ultrasound

applications and other applications requiring a high output current for

a capacitive load. The high-speed input stage of the MD1811 can

operate from a 1.8 to 5.0V logic interface with an optimum operating

input signal range of 1.8 to 3.3V. An adaptive threshold circuit is used to

set the level translator switch threshold to the average of the input logic

0 and logic 1 levels. The input logic levels may be ground referenced,

even though the driver is putting out bipolar signals. The level translator

uses a proprietary circuit, which provides DC coupling together with

high-speed operation.

The output stage of the MD1811 has separate power connections

enabling the output signal L and H levels to be chosen independently

from the supply voltages used for the majority of the circuit. As an

example, the input logic levels may be 0 and 1.8V, the control logic

may be powered by +5.0 and -5.0V, and the output L and H levels

may be varied anywhere over the range of -5.0 to +5.0V. The output

stage is capable of peak currents of up to ±2.0A, depending on the

supply voltages used and load capacitance present. The OE pin serves

a dual purpose. First, its logic H level is used to compute the threshold

voltage level for the channel input level translators. Secondly, when OE

is low, the outputs are disabled, with the A & C output high and the B

& D output low. This assists in properly pre-charging the AC coupling

capacitors that may be used in series in the gate drive circuit of an

external PMOS and NMOS transistor pair.

Typical Application Circuit

0.22µF

3.3V CMOS

Logic Inputs

OUTA

OUTB

OUTC

OUTD

VDDVH

+10V

VSS VLGND

INA

INB

INC

IND

ENAB

10nF

To Piezoelectric

Transducer #1

-100V

Supertex MD1811

0.47µF

1.0µF

+PLS1

-PLS1

+PLS2

-PLS2

10nF

+100V

-100V

+100V

Supertex TC6320

To Piezoelectric

Transducer #2

+10V

High Speed Quad MOSFET Driver

MD1811

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

VDD-VSS Logic supply voltage 4.5 - 13 V 2.5V ≤ VDD ≤13V

VSS Low side supply voltage -5.5 - 0 V --

VHOutput high supply voltage VSS +2.0 - VDD V --

VLOutput low supply voltage VSS - VDD -2.0 V --

IDDQ VDD quiescent current - 0.8 - mA No input transitions, OE = 1

IHQ VH quiescent current - 10 µA

IDD VDD average current - 8.0 - mA One channel on at 5.0Mhz,

No load

IHVH average current - 26 - mA

VIH Input logic voltage high VOE -0.3 - 5.0 V

For logic inputs

INA, INB, INC, and IND

VIL Input logic voltage low 0 - 0.3 V

IIH Input logic current high - - 1.0 µA

IIL Input logic current low - - 1.0 µA

VIH OE Input logic voltage high 1.7 - 5.0 V

For logic input OEVIL OE Input logic voltage low 0 - 0.3 V

RIN Input logic impedance to GND 10 20 30 KΩ

CIN Logic input capacitance - 5.0 10 pF ---

Ordering Information

Device

16-Lead QFN

4.00x4.00mm body

1.00mm height (max)

0.65mm pitch

MD1811 MD1811K6-G

DC Electrical Characteristics (VH = VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TA = 25°C)

Sym Parameter Min Typ Max Units Conditions

Absolute Maximum Ratings

Parameter Value

VDD - VSS, Logic supply voltage -0.5V to +13.5V

VH, Output high supply voltage VL -0.5V to VDD+0.5V

VL, Output low supply voltage VSS -0.5V to VH+0.5V

VSS, Low side supply voltage -7.0V to +0.5V

Logic input levels VSS -0.5V to GND +7.0V

Maximum junction temperature +125°C

Storage temperature -65°C to 150°C

Operating temperature -20°C to +85°C

Package power dissipation 2.2W

Thermal resistance (θJA)* 45°C/W

-G indicates package is RoHS compliant (‘Green’)

Absolute Maximum Ratings are those values beyond which damage to the device

may occur. Functional operation under these conditions is not implied. Continuous

operation of the device at the absolute rating level may affect device reliability. All

voltages are referenced to device ground.

* 1.0oz 4-layer 3x4” PCB

1811

YWLL

Y = Last Digit of Year Sealed

W = Code for Week Sealed

L = Lot Number

= “Green” Packaging

Product Marking

16-Lead QFN (K6)

(top view)

Pin Conguration

Package may or may not include the following marks: Si or

MD1811

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

RSINK Output sink resistance - - 12.5 ΩISINK = 50mA

RSOURCE Output source resistance - - 12.5 ΩISOURCE = 50mA

ISINK Peak output sink current - 2.0 - A --

ISOURCE Peak output source current - 2.0 - A --

AC Electrical Characteristics (VH = VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TA = 25°C)

Sym Parameter Min Typ Max Units Conditions

tirf Input or OE rise & fall time - - 10 ns Logic input edge speed

requirement

tPLH

Propagation delay when output

is from low to high - 7.0 - ns

CLOAD = 1000pF, see timing

diagram

Input signal rise/fall time 2ns

tPHL

Propagation delay when output

is from high to low - 7.0 - ns

trOutput rise time - 6.0 - ns

tfOutput fall time - 6.0 - ns

l tr - tf l Rise and fall time matching - 1.0 - ns

For each channel

l tPLH-tPHL lPropagation low to high and

high to low matching - 1.0 - ns

∆tdm Propagation delay matching - ±2.0 - ns Device to device delay match

tOE Output enable time - 9.0 - ns ---

Logic Truth Table

Logic Inputs Output

OE INA INB OUTA OUTB

H L L VHVH

H L H VHVL

H H L VLVH

H H H VLVL

L X X VHVL

OE INC IND OUTC OUTD

H L L VHVH

H L H VHVL

H H L VLVH

H H H VLVL

L X X VHVL

Outputs (VH = VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TA = 25°C)

Sym Parameter Min Typ Max Units Conditions

MD1811

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

Simplied Block Diagram

Detailed Block Diagram

INA

INB

OUTA

OUTB

INC

IND

OUTC

OUTD

MD1811

GND VSS VL

VDD VH

INB

VDD

OUTC

OUTD

GND

VSS

VDD

VDD VH

INA

VSS VL

OUTB

OUTA

VDD VH

INC

IND

VSS

SUB

VSS VL

Level

Shifter

Level

Shifter

Level

Shifter

Level

Shifter

Level

Shifter

MD1811

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

Application Information

For proper operation of the MD1811, low inductance bypass

capacitors should be used on the various supply pins. The

GND pin should be connected to the logic ground. The INA,

INB INC, IND, and OE pins should be connected to a logic

source with a swing of GND to OE, where OE is 1.8 to 5.0V.

Good trace practices should be followed corresponding to the

desired operating speed. The internal circuitry of the MD1811

is capable of operating up to 100MHz, with the primary speed

limitation being the loading effects of the load capacitance.

Because of this speed and the high transient currents that

result with capacitive loads, the bypass capacitors should

be as close to the chip pins as possible. Unless the load

specically requires bipolar drive, the VSS and VL pins should

have low inductance feed-through connections directly to a

ground plane. If these voltages are not zero, then they need

bypass capacitors in a manner similar to the positive power

supplies. The power connection VDD should have a ceramic

bypass capacitor to the ground plane with short leads and

decoupling components to prevent resonance in the power

leads.

The voltages of VH and VL decide the output signal levels.

These two pins can draw fast transient currents of up to

2.0A, so they should be provided with an appropriate bypass

capacitor located next to the chip pins. A ceramic capacitor

of up to 1.0µF may be appropriate, with a series ferrite bead

to prevent resonance in the power supply lead coming to

the capacitor. Pay particular attention to minimizing trace

lengths, current loop area and using sufcient trace width to

reduce inductance. Surface mount components are highly

recommended. Since the output impedance of this driver is

very low, in some cases it may be desirable to add a small

series resistance in series with the output signal to obtain

better waveform transitions at the load terminals. This will of

course reduce the output voltage slew rate at the terminals

of a capacitive load.

Pay particular attention that parasitic couplings are minimized

from the output to the input signal terminals. The parasitic

feedback may cause oscillations or spurious waveform

shapes on the edges of signal transitions. Since the input

operates with signals down to 1.8V even small coupled

voltages may cause problems. Use of a solid ground plane

and good power and signal layout practices will prevent this

problem. Be careful that a circulating ground return current

from a capacitive load cannot react with common inductance

to cause noise voltages in the input logic circuitry.

Timing Diagram and VTH / VOE Curve

2.0

1.5

1.0

0.5

0 1.0 2.0 3.0 4.0 5.0

0.6V

OE/2

PLH

10%

90%

50% 50%

PHL

90%

10%

vs V

3.3V

INPUT

12V

OUTPUT

MD1811

Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com

Pin # Function Description

1 INB Logic input. Input logic low will cause the output to swing to VH. Input logic high will

cause the output to swing to VL. Keep all logic inputs low until IC powered up.

2 VL Supply voltage for N-channel output stage.

3 GND Logic input ground reference.

4 VL Supply voltage for N-channel output stage.

5 INC Logic input. Input logic low will cause the output to swing to VH. Input logic high will

cause the output to swing to VL. Keep all logic inputs low until IC powered up.

6 IND

7 VSS Low side supply voltage. VSS is also connected to the IC substrate. It is required to

connect to the most negative potential of voltage supplies and powered-up rst.

8 OUTD

Output driver. Swings from VH to VL. Intended to drive the gate of an externel N-

channel MOSFET via a series capacitor. When OE is low, the output is disabled.

OUTD will swing to VL turning off the external N-channel MOSFET.

9 OUTC

Output driver. Swings from VH to VL. Intended to drive the gate of an externel P-

channel MOSFET via a series capacitor. When OE is low, the output is disabled.

OUTC will swing to VH turning off the external P-channel MOSFET.

10, 11 VH Supply voltage for P-channel output stage.

12 OUTB

Output driver. Swings from VH to VL. Intended to drive the gate of an externel N-

channel MOSFET via a series capacitor. When OE is low, the output is disabled.

OUTB will swing to VL turning off the external N-channel MOSFET.

13 OUTA

Output driver. Swings from VH to VL. Intended to drive the gate of an externel P-

channel MOSFET via a series capacitor. When OE is low, the output is disabled.

OUTA will swing to VH turning off the external P-channel MOSFET.

14 VDD High side supply voltage.

15 INA Logic input. Input logic low will cause the output to swing to VH. Input logic high will

cause the output to swing to VL. Keep all logic inputs low until IC powered up.

16 OE

Output-Enable logic input. When OE is high, (VOE+VGND)/2 sets the logic threshold

level for inputs, When OE is low, OUTA and OUTC are at VH, OUTB and OUTD are at

VL, regardless of the inputs INA, INB, INC or IND. Keep OE low until IC powered up.

Substrate The IC substrate is internally connected to the thermal pad. Thermal Pad and VSS

must be connected externally.

Pin Description

Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives

an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability

to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and

specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com)

1235 Bordeaux Drive, Sunnyvale, CA 94089

Tel: 408-222-8888

www.supertex.com

MD1811

(The package drawing(s) in this data sheet may not reect the most current specications. For the latest package outline

information go to http://www.supertex.com/packaging.html.)

Doc.# DSFP-MD1811

D011612

16-Lead QFN Package Outline (K6)

4.00x4.00mm body, 1.00mm height (max), 0.65mm pitch

Symbol A A1 A3 b D D2 E E2 e L L1 θ

Dimension

(mm)

MIN 0.80 0.00

0.20

REF

0.25 3.85* 2.50 3.85* 2.50

0.65

BSC

0.30†0.00 0O

NOM 0.90 0.02 0.30 4.00 2.65 4.00 2.65 0.40†- -

MAX 1.00 0.05 0.35 4.15* 2.80 4.15* 2.80 0.50†0.15 14O

JEDEC Registration MO-220, Variation VGGC-2, Issue K, June 2006.

* This dimension is not specied in the JEDEC drawing.

† This dimension differs from the JEDEC drawing.

Drawings not to scale.

Supertex Doc.#: DSPD-16QFNK64X4P065, Version C041009.

Seating

Plane

Top View

Side View

Bottom View

View B

Note 3

Note 2

Note 1

(Index Area

D/2 x E/2)

Note 1

(Index Area

D/2 x E/2)

Notes:

1. A Pin 1 identier must be located in the index area indicated. The Pin 1 identier can be: a molded mark/identier; an embedded metal marker; or

a printed indicator.

2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present.

3. The inner tip of the lead may be either rounded or square.