Integrated
Circuit
Systems, Inc.
ICS950805
0649G—06/11/02
Block Diagram
Recommended Application:
CK-408 clock for Almador-M and Brookdale-Mobile
chipsets. Programmable for group to group skew.
Output Features:
• 3 Differential CPU Clock Pairs (differential current
mode)
• 7 PCI (3.3V) @ 33.3MHz
• 3 PCI_F (3.3V) @ 33.3MHz
• 1 USB (3.3V) @ 48MHz
• 1 DOT (3.3V) @ 48MHz
• 1 REF (3.3V) @ 14.318MHz
• 1 3V66 (3.3V) @ 66.6MHz
• 1 VCH/3V66 (3.3V) @ 48MHz or 66.6MHz
• 3 66MHz_OUT/3V66 (3.3V) @ 66.6MHz_IN
or 66.6MHz
• 1 66MHz_IN/3V66 (3.3V) @ Input/66MHz
Features:
• Almador Chipset has a DLL driving the clock buffer
path for the 3 buffer path 66.6 MHz outputs,
66Buf(0:2). Almador board level designs MUST
use pin 22, 66Buf_1, as the feedback connection
from the clock buffer path to the Almador
(GMCH) chipset.
• Supports spread spectrum modulation,
down spread 0 to -0.5%.
• Efficient power management scheme through PD#,
CPU_STOP# and PCI_STOP#.
Key Specifications:
•CPU Output Jitter <150ps
• 3V66 Output Jitter <250ps
• 66MHz Output Jitter (Buffered Mode Only) <100ps
• CPU Output Skew <100ps
Pin Configuration
56-Pin 300mil SSOP
6.10 mm. Bod y, 0.50 mm. pitch TSSOP
Frequency Generator with 200MHz Differential CPU Clocks
VDDREF
X1
X2
GND
PCICLK_F0
PCICLK_F1
PCICLK_F2
VDDPCI
GND
PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
66MHz_OUT0/3V66_2
66MHz_OUT1/3V66_3
66MHz_OUT2/3V66_4
66MHz_IN/3V66_5
*PD#
VDDA
GND
Vtt_PWRGD#
REF
FS1
FS0
CPU_STOP#*
CPUCLKT0
CPUCLKC0
VDDCPU
CPUCLKT1
CPUCLKC1
GND
VDDCPU
CPUCLKT2
CPUCLKC2
MULTSEL0*
I REF
GND
FS2
48MHz_USB
48MHz_DOT
VDD48
GND
3V66_1/VCH_CLK
PCI_STOP#*
3V66_0
VDD3V66
GND
SCLK
SDATA
ICS950805
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Functionality
PLL2
PLL1
Spread
Spectrum
3V66_5/66MHz_IN
3V66_3/66MHz_OUT1
3V66_(4,2)/66MHz_OUT(2,0
)
48MHz_USB
48MHz_DOT
X1
X2 XTAL
OSC
3V66
DIVDER
PD#
CPU_STOP#
PCI_STOP#
MULTSEL0
SDATA
SCLK
FS (2:0)
I REF
Control
Logic
Config.
Reg.
REF
66MHz_0
CPU
DIVDER 3
3CPUCLKT (2:0)
CPUCLKC (2:0)
Stop
3V66_1/VCH_CLK
PCICLK (6:0)
PCI
DIVDER
3
7
PCICLK_F (2:0)
Stop
* These inputs ha ve 150K internal pull-up resistor to VDD.
2SF1SF0SF UPC )zHM( )0:1(66V3 )zHM( )0:2(tuOzHM66 )2:4(66V3 )zHM(
F_ICP ICP )zHM(
nIzHM66 )5(66V3 )zHM(
000 66.6666.6666.6633.3366.66
001 00.00166.6666.6633.3366.66
010 00.00266.6666.6633.3366.66
011 33.33166.6666.6633.3366.66
100 66.6666.66NI_zHM662/NI_zHM66NI_zHM66
10 1 00.00166.66NI_zHM662/NI_zHM66NI_zHM66
110 00.00266.66NI_zHM662/NI_zHM66NI_zHM66
111 33.33166.66NI_zHM662/NI_zHM66NI_zHM66
diM00 etatsirTetatsirTetatsirTetatsirTetatsirT
diM01 2/KLCT4/KLCT4/KLCT8/KLCT4/KLCT
diM10 devreseRdevreseRdevreseRdevreseRdevreseR
diM11 devreseRdevreseRdevreseRdevreseRdevreseR
2
ICS950805
0649G—06/11/02
Pin Configuration
Power Groups
(Analog)
VDDA = PLL1
VDD48 = 48MHz, PLL
VDDREF = VDD for Xtal, POR
(Digital)
VDDPCI
VDD3V66
VDDCPU
REBMUNNIPEMANNIPEPYTNOITPIRCSED
,62,91,41,8,1 05,64,73,23 DDVRWPylppusrewopV3.3
21XtupnIlatsyrC2XtupnilatsyrCzHM813.41
32XlatsyrC1X tuptuO tuptuolatsyrCzHM813.41
5,6,7
)0:2(F_KLCICPTUO rewoprof#POTS_ICPybdetceffatonkcolcICPgninnureerF .tnemeganam
,72,02,51,9,4 74,14,63,13 DNGRWPylppusV3.3rofsnipdnuorG
,31,61,71,81 01,11,21 )0:6(KLCICPTUOstuptuokcolcICP
12,22,32 )0:2(TUO_zHM66TUO.tupniNI_zHM66morfTUO_zHM66dereffubzHM66
)2:4(66V3TUOOCVlanretnimorf,skcolcecnereferzHM66
42 NI_zHM66NIskcolcICPdnaTUO_zHM66dereffubottupnizHM66
5_66V3TUOOCVlanretnimorf,kcolcecnereferzHM66
52#DPNI.woLevitcA.edomnwod-rewopsekovnI
82#DGRWP_ttV
NI enimretedotdesuebortsevitisneslevelasitupniLTTVLV3.3sihT ebotydaereradnadilaverastupni0LESITLUMdna]2:0[SFnehw delpmas )wolevitca(
92ATADS
O/IIrofnipataD
2
tnarelotV5yrtiucricC
03KLCS
NIIfonipkcolC
2
tnarelotV5yrtiucricC
330_66V3TUOOCVlanretnimorf,skcolcecnereferzHM66
43#POTS_ICPNItpecxewoltupninehw,level0cigoltaskcolcKLCICPstlaH gninnureerferahcihwF_KLCICP
53KLC_HCV/1_66V3TUO hguorhtelbatcelestuptuoV3.3
I
2
C
roOCVlanretnimorfzHM66ebot
)CSS-non(zHM84
83TOD_zHM84TUOTODrofkcolctuptuozHM84
93BSU_zHM84TUOBSUrofkcolctuptuozHM84
042SFNInoitcelesedoMroftupniV3.3laicepS
24FERITUO nipsihT.sriapKLCUPCehtroftnerrucecnereferehtsehsilbatsenipsihT ehthsilbatseotredronidnuorgotdeitrotsisernoisicerpdexifaseriuqer .tnerrucetairporppa
340LESTLUMNI stuptuoUPCrofreilpitlumtnerrucehtgnitcelesroftupniLTTVLV3.3
15,84,44)0:2(CKLCUPCTUO tnerruceraesehT.stuptuoUPCriaplaitnereffidfoskcolc"yrotnemelpmoC" .saibegatlovrofderiuqererasrotsiserlanretxednastuptuo
25,94,54)0:2(TKLCUPCTUO dnastuptuotnerruceraesehT.stuptuoUPCriaplaitnereffidfoskcolc"eurT" .saibegatlovrofderiuqererasrotsiserlanretxe
35#POTS_UPCNIwoltupninehw,level0cigoltaskcolcKLCUPCstlaH
45,55)0:1(SFNIsniptcelesycneuqerF
65FERTUO.kcolcecnereferzHM813.41
3
ICS950805
0649G—06/11/02
Host Swing Select Functions
0LESITLUM tegraTdraoB ZmreT/ecarT
,RecnerefeR =ferI
V
DD
)rR*3(/
tuptuO tnerruC Z@hoV
0smho05 ,%1122=rR Am00.5=ferI FERI*4=hoI05@V0.1
1smho05 ,%1574=rR Am23.2=ferI FERI*6=hoI05@V7.0
T ruth Table
Maximum Allowed Current
noitidnoC
noitpmusnocylppusV3.3xaM ,sdaolpacetercsidxaM V564.3=ddV DNGroddV=stupnicitatsllA
edoMnwodrewoP )0=#NWDRWP( Am04
evitcAlluF Am063
2SF1SF0SF UPC )zHM( 66V3 )0:1( )zHM(
)0:2(ffuB66 )2:4(66V3 )zHM( /NI_zHM66 5_66V3 F_ICP ICP )zHM( 0FER )zHM( TOD/BSU )zHM(
000 66.6666.6666.6666.6633.33813.4100.84
001 00.00166.6666.6666.6633.33813.4100.84
010 00.00266.6666.6666.6633.33813.4100.84
011 33.33166.6666.6666.6633.33813.4100.84
100 66.6666.66NI_zHM66tupnI2/NI_zHM66813.4100.84
10 1 00.00166.66NI_zHM66tupnI2/NI_zHM66813.4100.84
110 00.00266.66NI_zHM66tupnI2/NI_zHM66813.4100.84
111 33.33166.66NI_zHM66tupnI2/NI_zHM66813.4100.84
diM00 etatsirTetatsirTetatsirTetatsirTetatsirTetatsirTetatsirT
diM01 2/KLCT4/KLCT4/KLCT4/KLCT8/KLCTKLCT2/KLCT
diM10 devreseRdevreseRdevreseRdevreseRdevreseRdevreseRdevreseR
diM11 devreseRdevreseRdevreseRdevreseRdevreseRdevreseRdevreseR
4
ICS950805
0649G—06/11/02
Byte 0: Control Register
Byte 1: Control Register
tiB#niPemaNDWP
2
epyT
1
noitpircseD
0tiB450SFXR nodelpmasnip0SFfoeulavehtstcelfeR purewop
1tiB551SFXR nodelpmasnip1SFfoeulavehtstcelfeR purewop
2tiB042SFXR nodelpmasnip2SFfoeulavehtstcelfeR purewop
3tiB43#POTS_ICP
3
XR foeulavehtstcelfeR:edomerawdraH DWPnodelpmasnip#POTS_ICP
1WR:edomerawtfoS deppotsKLCICP=0 deppotstonKLCICP=1
4tiB35#POTS_UPCXR lanretxeehtfoeulavtnerrucehtstcelfeR nip#POTS_UPC
5tiB53HCV/1_66V30WRzHM84/zHM66tceleSHCV zHM84=1,zHM66=0
6tiB- )0:2(T_UPC0 leveltuptuoslortnocedomnwodrewopnI hgihpots=0 wolpots=1
7tiB- delbanEdaerpS0WRnOdaerpS=1,ffOdaerpS=0
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways.
Wither the system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert
PCI_STOP functionality via I2C Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the I2C Byte 0 Bit3. In Software mode it is not allowed to pull the
external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped
PCI_STOP conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it
is not allowed to mix these modes.
In Hardware mode the I2C byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip
is in PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (I2C Byte 0 Bit 3 = 0)].
4. For disabled clocks, they stop low for single ended clocks. Differential CPU clocks stop with CPUCLKT at high,
CPUCLKC off, and external resistor termination will bring CPUCLKC low.
tiB#niPemaNDWP
2
epyT
1
noitpircseD
0tiB15,25 0TKLCUPC 0CKLCUPC 1WRdelbanE=1delbasiD=0
4
1tiB84,94 1TKLCUPC 1CKLCUPC 1WRdelbanE=1delbasiD=0
4
2tiB44,54 2TKLCUPC 2CKLCUPC 1WRdelbanE=1delbasiD=0
4
3tiB15,25 0TKLCUPC 0CKLCUPC 0WRnoitressahtiw0C/0TKLCUPCfolortnocwollA eerF=1gninnureerftoN=0#POTS_UPCfo gninnur
4tiB84,94 1TKLCUPC 1CKLCUPC 0WRnoitressahtiw1C/1TKLCUPCfolortnocwollA eerF=1gninnureerftoN=0#POTS_UPCfo gninnur
5tiB44,54 2TKLCUPC 2CKLCUPC 0WRnoitressahtiw2C/2TKLCUPCfolortnocwollA eerF=1gninnureerftoN=0#POTS_UPCfo gninnur
6tiB- - 0 - )devreseR(
7tiB340LESTLUMXR 0LESTLUMfoeulavtnerrucehtstcelfeR
5
ICS950805
0649G—06/11/02
Byte 2: Control Register
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
tiB#niPemaNDWPepyTnoitpircseD
0tiB010KLCICP1WRdelbanE=1delbasiD=0
1tiB111KLCICP1WRdelbanE=1delbasiD=0
2tiB212KLCICP1WRdelbanE=1delbasiD=0
3tiB313KLCICP1WRdelbanE=1delbasiD=0
4tiB614KLCICP1WRdelbanE=1delbasiD=0
5tiB715KLCICP1WRdelbanE=1delbasiD=0
6tiB816KLCICP1WRdelbanE=1delbasiD=0
7tiB- - 0 - )devreseR(
Byte 3: Control Register
Byte 4: Control Register
tiB#niPemaNDWPepyTnoitpircseD
0tiB122-66V3/0TUO_zHM661WRdelbanE=1delbasiD=0
1tiB223-66V3/0TUO_zHM661WRdelbanE=1delbasiD=0
2tiB324-66V3/0TUO_zHM661WRdelbanE=1delbasiD=0
3tiB425_66V31WRdelbanE=1delbasiD=0
4tiB53KLC_HCV/1_66V31WRdelbanE=1delbasiD=0
5tiB330_66V31WRdelbanE=1delbasiD=0
6tiB- - 0 R )devreseR(
7tiB- - 0 R )devreseR(
tiB#niPemaNDWPepyTnoitpircseD
0tiB5 0F_KLCICP1WRdelbanE=1delbasiD=0
1tiB6 1F_KLCICP1WRdelbanE=1delbasiD=0
2tiB7 2F_KLCICP1WRdelbanE=1delbasiD=0
3tiB5 0F_KLCICP0WRfonoitressahtiw0F_KLCICPfolortnocwollA eerftoN=1,gninnuReerF=0.#POTS_ICP gninnur
4tiB6 1F_KLCICP0WRfonoitressahtiw1F_KLCICPfolortnocwollA eerftoN=1,gninnuReerF=0.#POTS_ICP gninnur
5tiB7 2F_KLCICP0WRfonoitressahtiw2F_KLCICPfolortnocwollA eerftoN=1,gninnuReerF=0.#POTS_ICP gninnur
6tiB93BSU_zHM841WRdelbanE=1delbasiD=0
7tiB83TOD_zHM841WRdelbanE=1delbasiD=0
6
ICS950805
0649G—06/11/02
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
tiB#niPemaNDWPepyTnoitpircseD
0tiBX 0tiBDIrodneV1R)devreseR(
1tiBX 1tiBDIrodneV1R)devreseR(
2tiBX 2tiBDIrodneV1R)devreseR(
3tiBX 3tiBDIrodneV1R)devreseR(
4tiBX 0tiBDInoisiveR1R nodesabeblliwseulavDInoisiveR noisivers'ecivedlaudividni
5tiBX 1tiBDInoisiveR1R
6tiBX 2tiBDInoisiveR1R
7tiBX 3tiBDInoisiveR1R
Byte 5: Programming Edge Rate
(1 = enable, 0 = disable)
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
tiB#niPemaNDWPepyTnoitpircseD
0tiBX BSU_zHM840WRlortncetaregdeBSU
1tiBX BSU_zHM840WRlortncetaregdeBSU
2tiBX TOD_zHM840WRlortnocetaregdeTOD
3tiBX TOD_zHM840WRlortnocetaregdeTOD
4tiBX ]0:2[TUO_zHM660WRT
dp
TUO_zHM66otNI_zHM66 lortnocyalednoitagaporp
5tiBX ]0:2[TUO_zHM660WRT
dp
TUO_zHM66otNI_zHM66 lortnocyalednoitagaporp
6tiBX - 0 - )devreseR(
7tiBX - 0 - )devreseR(
7
ICS950805
0649G—06/11/02
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +85°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
El ectrical Char acterist ics - I nput/ Supply / Comm on Out put Par am eters
TA = 0 - 70C; Sup pl y Vol tage V DD = 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I nput High Vol t age V IH 2V
DD+0.3 V
Input Low Voltage VIL VSS-0.3 0.8 V
I nput High Current I IH VIN = VDD -5 5 mA
IIL1 VIN = 0 V; Inputs with no pull-up res istors -5 mA
IIL2 VIN = 0 V; Inputs with pull-up resistors -200
Opera t i n g S upp l y
Current IDD3.3OP CL = Ful l l oad; S el ec t @ 100 MHz 229 230 360 mA
IDD3.3OP CL = Ful l load; S elect @ 133 MHz 220 233 360 mA
P owerdown Current I DD3.3PD IREF=5 mA 38.1 45 mA
I n pu t Freq uency FiVDD = 3. 3 V 14. 318 M Hz
P in I nduc t anc e L
p
in 7nH
CIN Logic I nput s 5 pF
COUT Out put pin c apac i t anc e 6 pF
CINX X 1 & X 2 pins 27 36 45 pF
Tran si tion ti me1Ttrans To 1s t cros s i ng of t arget frequenc y 3 m s
Settling time1TsF rom 1st crossi ng to 1% target f reque ncy 3 m s
Clk S t abilization1TSTAB From VDD = 3. 3 V t o 1% t arget f requenc y 1 3 m s
Time to first cloc k1T1C Time to first clock 1.8 ms
tPZH,tPZL Output enable delay (all output s ) 1 10 ns
tPHZ,tPLZ Output disable delay (all out put s) 1 10 ns
1Gua rant e ed by desi gn, n ot 10 0% test ed in producti on.
Delay1
I n put Capa c i tance1
Input Low Current
8
ICS950805
0649G—06/11/02
El ect r ical Char act er ist i c s - CPU
TA = 0 - 70C; V DD= 3.3V + /-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Current Source
Out put Im pedanc e Zo1 V O = Vx3000 W
Output Hi gh V ol tage VOH3 IOH = -1 mA 2.4 V
Output Low V ol tage VOL3 IOL = 1 m A 0. 4
Ri se Ti m e t r3 VOL = 0. 41V , V OH = 0.86V 175 240 700 ps
Fall Time t f3 VOH = 0.86V VOL = 0. 41V 175 242 700 ps
Duty Cycle dt3 measurem ent from di fferent i al wavefrom -
0. 35V to + 035V 45 51 55 %
Skew tsk3 VT = 50% 50 100 ps
Jitter, Cycle to cycle tjcyc-cyc1VT = 50% 76 150 ps
1Guarant eed b
y
desi
g
n, not 100% tes ted i n producti on.
2 IOWT c an be v ari ed and i s s el ectable thru t he M ULTS EL pi n.
El ect rical Char act er i st ics - PCI CLK Buf f er ed Mode
TA = 0 - 70C; VDD= 3. 3V +/ -5% ; CL = 10-30 pF (unless otherwise s pecifi ed)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Out put F requenc y FO1 MHz
Out put Im pedanc e RDSP11VO = VDD*(0.5) 12 33 55 W
Ou tp ut High Vo l tage VOH1IOH = -1 mA 2. 4 V
Out put Low V olt age V OL1IOL = 1 mA 0. 55 V
Out put High Current IOH1V OH@MIN = 1.0 V , V OH@MAX = 3. 135 V -33 -33 m A
Out put Low Current IOL1VOL @MIN = 1.95 V, V OL @MAX = 0.4 V 30 38 m A
Ri se T i me tr11VOL = 0.4 V, V OH = 2.4 V 0.5 1. 29 0. 5 to 2 ns
Fall Time t f11VOH = 2. 4 V , V OL = 0.4 V 0.5 1 . 32 0.5 to 2 ns
Duty Cycle dt11V
T
= 1.5 V 45 5 1.9 55 %
Skew tsk11V
T
= 1.5 V 209 500 ps
Jitter,cycle to cyc tjcyc-cyc1VT = 1. 5 V (A dditi ve) 60 100 ps
1Guaranteed by des i gn, not 100% test ed i n produc ti on.
9
ICS950805
0649G—06/11/02
Ele ct ri cal Charact er i st i cs - PCI CLK Un-Buffered M ode
TA = 0 - 70C; VDD= 3. 3V +/ -5%; CL = 10-30 pF (unless otherwise specifi ed)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Out put F requenc y F O1 MHz
Out put Im pedanc e RDSP11VO = VDD*(0.5) 12 33 55 W
Out put High V ol t age V OH1IOH = -1 mA 2.4 V
Out put Low Vol t age V OL1IOL = 1 m A 0. 55 V
Output Hi gh Current IOH1V OH@MIN = 1. 0 V, V OH@MAX = 3. 135 V -33 -33 m A
Output Low Current IOL1VOL @MIN = 1. 95 V , V OL @MAX = 0. 4 V 30 38 mA
Ri se Ti me tr11VOL = 0.4 V, V OH = 2. 4 V 0. 5 1. 32 0. 5to 2 ns
Fall Time t f11VOH = 2.4 V, VOL = 0. 4 V 0. 5 1. 39 0. 5 to 2 ns
Duty Cycle dt11V
T
= 1.5 V 45 52 55 %
Skew tsk11V
T
= 1.5 V 247 500 ps
J
itter,cycle to cyc tjcyc-cyc1VT = 1.5 V 111 500 ps
1Guarant eed by des ign, not 100% t est ed in produc t i on.
El ec t r i cal Char act e r i sti cs- 3V66 - Buf f er ed M ode : 3V66 [1: 0] 66 M Hz_O UT [ 2:0]
TA = 0 - 70C; VDD= 3.3V +/-5%; CL = 10-30 pF (unless ot herwis e spec ifi ed)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Out put Frequenc y FO1 66.66 MHz
Output Im pe dance RDSP11VO = VD
D
*(0.5) 12 33 55 W
Output High Voltage VOH1IOH = -1 mA 2.4 V
Outpu t Lo w V ol tage V OL1IOL = 1 m A 0. 55 V
Output High Current IOH1V OH@MIN = 1.0 V, V OH@MAX = 3. 135 V -33 -33 m A
Out put Low Current IOL1VOL @MI N = 1.95 V, VOL @MAX = 0.4 V 30 38 mA
Ri se T ime tr11VOL = 0.4 V, VOH = 2.4 V 0. 5 1. 44 2 ns
Fall Time t f11VOH = 2.4 V, VOL = 0. 4 V 0. 5 1. 36 2 ns
Duty Cyc le dt11V
T
= 1. 5 V 45 54. 6 55 %
Skew tsk11V
T
= 1.5 V 3V66 [1:0] 105 250 ps
Jitter t
c
c-c
c1V
T
= 1.5 V 3V66 [1:0] (Additive) 20 100 ps
Skew tsk11V
T
= 1.5 V 66MHz_OUT [2:0] 169 250 ps
Jitter tjcyc-cyc1VT = 1.5 V 66MHz_OUT [2:0] 89 300 ps
1Guaranteed by desi gn, not 100% tested i n produc t i on.
10
ICS950805
0649G—06/11/02
El ect r i ca l Char act er ist i cs - 3V6 6 - Un- Buff e r ed M ode: 3V66 [5: 0]
TA = 0 - 70C; VDD= 3. 3V +/ -5% ; CL = 10-30 pF (unless otherwise spec i f i ed)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Out put F requenc y F O1 66.66 MHz
Out put Im pedanc e RDSP11VO = VDD*(0.5) 12 33 55 W
Out put High V ol t age V OH1IOH = -1 mA 2.4 V
Ou t p ut Low Vo l tag e VOL1IOL = 1 mA 0.55 V
Out put High Current IOH1V OH@MIN = 1.0 V, V OH@MAX = 3.135 V -3 3 -33 m A
Out put Low Current IOL1VOL @MI N = 1.95 V, VOL @MAX = 0.4 V 30 38 m A
Ri se T i m e tr11VOL = 0. 4 V, V OH = 2. 4 V 0. 5 1. 38 2 ns
Fall Time t f11VOH = 2.4 V, VOL = 0.4 V 0. 5 1. 45 2 ns
Duty Cycl e dt11V
T
= 1. 5 V 45 54. 4 55 %
Skew tsk11V
T
= 1. 5 V 243 500 ps
Jitter tjcyc-cyc1VT = 1. 5 V 3V 66 139 300 ps
1Guarant eed by design, not 100% test ed i n produc ti on.
Elect r i cal Char act eri st i cs - VCH, 48M Hz DO T, 48M Hz, USB
TA = 0 - 70C; V DD= 3. 3V +/ -5%; CL = 10-20 pF (unless otherwi s e speci fi ed)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Frequency F O1 48 MHz
Output I m pedance RDSP11VO = VDD*(0.5) 20 48 60 W
Output Hi gh V ol tage VOH1IOH = -1 mA 2.4 V
Output Low V oltage V OL1IOL = 1 m A 0. 4 V
Output High Current IOH1V OH@MIN = 1. 0 V , V OH@MAX = 3. 135 V -29 -23 m A
Output Low Current IOL1VOL @MIN = 1. 95 V , VOL @MAX = 0. 4 V 29 27 m A
48DOT Ri s e T i m e tr11VOL = 0.4 V, V OH = 2.4 V 0. 5 0. 6 1 ns
48DOT Fall Time tf11VOH = 2.4 V , V OL = 0. 4 V 0.5 0.8 1 ns
VCH 48 USB R i se T i m e tr11VOL = 0.4 V, V OH = 2.4 V 1 1.2 2 ns
V CH 48 USB Fall Time tf11VOH = 2.4 V , VOL = 0. 4 V 1 1. 3 2 ns
48 DO T Duty Cycl e dt11V
T
= 1.5 V 45 52. 8 55 %
V C H 48 USB Du ty Cycl e dt11V
T
= 1.5 V 45 53. 5 55 %
48 DOT Ji t ter t
j
c
y
c-c
y
c1V
T
= 1.5 V 183 350 ps
VCH Jitter tjcyc-cyc1VT = 1. 5 V 223 350 ps
1Guarant eed by desi
g
n, not 100% test ed i n produc ti on.
11
ICS950805
0649G—06/11/02
El ect r i cal Char act er ist i cs - REF
TA = 0 - 70C; VDD= 3. 3V +/-5% ; CL = 10 -20 p F (unl e ss o the rwi se sp eci fie d)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Out put F requenc y FO1 MHz
Out put I mpedanc e RDSP11VO = VDD*(0.5) 20 48 60 W
Out put High V ol t age VOH1IOH = -1 mA 2.4 V
Out put Low V oltage V OL1IOL = 1 m A 0. 4 V
Ou t p ut High Curren t IOH1V OH@MIN = 1.0 V, V OH@MAX = 3.13 5 V -29 -23 m A
Ou t put Low Current IOL1VOL @MI N = 1.95 V, VOL @MAX = 0.4 V 29 27 mA
Ri se Time tr11VOL = 0.4 V, V OH = 2. 4 V 1 1. 25 2 ns
Fall Time t f11VOH = 2.4 V, VOL = 0. 4 V 1 1.15 2 ns
Duty Cy cle dt11V
T
= 1.5 V 45 53 55 %
Jitter tjcyc-cyc1VT = 1. 5 V 723 1000 ps
1Guarant eed by desi gn, not 100% tes ted i n produc ti on.
12
ICS950805
0649G—06/11/02
1 . The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3. The input is operating at 3.3V logic levels.
4. The data byte format is 8 bit bytes.
5 . To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
6. At power-on, all registers are set to a default condition, as shown.
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D2 (H)
• ICS clock will acknowledge
• Controller (host) sends a dummy command code
• ICS clock will acknowledge
• Controller (host) sends a dummy byte count
• ICS clock will acknowledge
• Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time .
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the read address D3 (H)
• ICS clock will acknowledge
• ICS clock will send the byte count
• Controller (host) acknowledges
• ICS clock sends first byte (Byte 0) through byte 6
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a stop bit
Notes:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D2(H)
A
CK
Du mmy Command Code
A
CK
Dummy Byte Count
A
CK
By te 0 ACK
By te 1
A
CK
By te 2
A
CK
By te 3 ACK
By te 4
A
CK
By te 5
A
CK
By te 6 ACK
Stop Bit
How to Write:
Controller (Host) ICS (Slave/Receiver)
Start Bit
Address
D3(H)
A
CK
Byte Count
ACK Byte 0
ACK Byte 1
ACK Byte 2
ACK Byte 3
ACK Byte 4
ACK Byte 5
ACK Byte 6
ACK
Stop Bit
How to Read:
13
ICS950805
0649G—06/11/02
All 3V66 clocks are to be in phase with each other. All 66MHz_OUT clocks are to be in phase with each other. There
is NO phase relationship between the 3V66 clocks and the 66MHz_OUT and PCI clocks. In the case where 3V66_1
is configured as 48MHz VCH cloc k, there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks .
The PCI group should lag 3V66 by the standard skew described below as Tpci.
The 66MHz_IN to 66MHz_OUT delay is shown in the figure below and is specified to be within a min and max
propagation value.
66MHz_IN
66MHz_OUT
PCICLK_F
3V66
Tpd
Tpci
No Relationship
Buffered Mode - 3V66[0:1], 66MHz_IN, 66MHz_OUT[0:2] and PCI Phase Relationship
G roup Skew s at Com mon Tra nsi t i on Edges: ( Buf f er ed Mode)
GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS
3V 66 3V 66 3V 66 (1:0) pi n t o pin skew 0 500 ps
66MHz_O UT 66OUT 66M Hz_OUT (2: 0) pi n to pin skew 0 175 ps
P CI P CI P CI _F (2:0) and PCI (6: 0) pi n to pin skew 0 500 ps
66MHz_IN
66MHz_OUT Tpd Propogat i on delay f rom 66M Hz _I N t o
66MHz_OUT (2: 0) 2.5 4.5 nS
66MHz _O UT t o P CI Tpci 66M Hz _OUT (2: 0) leads 33 MHz P CI 1. 5 3.5 nS
66MHz _O UT1 t o all
CLK Ts1 30 150 400 mS
14
ICS950805
0649G—06/11/02
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock,
there is no defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66
by the standard skew described below as Tpci.
Un-Buffered Mode 3V66 & PCI Phase Relationship
3V66 (1:0)
3V66 (4:2)
3V66_5
PCICLK_F (2:0) PCICLK (6:0) Tpci
G r oup Sk ew s at Com m on Tr ansition Edge s: (Un- Buf f er e d M ode)
GROUP SYMBOL CONDITIONS MIN TYP MAX UNITS
3V66 3V 66 3 V 6 6 (5:0) pin to pi n skew 0 500 ps
PCI PCI PCI_F (2:0) and PCI (6:0) pin to pin skew 0 500 ps
3V66 to P CI S3V66-PCI 3V 66 (5: 0) leads 33MHz PCI 1.5 3. 5 ns
1Guarenteed by desi gn, not 10 0% t e s ted i n product i o n.
15
ICS950805
0649G—06/11/02
Normal operation transition to Suspend State S1 Entry sequence of events:
1. Power-Down (PD#) pin is taken from a high to low to start into S1 Suspend state with digital filtering of the
transition in the clock circuit.
2. The first clocks to be forced to a Stop Low power down condition are the PCI buffer output clocks after a full
clock cycle. If the PCI_Stop# is low, then the free-running PCI clocks (for PCI and APIC signals) are the
remaining PCI buffer clocks stopped.
3. Immediately after the PCI clocks have been stopped the 66Buf_0:2 clocks are stopped low after the next
high to low transition. It will always be a sequence of PCI stopping, THEN the 66Buf clocks.
4. Following the two buffer output clocks being stopped (PCI then 66.6Buffer outputs), the remaining clocks
within a short delay will transition to a stopped power-down state. The first of these driven clocks that
transition to a stopped state are all of the CPU PLL clocks: the CPU and the driven 3V66 clocks.
5. After the CPU PLL clocks are stopped, the 48 MHz clocks (USB, DOT clocks) will stop low, then the REF
clock 14.318 MHz clock will stop low.
6. After the clocks have all been stopped, the internal PLL stages and the Crystal oscillator will all be driven to
a low power stopped condition.
7. As a note to power management calculations, please be aware that the CPU design requires that in the
Power-Down (S1 mode) the CPU outputs have a differential bias voltage driving the differential input stage of
the CPU in this S1 state. For this PD condition of the clock generator, the IDD_PD is running around 30 to
45 mA from having the Iref running (5 mA), the output multiplier bias generator at a 2X condition and the
output current source outputs are running at a 2xIref bias level (for approx 10 mA each CPU output). This
results in a higher level of Clock generator IDD_PD than in prior generations of clocks due to the CPU output
differential requirements.
Suspend State S1 Exit transition to normal operation sequence of events:
1. Power-Down (PD#) pin is taken from Low to High with digital filtering of the transition in the clock circuit to
return to normal running operation.
2. The Crystal Oscillator and the two PLL stages are released from PD to start-up to normal operation. No
clocks will operate until the Lock detect circuitry verifies the PLL has reached stable final frequency (the
same as normal initial power-up).
3. The CPU PLL clocks (differential CPU outputs and the driven 3V66_(0:1) clocks are operating first as soon
as the Lock detect releases the clocks. With the release of these clocks, the single 66Buf_1 buffer driven
output (at pin 22) is also released from the PD stopped state (but NOT the other 66Buf0,2 and not the PCI
outputs). This allows the GMCH chipset 66.6 MHz DLL stage to start operating and have an operating
feedback path before the other buffer outputs are released. This change is why the requirement is made that
pin 22 be the connection from the clock to the GMCH chipset. Note that along with the 66Buf_0,2 and the
PCI clocks, the 48 MHz and REF (14.318 MHz) clocks are also NOT released at this point.
4. A delay is built into the clock generator that allows the CPU, driven 3V66_0,1 and the single buffer clock
66Buf_1 (at pin 22) to operate before other clocks are released. This delay is larger than 30 uS and shor ter
than 400 uS, and after this the other clocks are staged for a sequential release.
5. The initial clocks released after the delay are the 66Buf_0, 2 outputs.
6. After the 66Buf_0,2 clocks are released, then the PCI clocks are released.
7. It will always be the sequence of 66_1 (pin 22) released with the CPU clocks, then after the delay the
remaining 66Buf_0,2 first, THEN the PCI clocks.
8. Following the 66Buf_0,2 clocks, the 48 MHz (DOT and USB clocks) and the REF (14.318MHz) clocks are
released.
9. Note, the initial power-up time is the same as this PD release, the PLL will power-up and the outputs will be
running within a 3 ms time point.
16
ICS950805
0649G—06/11/02
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
CPU_STOP#
CPUT
CPUC
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
CPU_STOP# Functionality
#POTS_UPCTUPCCUPC
1lamroNlamroN
0tluM*feritaolF
PCI_STOP#
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
tsu
The impact of asser ting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will
latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized
by the next rising edge.
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable
via asser tion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling
as shown. The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the
output drive current v alues. The CPUT will be driven high with a current v alue equal to (MULTSEL0) X (I REF), the CPUC
signal will not be driven.
17
ICS950805
0649G—06/11/02
When PD# is sampled low by two consecutive rising edges of CPU clock then all clock outputs except CPU clocks
must be held low on their next high to low transition. CPU clocks must be held with the CPU clock pin driven high with
a value of 2x Iref, and CPUC undriven. Note the example below shows CPU = 100MHz, this diagram and description
is applicable for all valid CPU frequencies 66, 100, 133, 200MHz.
Due to the state of the internal logic, stopping and holding the REF clock outputs in the LOW state may require more
than one clock cycle to complete.
PD# - Assertion (transition from logic "1" to logic "0")
PD# Functionality
#POTS_UPCTUPCCUPC66V3TUO_zHM66 F_KLCICP KLCICP KLCICP TOD/BSU zHM84
1lamroNlamroNzHM66NI_zHM66NI_zHM66NI_zHM66zHM84
0tluM*feritaolFwoLwoLwoLwoLwoL
Power Down Assertion of Waveforms - Buffered Mode
0ns
PD#
CPUT 100MHz
CPUC 100MHz
3V66MHz
66MHz_IN
66MHz_OUT
PCI 33MHz
USB 48MHz
REF 14.318MHz
25ns 50ns
18
ICS950805
0649G—06/11/02
Ordering Information
ICS950805yF-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Packag e Type
F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y F - PPP - T
300 mil SSOP Package
INDEX
AREA
INDEX
AREA
12
1 2
N
D
h x 45°
h x 45°
E1 E
α
SEATING
PLANE
SEATING
PLANE
A1
A
e
-C-
- C -
b
.10 (.004) C
.10 (.004) C
c
L
MIN MAX MIN MAX
A 2.41 2.80 .095 .110
A1 0.20 0.40 .008 .016
b 0.20 0.34 .008 .0135
c 0.13 0.25 .005 .010
D
E 10.03 10.68 .395 .420
E1 7.40 7.60 .291 .299
e
h 0.38 0.64 .015 .025
L 0.50 1.02 .020 .040
N
α
0° 8° 0° 8°
MIN MAX MIN MAX
56 18.31 18.55 .720 .730
10-0034
Reference Doc.: JEDEC Publication 95, MO-118
VARIATIONS
SEE VARIATIONS SEE VARIATIONS
ND mm. D (inch)
SEE VARIATIONS SEE VARIATIONS
0.635 BASIC 0.025 BASIC
SYMBOL In Millimeters In Inches
COMMON DIMENSIONS COMMON DIMENS IONS
19
ICS950805
0649G—06/11/02
Ordering Information
ICS950805yG-T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code
patterns)
Packag e Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX y G - PPP - T
INDEX
AREA
INDEX
AREA
12
1 2
N
D
E1 E
SEATING
PLANE
SEATING
PLANE
A1
A
A2
e
-C-
- C -
b
c
L
aaa
C
6.10 mm. Body, 0.50 mm. pitch TSSOP
(240 mil) (0.020 mil)
MIN MAX MIN MAX
A -- 1.20 -- .047
A1 0.05 0.15 .002 .006
A2 0.80 1.05 .032 .041
b 0.17 0.27 .007 .011
c 0.09 0.20 .0035 .008
D
E
E1 6.00 6.20 .236 .244
e
L 0.45 0.75 .018 .030
N
α
0° 8° 0° 8°
aaa -- 0.10 -- .004
V
ARIATIONS
MIN MAX MIN MAX
56 13.90 14.10 .547 .555
10-0039
SYMBOL In Millimeters In Inches
COMMON DIM EN SIONS COMMON DIMENSIONS
SEE VARIATION S SE E VARIATI ONS
8.10 BASIC 0.319 BASIC
0.50 BASIC 0.020 BASIC
SEE VARIATION S SE E VARIATI ONS
ND mm . D (inch)
Reference Doc.: JEDEC Publication 95, MO-153