PE4251MLI - Peregrine Semiconductor Corp.

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RF1 RF2

V1

50Ω50ΩCMOS

Control

Driver

ESD ESD

V2

RFC

ESD

The PE4251 is a HaRP™-enhanced Absorptive SPDT (single

po le doub le throw) RF Switch for use in ge ne ral switchin g

applications and mobile infrastructure. This device offers a

flexible supply voltage of 3.3/5V, single-pin or complementary

pin control in put s , an d 4k V ESD tol erance. It pres ents a simpl e

alternative solution to pin diode and mechanical relay switches.

Peregrine’s HaRP™ technology enhancements deliver high

linearity and exceptional performance. It is an innovative

feature of the UltraCMOS™ process, providing performance

superior to GaAs with the economy and integration of

conventional CMOS.

Pro duct Specificat ion

SPDT UltraCMOS™ RF Switch

10 – 3000 MHz, Absorptive

Product Description

Figure 1. Functional Diagram

PE4251

Features

• HaRP-Technology Enhanced

• Low Insertion Loss: 0.60 dB @ 1000 MHz

• High Isolation: 62 dB @ 1000 MHz

• P1dB typical: +30.5 dBm

• IIP3 typical: +59 dBm

• Fast switching time: 150 ns

• Flexible supply voltage: 3.3 V ±10% or 5.0

V ±10% supply (see table 3)

• Excellent ESD protection: 4000 V HBM

• No blocking capacitors required

• Single pin or complementary control inputs

Fig ur e 2. Pac kage Typ e

8-lead MSOP with exposed paddle

Table 1. Target Electrical Specifications Temp = 25°C, VDD = 3.3 or 5.0 V

Notes: 1. Device linearity will begin to degrade below 10 MHz.

2. Note Absolute Maximum rating of PIN = 27 dBm.

Parameter Conditions Min Typical Max Units

Operation Frequency1 10 3000 MHz

Insertion Loss (RF1/RF2)

10 MHz 0.5 5 0.6 0 dB

1000 MH z 0.6 0 0.7 0 dB

2000 MH z 0.7 5 0.8 5 dB

3000 MH z 0.7 5 0.9 0 dB

Isolation (RFC to RF1/RF2) 1000 MH z 61 62 dB

2000 MH z 51 53 dB

3000 MH z 42 43 dB

Return Loss 1000 MH z 26 dB

2000 MH z 23 dB

3000 MH z 22 dB

Input 1 dB Co mpr ess io n2 50 - 3000 MHz 30.5 dBm

Input IP3 50 - 3000 MHz, +18 dBm per tone, 5 MHz spacing 59 dBm

Switching Time 50% CTRL to 10/90% RF 150 300 ns

Product Specification

PE4251

Page 2 of 9

Table 2 . Pin Descriptions

Electrostatic Discharge (ESD) Precautions

When hand ling this UltraCMOS ™ devi ce, obs erve

the same precautions that you would use with

other ESD-sensitive devices. Although this device

contains circuitry to protect it from damage due to

ESD, precautions should be taken to avoid

exceeding the specified rating.

Latc h-Up Avoidance

Unlike conventional CMO S device s, UltraCMOS™

devices are immune to latch-up.

Table 3. Operating Ranges

Note 3. All RF pins must be DC blocked with an external

series capacitor or held at 0 VDC.

Figure 3. Pin Configuration (Top View)

Pin No. Pin Name Description

1 V2

This pin su pp or ts tw o int er f ac e op t i ons :

Single-pin control mode. A no mi na l 3-

volt supply connection is required.

Complementary-pin control mode. A

compl ementary CMOS control signal

to V1 is supplied to this pin.

2 V1 Sw it c h control input, C MOS logic le ve l.

3 RFC RF Common port.3

4 N/C or GND No Connect or Ground

5 RF1 RF1 port.3

6 GND

Ground Connection. Traces should be

physically short and connected to

gro un d pl ane for bes t per f or m anc e.

7 GND

Ground Connection. Traces should be

physically short and connected to

gro un d pl ane for bes t per f or m anc e.

8 RF2 RF2 port.3

Paddle GND Expo s ed ground paddle. Ground for

proper device operation

Exceeding absolute maximum ratings may cause

permanent damage. Operation should be

restricted to the limits in the Operating Ranges

tabl e. Oper ation be tw e en op er a ti ng ran ge

maxi mum and absolut e maximu m fo r ex tended

periods may redu ce reliability.

Swi tc hing Frequency

The PE4251 has a maximum 25 kHz switching rate.

4251

1

2

3

4

8

7

6

5

V2

V1

RFC

N/C or

GND

RF2

GND

RF1

Exposed ground paddle

Note 4. Cu stomer must ch oose either 3.3 V or 5.0 V power

supply range

Table 4. Absolute Maximum Ratings

Symbol Parameter/Conditions Min Max Units

VDD Power supply voltage 3 5.5 V

VI Voltage on any control input -0.3 5.5 V

TST Storage temperature range -65 150 °C

PIN RF Input power (50Ω) 27 dBm

VESD ESD voltag e (HBM)5

ESD voltag e (Mac hine M odel ) 4000

250 V

Note: 5 . Human Body Model ( HB M , MI L_STD 883 Method 3 015. 7)

Parameter Min Typ Max Units

VDD Power Supp ly Voltage4 3.0

4.5 3.3

5.0 3.6

5.5 V

V

IDD Power S upp ly Current

VDD = VCNTL= 3.3V

VDD = VCNTL= 5.0V

55

75

60

80

µA

Control Voltage High 0.8 x VDD V

Control Voltage Low 0.2 x VDD V

PIN RF Input Power (50Ω) 27 dBm

TOP Operating temperature

range -40 25 85 °C

TST Storage temperature range -65 25 150 °C

Moist u re Sen sit i vit y L evel

The Moisture Sensitivity Level rating for the PE4251

in the 8-lead MSOP package is MSL1.

Product Specification

PE4251

Page 3 of 9

Control Logic Input

The PE4251 is a versatile RF CMOS switch that

supports two operating control modes; single-pin

control mode and complementary-pin control

mode.

Single- pin c o ntr ol m od e enables the switch to

operate with a single control pin (pin 2) supporting

a +3.3 or 5.0-volt CMOS logic input, and requires

a dedicated +3.3 or 5.0-volt power supply

connection (pin 1). This mode of operation

reduces the number of control lines required and

simplifies the switch contro l interface typ ically

derived from a CMOS µProcessor I/O port.

Complementary-pin control mode allo ws the

switch to operate using complementary control

pins V1 and V2 (pi ns 2 & 1), that ca n be di r ectl y

driven by +3.3 or 5.0-volt CMOS logic or a suitable

µProcessor I/O port. This enables the PE4251 to

operate in positive control voltage mode within the

PE4251 op er ating lim it s.

Control Voltages Signal Pat h

Pin 1 (V2) = VDD

Pin 2 (V1) = High RFC to RF1

Pin 1 (V2) = VDD

Pin 2 (V1) = Low RFC to RF2

Table 5. Single-pin Control Logic Truth Table

Table 6. Complementary-pin Control Logic

Truth Table

Control Voltages Signal Pat h

Pin 1 (V2 ) = Low

Pin 2 (V1) = High RFC to RF1

Pin 1 (V2) = High

Pin 2 (V1) = Low RFC to RF2

Product Specification

PE4251

Page 4 of 9

Evaluation Kit Figure 4. Evaluation Board Layouts

Figure 5. Evaluation Board Sc hematic

Peregr ine s pec ificat ion 102/0408

Peregr ine s pec ificat ion 101/0337

NOTES:

4.3 Er AND 2.1MIL Cu

THICKNESS.

3. ALL TRANSMISION LINES ARE:

33MIL WIDTH, 10MIL GAPS, 28MIL CORE DIELECTRIC

TO DAMAGE BY ELECTROSTATIC DISCHARGE (ESD)

2. CAUTION:

1. USE 101-0337-02 PCB.

CONTAINS PARTS AND ASSEMBLIES SUSCEPTIBLE

or GND

R1

DNI

C2

100pF

1

2

J3

SMASM

1

2

J4

SMASM

1

2

J5

SMASM

1

2

J2

SMASM

C1

100pF

1

2

J6

SMASM

2V1

1V2

3RFC 6

GNDS1

7

GNDS2

8

RF2

4N/C 5

RF1

U1

MSOP

1

13

35

57

7

22

44

66

88

10 10 9

9

J1

HEADER 2 X 5 PIN

R2

0 OHM

R3

0 OHM

The SPDT Switch Evaluation Kit board was

designed to ease customer evaluation of the

PE4250 SPDT switch. The RF common port is

connected through a 50 Ω transmission line to the

bottom SMA connector, J3. Port 1 and Port 2 are

connected through 50 Ω transmission lines to two

SMA connectors on either side of the board, J4 and

J2. A through transmission line connects SMA

connectors J5 and J6. This transmission line can be

used to estimate the loss of the PCB over the

environmental conditions being evaluated.

The board is constructed of a two metal layer FR4

material with a total thickness of 0.0322”. The

bottom layer provides ground for the RF

transmission lines. The transmission lines were

designed using a coplanar waveguide with ground

plane model using a trace width of 0.033”, trace

gaps of 0.010”, dielectric thickness of 0.028”, copper

thickness of 0.0021” and εr of 4.3.

J1 provides a means for controlling the DC inputs to

the device. The second-to-bottom lower right pin

(J1-3) is connected to the device V1 input. The

second-to-top upper right pin (J1-7) is connected to

the device V 2 input. Footprints for decoupling

capacitors are provided on both V1 and V2 traces. It

is the responsibility of the custo mer to determine

proper supply decoupling for their design application.

Removing these components from the evaluation

board has not been shown to degrade RF

performance.

Product Specification

PE4251

Page 5 of 9

Figure 9. Isolation: RFC-RF @ 3.3 V Figure 8. Isolation: RFC-RF @ 25 °C

Figure 6. Insertion Loss: RFC-RF @ 25 °C Figure 7. Insertion Loss: RFC-RF @ 3.3 V

Product Specification

PE4251

Page 6 of 9

Figure 10. Return Loss at ac ti ve port @ 25 °C Figure 11. Return Loss at active port @ 3.3 V

Product Specification

PE4251

Page 7 of 9

Figure 12. Package Drawing

4) THE PE4251 USES SEATING PLANE OPTION 2

8-lead MSOP with exposed paddle: 19-0134-01

Product Specification

PE4251

Page 8 of 9

8-lead MSOP with exposed paddle

Table 7. Ordering Information

Figure 14. Tape and Reel Specifications

Pin1

Or der Code Part Marking Description Package Shipping Met hod

EK4251-01 PE4251-EK PE4251-08MSOP-EK Evaluation Kit 1 / Box

PE4251MLI 4251 PE4251G-08MSOP-Cut tape or loose Green 8-lead MSOP, exposed paddle Cut tape or loose

PE4251MLI-Z 4251 PE4251G-08MSOP-2000C Green 8-lead MSOP, exposed paddle 2000 units / T&R

Figure 13. Top Marking S pecification

4251

LLLL

YWW

AAAA: Product Number, last 4 digits, Exp.

LLLL: Last four digits of the Assembly lot number

YWW: Date Code, last digit of the year and work week

Product Specification

PE4251

Page 9 of 9

Sales Offices

The Americas

Peregrine Semiconductor Corporation

9380 Carr oll Park Drive

San Diego, CA 92121

Tel: 858-731-9400

Fax: 858-731-9499

Europe

Peregrine Semiconductor Europe

Bâtiment Maine

13-15 rue des Quatre Vents

F-92380 Garches , France

Tel: +33-1-4741-9173

Fax : +33-1 -4741 -917 3

For a list of representatives in your area, please refer to our Web site at: www.psemi.com

Data Sheet Identification

Advance Information

The product is in a formative or design stage. The data

sheet contains design target specificat ions for product

development. Specifications and features may change in

any manner without notice.

Preliminary Specification

The data sheet contains preliminary data. Additional data

may be added at a later date. Peregrine reserves the right

to change specifications at any time without notice in order

to supply the best possible product.

Product Specification

The data sheet contains final data . In the event Peregrine

dec ide s to cha nge the spe c ific a tions, Pereg rine will not ify

customer s of the intended changes by issuing a CNF

(Customer Notification Form).

The information in this dat a sheet is believed to be reliable.

Howeve r, Peregrine assum es no liability f or th e use of this

information. Use shall be entirely at the user’s own risk.

No patent rights or licenses to any circuits described in this

data sheet are implied or granted to any third part y.

Peregrine’s products are not designed or intended for use in

devices or systems intended for surgical implant, or in other

applications intended to support or sustain life, or in any

application in which the failure of the Peregrine product could

create a situation in which personal injury or death might occur.

Peregr ine assumes no liability for damages, including

consequential or incidental damages, ar ising out of the use of

its products in such applications.

The Peregr ine name, logo, and UTSi ar e regist er ed tr ademarks

and UltraCMOS, HaRP, MultiSwitch and DuNE are trademarks

of Peregrine Semiconductor Corp.

High-Reliability and Defense Products

Americas

San Diego, CA, USA

Phone: 858-731-9475

Fax: 848-731-9499

Europe/Asia-Pacific

Aix-En-Provence Cedex 3, France

Phone: +33-4-4239-3361

Fax: +33-4- 4239-7227

Peregri ne Semiconduc tor, Asia Pacific (AP AC)

Shanghai, 200040, P.R. China

Tel: +86-21-5836-8276

Fax: +86-21-5836-7652

Peregrine Semiconductor, Korea

#B-2607, Kolon Tr ipolis, 210

Geumgok-dong, Bundang-gu, Seongnam-si

Gyeonggi-do, 463-943 South Korea

Tel: +82-31-728-3939

Fax: +82-31-728-3940

Peregrine Semiconductor K.K., Japan

Teiko k u Hote l Tower 10B-6

1- 1-1 Uchisa iwa i-ch o, Ch iy o da-k u

Tokyo 100-0011 Japan

Tel: +81-3-3502-5211

Fax: +81-3- 3502-5213