JANSR2N7438 Data Sheet Title ANS N74 bt orrly aile L91 0R4 adion rded, GR sist, Chanwer OSTs) utho eyrds terrpoon, minctor, rrly ail- Formerly Available As FSL913A0R4, Radiation Hardened, SEGR Resistant, P-Channel Power MOSFETs The Discrete Products Operation of Intersil has developed a series of Radiation Hardened MOSFETs specifically designed for commercial and military space applications. Enhanced Power MOSFET immunity to Single Event Effects (SEE), Single Event Gate Rupture (SEGR) in particular, is combined with 100K RADS of total dose hardness to provide devices which are ideally suited to harsh space environments. The dose rate and neutron tolerance necessary for military applications have not been sacrificed. The Intersil portfolio of SEGR resistant radiation hardened MOSFETs includes N-Channel and P-Channel devices in a variety of voltage, current and on-resistance ratings. Numerous packaging options are also available. This MOSFET is an enhancement-mode silicon-gate power field-effect transistor of the vertical DMOS (VDMOS) structure. It is specially designed and processed to be radiation tolerant. The MOSFET is well suited for applications exposed to radiation environments such as switching regulation, switching converters, motor drives, relay drivers and drivers for high-power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from integrated circuits. Also available at other radiation and screening levels. See us on the web, Intersil' home page: http://www.semi.intersil.com. Contact your local Intersil Sales Office for additional information. JANSR2N7438 PACKAGE TO-205AF File Number 4638 Features * 7A, -100V, rDS(ON) = 0.300 * Total Dose - Meets Pre-RAD Specifications to 100K RAD (Si) * Single Event - Safe Operating Area Curve for Single Event Effects - SEE Immunity for LET of 36MeV/mg/cm2 with VDS up to 80% of Rated Breakdown and VGS of 10V Off-Bias * Dose Rate - Typically Survives 3E9 RAD (Si)/s at 80% BVDSS - Typically Survives 2E12 if Current Limited to IDM * Photo Current - 1.5nA Per-RAD(Si)/s Typically * Neutron - Maintain Pre-RAD Specifications for 3E13 Neutrons/cm2 - Usable to 3E14 Neutrons/cm2 Symbol D G S Packaging TO-205AF Ordering Information PART NUMBER January 1999 BRAND JANSR2N7438 Die Family TA17796. MIL-PRF-19500/658. D (c)2001 Fairchild Semiconductor Corporation G S JANSR2N7438 Rev. A JANSR2N7438 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified JANSR2N7438 -100 -100 UNITS V V 7 4 A A 21 20 A V 25 10 W W Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulsed Avalanche Current, L = 100H, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . .IAS Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IS Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG 0.20 21 7 21 -55 to 150 W/oC A A A oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL (Distance >0.063in (1.6mm) from Case, 10s Max) Weight (Typical) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 oC 1.0 g Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current TC = 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID TC = 100oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Maximum Power Dissipation TC = 25oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT TC = 100oC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PT CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications TC = 25oC, Unless Otherwise Specified PARAMETER Drain to Source Breakdown Voltage Gate Threshold Voltage Zero Gate Voltage Drain Current SYMBOL BVDSS VGS(TH) IDSS Gate to Source Leakage Current IGSS Drain to Source On-State Voltage VDS(ON) Drain to Source On Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge (Not on slash sheet) rDS(ON)12 td(ON) tr TEST CONDITIONS ID = 1mA, VGS = 0V VGS = VDS, ID = 1mA VDS = -80V, VGS = 0V VGS = 20V TC = -55oC TC = 25oC TC = 125oC TC = 25oC TC = 125oC TC = 25oC TC = 125oC TYP MAX UNITS -100 - - V - - -7.0 V -2.0 - -6.0 V -1.0 - - V - - 25 A - - 250 A - - 100 nA - - 200 nA - - -2.31 V TC = 25oC - 0.230 0.300 TC = 125oC - - 0.492 - - 30 ns VGS = -12V, ID = 7A ID = 4A, VGS = -12V MIN VDD = -50V, ID = 7A, RL = 7.14, VGS = -12V, RGS = 7.5 - - 50 ns td(OFF) - - 50 ns tf - - 50 ns - - 60 nC - 36 40 nC Qg(TOT) VGS = 0V to -20V Gate Charge at 12V Qg(12) VGS = 0V to -12V Threshold Gate Charge (Not on slash sheet) Qg(TH) VGS = 0V to -2V VDD = -50V, ID = 7A - - 2.3 nC Gate Charge Source Qgs - 6.3 7.3 nC Gate Charge Drain Qgd - 16 19 nC Thermal Resistance Junction to Case RJC - - 5 oC/W Thermal Resistance Junction to Ambient RJA - - 175 oC/W (c)2001 Fairchild Semiconductor Corporation JANSR2N7438 Rev. A JANSR2N7438 Source to Drain Diode Specifications PARAMETER SYMBOL Forward Voltage VSD Reverse Recovery Time TEST CONDITIONS ISD = 7A MIN TYP MAX -0.6 - -1.8 V - - 160 ns ISD = 7A,dISD/dt = 100A/s trr Electrical Specifications up to 100K RAD UNITS TC = 25oC, Unless Otherwise Specified MIN MAX UNITS Drain to Source Breakdown Volts PARAMETER (Note 3) SYMBOL BVDSS VGS = 0, ID = 1mA TEST CONDITIONS -100 - V Gate to Source Threshold Volts (Note 3) VGS(TH) VGS = VDS, ID = 1mA -2.0 -6.0 V Gate to Body Leakage (Notes 2, 3) IGSS VGS = 20V, VDS = 0V - 100 nA Zero Gate Leakage (Note 3) IDSS VGS = 0, VDS = -80V - 25 A Drain to Source On-State Volts (Notes 1, 3) VDS(ON) VGS = -12V, ID = 7A - -2.31 V Drain to Source On Resistance (Notes 1, 3) rDS(ON)12 VGS = -12V, ID = 4A - 0.300 NOTES: 1. Pulse test, 300s Max. 2. Absolute value. 3. Insitu Gamma bias must be sampled for both VGS = -12V, VDS = 0V and VGS = 0V, VDS = 80% BVDSS . Single Event Effects (SEB, SEGR) Note 4 ENVIRONMENT (NOTE 5) TYPICAL LET (MeV/mg/cm) TYPICAL RANGE () APPLIED VGS BIAS (V) (NOTE 6) MAXIMUM VDS BIAS (V) TEST SYMBOL ION SPECIES Single Event Effects Safe Operating Area SEESOA Ni 26 43 20 -100 Br 37 36 10 -100 Br 37 36 15 -80 Br 37 36 20 -50 NOTES: 4. Testing conducted at Brookhaven National Labs; sponsored by Naval Surface Warfare Center (NSWC), Crane, IN. 5. Fluence = 1E5 ions/cm2 (typical), TC = 25oC. 6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR). Typical Performance Curves Unless Otherwise Specified LET = 26MeV/mg/cm2, RANGE = 43 LET = 37MeV/mg/cm2, RANGE = 36 -120 1E-3 LIMITING INDUCTANCE (HENRY) FLUENCE = 1E5 IONS/cm2 (TYPICAL) -100 VDS (V) -80 -60 -40 -20 1E-4 ILM = 10A 30A 1E-5 100A 300A 1E-6 TEMP = 25oC 0 0 5 10 15 20 25 VGS (V) FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA (c)2001 Fairchild Semiconductor Corporation 1E-7 -10 -30 -100 -300 -1000 DRAIN SUPPLY (V) FIGURE 2. DRAIN INDUCTANCE REQUIRED TO LIMIT GAMMA DOT CURRENT TO IAS JANSR2N7438 Rev. A JANSR2N7438 Typical Performance Curves Unless Otherwise Specified (Continued) 50 10 TC = 25oC 9 ID , DRAIN CURRENT (A) 8 ID , DRAIN (A) 7 6 5 4 3 2 1ms 0 50 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 0.1 -1 150 100 TC , CASE TEMPERATURE (oC) FIGURE 3. MAXIMUM CONTINUOUS DRAIN CURRENT vs TEMPERATURE NORMALIZED rDS(ON) QG QGD QGS 100ms -300 -10 -100 VDS , DRAIN-TO-SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA 2.5 -12V 10ms 1 1 0 -50 100s 10 PULSE DURATION = 250ms, VGS = -12V, ID = 4A 2.0 1.5 1.0 0.5 VG 0.0 -80 -40 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (oC) CHARGE FIGURE 5. BASIC GATE CHARGE WAVEFORM FIGURE 6. NORMALIZED rDS(ON) vs JUNCTION TEMPERATURE THERMAL RESPONSE (ZJC) 10 1 0.5 0.2 0.1 0.1 0.05 0.02 0.01 0.01 PDM SINGLE PULSE 0.001 10-5 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC + TC 10-4 10-3 10-2 t1 t2 10-1 100 101 t, RECTANGULAR PULSE DURATION (s) FIGURE 7. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE (c)2001 Fairchild Semiconductor Corporation JANSR2N7438 Rev. A JANSR2N7438 Typical Performance Curves Unless Otherwise Specified (Continued) IAS , AVALANCHE CURRENT (A) 40 STARTING TJ = 25oC 10 STARTING TJ = 150oC IF R = 0 tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD) IF R 0 tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1] 1 0.01 0.1 1 tAV , TIME IN AVALANCHE (ms) 10 FIGURE 8. UNCLAMPED INDUCTIVE SWITCHING Test Circuits and Waveforms ELECTRONIC SWITCH OPENS WHEN IAS IS REACHED VDS L BVDSS + CURRENT I TRANSFORMER AS tP - VARY tP TO OBTAIN REQUIRED PEAK IAS 0V VDS IAS VDD + 50 - tP VDD 50V-150V DUT 50 VGS 20V tAV FIGURE 9. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 10. UNCLAMPED ENERGY WAVEFORMS tON VDD tOFF td(ON) td(OFF) tr RL VDS tf 90% 90% VDS 0V 10% DUT VGS = -12V 10% 90% RGS 50% VGS 50% PULSE WIDTH 10% FIGURE 11. RESISTIVE SWITCHING TEST CIRCUIT (c)2001 Fairchild Semiconductor Corporation FIGURE 12. RESISTIVE SWITCHING WAVEFORMS JANSR2N7438 Rev. A JANSR2N7438 Screening Information Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table). Delta Tests and Limits (JANS) TC = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MAX UNITS Gate to Source Leakage Current IGSS VGS = 20V 20 (Note 7) nA Zero Gate Voltage Drain Current IDSS VDS = 80% Rated Value 25 (Note 7) A Drain to Source On Resistance rDS(ON) TC = 25oC at Rated ID 20% (Note 8) Gate Threshold Voltage VGS(TH) ID = 1.0mA 20% (Note 8) V NOTES: 7. Or 100% of Initial Reading (whichever is greater). 8. Of Initial Reading. Screening Information TEST JANS Gate Stress VGS = -30V, t = 250s Pind Required Pre Burn-In Tests (Note 9) MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC) Steady State Gate Bias (Gate Stress) MIL-STD-750, Method 1042, Condition B VGS = 80% of Rated Value, TA = 150oC, Time = 48 hours Interim Electrical Tests (Note 9) All Delta Parameters Listed in the Delta Tests and Limits Table Steady State Reverse Bias (Drain Stress) MIL-STD-750, Method 1042, Condition A VDS = 80% of Rated Value, TA = 150oC, Time = 240 hours PDA 5% Final Electrical Tests (Note 9) MIL-S-19500, Group A, Subgroups 2 and 3 NOTE: 9. Test limits are identical pre and post burn-in. Additional Screening Tests PARAMETER Safe Operating Area Unclamped Inductive Switching SYMBOL SOA TEST CONDITIONS VDS = -80V, t = 10ms MAX UNITS 1.43 A IAS VGS(PEAK) = -15V, L = 0.1mH 21 A Thermal Response VSD tH = 10ms; VH = -25V; IH = 1A 60 mV Thermal Impedance VSD tH = 500ms; VH = -25V; IH = 1A 230 mV (c)2001 Fairchild Semiconductor Corporation JANSR2N7438 Rev. A JANSR2N7438 Rad Hard Data Packages - Intersil Power Transistors 1. JANS Rad Hard - Standard Data Package A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - Hi-Rel Lot Traveler - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data F. Group A - Attributes Data Sheet G. Group B - Attributes Data Sheet H. Group C - Attributes Data Sheet I. Group D - Attributes Data Sheet 2. JANS Rad Hard - Optional Data Package A. Certificate of Compliance B. Serialization Records C. Assembly Flow Chart D. SEM Photos and Report E. Preconditioning - Attributes Data Sheet - Hi-Rel Lot Traveler - HTRB - Hi Temp Gate Stress Post Reverse Bias Data and Delta Data - HTRB - Hi Temp Drain Stress Post Reverse Bias Delta Data - X-Ray and X-Ray Report F. Group A - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups A2, A3, A4, A5 and A7 Data G. Group B - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups B1, B3, B4, B5 and B6 Data H. Group C - Attributes Data Sheet - Hi-Rel Lot Traveler - Subgroups C1, C2, C3 and C6 Data I. Group D - Attributes Data Sheet - Hi-Rel Lot Traveler - Pre and Post Radiation Data (c)2001 Fairchild Semiconductor Corporation JANSR2N7438 Rev. A JANSR2N7438 TO-205AF 3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE INCHES OD OD1 P A SEATING PLANE h L Ob e e1 2 e2 1 90o 3 45o j k MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.160 0.180 4.07 4.57 NOTES - Ob 0.016 0.021 0.41 0.53 2, 3 - OD 0.350 0.370 8.89 9.39 OD1 0.315 0.335 8.01 8.50 - e 0.095 0.105 2.42 2.66 4 e1 0.190 0.210 4.83 5.33 4 e2 0.095 0.105 2.42 2.66 4 h 0.010 0.020 0.26 0.50 - j 0.028 0.034 0.72 0.86 - k 0.029 0.045 0.74 1.14 - L 0.500 0.560 12.70 14.22 3 P 0.075 - 1.91 - 5 NOTES: 1. These dimensions are within allowable dimensions of Rev. E of JEDEC TO-205AF outline dated 11-82. 2. Lead dimension (without solder). 3. Solder coating may vary along lead length, add typically 0.002 inches (0.05mm) for solder coating. 4. Position of lead to be measured 0.100 inches (2.54mm) from bottom of seating plane. 5. This zone controlled for automatic handling. The variation in actual diameter within this zone shall not exceed 0.010 inches (0.254mm). 6. Lead no. 3 butt welded to stem base. 7. Controlling dimension: Inch. 8. Revision 3 dated 6-94. (c)2001 Fairchild Semiconductor Corporation JANSR2N7438 Rev. A TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM FAST FASTrTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM PowerTrench QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER SMART STARTTM Star* PowerTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM UHCTM UltraFET VCXTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H1