Features * * * * * * * 10-bit Resolution 2 Gsps Sampling Rate Selectable 1:2 or 1:4 Demultiplexed Output 500 mVpp Differential 100 or Single-ended 50 Analog Input 100 Differential or Single-ended 50 Clock Input LVDS Output Compatibility Functions: - ADC Gain Adjust - Sampling Delay Adjust - 1:4 Demultiplexed Simultaneous or Staggered Digital Outputs - Data Ready Output with Asynchronous Reset - Out-of-range Output Bit (11th Bit) * Power Consumption: 6.5W * Power Supplies: -5V, -2.2V, 3.3V and VPLUSD Output Power Supply * Package - Cavity Down EBGA 317 (Enhanced Ball Grid Array) - 25 x 35 mm Dimensions 10-bit 2 Gsps ADC With 1:4 DMUX AT84AS004 Performances * 3 GHz Full Power Analog Input Bandwidth * - 0.5 dB Gain Flatness from DC up to 1.5 GHz * Single-tone Performance at Fs = 2 Gsps, Full First and Second Nyquist (- 1 dBFS) - ENOB = 7.8 Effective Bits, FIN = 1000 MHz - SNR = 51 dBc, SFDR = -55 dBc, FIN = 1000 MHz - ENOB = 7.5 Effective Bits, FIN = 2 GHz - SNR = 50 dBc, SFDR = -54 dBc, FIN = 2 GHz * Dual-tone Performance (IMD3) at Fs = 2 Gsps (-7 dBFS Each Tone) - Fin1 = 945 MHz, Fin2 = 955 MHz: IMD3 = - 60 dBFS - Fin1 = 1545 MHz, Fin2 = 1555 MHz: IMD3 = - 60 dBFS Screening * Temperature Range: - Tamb > 0C; TJ < 90C (Commercial C Grade) - Tamb > - 40C; TJ < 110C (Industrial V Grade) Applications * Direct RF Down Conversion * Broadband Digital Receivers * Test Instrumentation * High Speed Data Acquisition * High Energy Physics 5431B-BDC-01/06 1. Description The AT84AS004 combines a 10-bit 2 Gsps analog-to-digital converter with a 1:4 DMUX, designed for accurate digitization of broadband signals in either first or second Nyquist zone. It features 7.8 Effective Number of Bits (ENOB) and -55 dBFS Spurious Free Dynamic Range (SFDR) at 2 Gsps over the full first Nyquist zone and 7.5-bit with 54 dB SFDR over full second Nyquist. The 1:4 demultiplexed digital outputs are LVDS logic compatible, allowing easy interfacing with standard FPGAs or DSPs. The AT84AS004 operates at up to 2 Gsps. The AT84AS004 comes in a 25 x 35 mm EBGA317 package. This package has the same TCE as FR4 boards, offering excellent reliability when subjected to large thermal shocks. 2. Block Diagram Figure 2-1. Block Diagram BIST ASYNRST PGEB DRRB SDA 2 CLK/CLKN 20 SDA 2 VINN Demultiplexer 1:2 or 1:4 LVDS Buffers S/H Logic Block VIN Quantizer 20 2 20 2 20 2 2 Port A AOR/AORN Port B BOR/BORN Port C COR/CORN Port D DOR/DORN DR/DRN GA B/GB SLEEP STAGG RS DRTYPE 2 AT84AS004 5431B-BDC-01/06 AT84AS004 3. Functional Description The AT84AS004 is a 10-bit 2 Gsps ADC combined with a 1:4 demultiplexer (DMUX) allowing to lower the 11 bit output data stream (10-bit data and one out-of-range bit) by a selectable factor of 4 or 2. The ADC works in fully differential mode from analog input through to digital outputs. The ADC should be 50 reverse terminated, as close as possible to the EBGA Package input pin (1 mm maximum). The ADC Clock input is on-chip 100 differentially terminated. The output clock and the output data are LVDS logic compatible, and should be 100 differentially terminated. The AT84AS004 ADC features two asynchronous resets: - DRRB, which ensures that the first digitized data corresponds to the first acquisition. - ASYNCRST, which ensures that the first digitized data will be output on port A of the DMUX. The ADC gain can be tuned-in to unity gain by the means of the GA analog control input A Sampling Delay Adjust function (SDA analog control input, activated via the SDAEN signal) may be used to fine-tune the ADC aperture delay by 120 ps around its center value. The SDA function may be of interest for interleaving multiple ADCs.The control pin B/GB is provided to select either a binary or gray data output format. A tunable delay cell (controlled via CLKDACTRL) is integrated between the ADC and the DMUX on the clock path to fine tune the data vs. clock alignment at the interface between the ADC and the DMUX. This delay can be tuned from -275 to 275 ps around default center value, featuring a 550 ps typical delay tuning range. An extra standalone delay cell is also provided, (controlled via DACTRL analog control input and activated via DAEN). The tuning range is typically 550 ps. A pattern generator (PGEB) is integrated in the ADC part for debug or acquisition setup. Similarly, a Built-in Self Test (BIST) is provided for quick debug of the DMUX part. The output demultiplexing 1:4 or 1:2 ratio can be selected by the means of RS digital control input. Two modes for the output clock (via DRTYPE) can be selected: * DR mode: only the output clock rising edge is active, the output clock rate is the same as the output data rate * DR/2 mode: both the output clock rising and falling edges are active, the output clock rate is half the output data rate The data outputs are available at the output of the AT84AS004 in two different modes: * Staggered: even and odd bits come out with half a data period delay * Simultaneous: even and odd bits come out at the same time A Power reduction mode (SLEEP control input) is provided to reduce the DMUX power consumption. The ADC junction temperature monitoring is made possible through the DIODE input by sensing the voltage drop across 1 diode implemented on the ADC close to chip hot point. The AT84AS004 is delivered in an Enhanced Ball Grid Array (EBGA), very suitable for applications subjected to large thermal variations (thanks to its TCE which is similar to FR4 material TCE). 3 5431B-BDC-01/06 Table 3-1. Functions Description Name Function VCCA Analog 3.3V power supply VCCD Digital 3.3 V power supply VEE Analog -5V power supply VCCA VEE VMINUSD VCCDVPLUSD 3.3V -5V -2.2V 3.3V 2.5V 2 VIN, VINN 20 [A0...A9] [A0N...A9N] 2 AOR/DRAN, AORN/DRA 20 [B0...B9] [B0N...B9N] 2 BOR/DRBN, BORN/DRB 20 [C0...C9] [C0N...C9N] 2 COR/DRCN, CORN/DRC 20 [D0...D9] 2 [D0N...D9N] DOR/DRDN, DORN/DRD 2 DR, DRN 2 DAO, DAON VPLUSD Output 2.5 V power supply VMINUSD Output -2.2V power supply AGND Analog ground DGND Digital ground CLK, CLKN Input clock signals VIN, VINN Analog input data DRRB ADC reset ASYNCRST DMUX asynchronous reset DR/DRN Output clock signals A0...A9 A0N...A9N Output data port A AOR/DRAN, AORN/DRA Additional output bit port A or output clock in staggered mode for port A Name Function B0...B9 B0N...B9N Output data port B DAI, DAIN Input signals for standalone delay cell BOR/DRBN, BORN/DRB Additional output bit port B or output clock in staggered mode for Port B DAO, DAON Output signals for standalone delay cell GA ADC gain adjust C0...C9 C0N...C9N SDAEN ADC SDA enable Output data Port C SDA ADC sampling delay adjust COR/DRCN, CORN/DRC Additional output bit port C or Output clock in staggered mode for Port C PGEB ADC pattern generator D0...D9 D0N...D9N B/GB Binary or gray output code selection Output data Port D SLEEP Sleep mode selection signal DOR/DRDN, DORN/DRD Additional output bit Port D or output clock in staggered mode for Port D STAGG Staggered mode selection for data outputs RS DMUX ratio selection signal CLKTYPE Input clock type selection signal (to be connected to VCCD or left floating) CLKDACTRL Control signal for clock delay cell DRTYPE Output clock type selection signal DACTRL Control signal for standalone delay cell BIST Built-in Self Test DAEN Enable signal for standalone delay cell DIODE ADC Diode for die junction temperature monitoring (ADC) 4 CLK, CLKN DRRB ASYNCRST SDAEN SDA GA PGEB B/GB 2 AT84AS004 2 DACTRL, CLKDACTRL 2 DAI, DAIN SLEEP STAGG CLKTYPE RS DAEN BIST DRTYPE DIODE ADC AGND DGND AT84AS004 5431B-BDC-01/06 AT84AS004 4. Specifications 4.1 Absolute Maximum Ratings Table 4-1. Absolute Maximum Ratings Parameter Symbol Value Unit Analog positive supply voltage VCCA GND to 6 V Digital positive supply voltage VCCD GND to 3.6 V Analog negative supply voltage VEE GND to - 5.5 V Digital positive supply voltage VPLUSD GND to 3 V Digital negative supply voltage VMINUSD GND to - 3 V Maximum difference between VPLUSD and VMINUSD VPLUSD - VMINUSD 5 V Analog input voltages VIN or VINN - 1.5 to 1.5 V Maximum difference between VIN and VINN VIN or VINN - 1.5 to 1.5 Clock input voltage VCLK or VCLKN -1 to 1 V Maximum difference between VCLK and VCLKN VCLK - VCLKN -1 to 1 Vpp Control input voltage GA, SDA - 1 to 0.8 V Digital input voltage SDAEN, B/GB, PGEB, DECB - 5 to 0.8 V DRRB -0.3 to VCCA + 0.3 V RS, CLKTYPE, DRTYPE, SLEEP, STAGG, BIST, DAEN -0.3 to VCCD + 0.3 V ASYNCRST - 0.3 to VCCD + 0.3 DAI, DAIN - 0.3 to VCCD + 0.3 V CLKDACTRL, DACTRL - 0.3 to VCCD + 0.3 V Maximum input voltage on DIODE DIODE ADC 700 mV Maximum input current on DIODE DIODE ADC 1 mA TJ 135 C ADC reset voltage DMUX function input voltage DMUX asynchronous reset DMUX input voltage DMUX control voltage Junction temperature Notes: 1. Absolute maximum ratings are short term limiting values (referenced to GND = 0 V), to be applied individually, while other parameters are within specified operating conditions. Long exposure to maximum ratings may affect device reliability. 2. All integrated circuits have to be handled with appropriate care to avoid damage due to ESD. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure. 5 5431B-BDC-01/06 Table 4-2. Recommended Condition of Use Parameter Symbol Comments Recommended Value Unit Positive supply voltage VCCA 3.3 V Positive supply voltage VCCD 3.3 V Negative supply voltage VEE - 5.0 V Positive negative supply voltage VMINUSD - 2.2 V Differential analog input voltage VIN - VINN 500 mVpp 125 500 mV mVpp 0 dBm GA, SDA - 0.5 to 0.5 V SDAEN, B/GB, PGEB, DECB GND or VEE V DRRB GND to 3.3V V DAI, DAIN GND to 3.3V V SLEEP, STAGG, ASYNCRST, BIST, RS, DAEN, DRTYPE, CLKDACTRL, DACTRL GND to 3.3V V 0C < TC ; TJ < 90C -20C < TC; TJ < 110C C Differential clock input level Clock input power level (ground common mode) ADC control input voltage ADC functions ADC reset DMUX standalone delay cell inputs DMUX control inputs Operating temperature range Vinclk PCLK PCLKN TC; TJ 50 single-ended (VINN grounded through 50) 50 single-ended clock input or 100 differential clok (recommended) Commercial C grade industrial V grade Storage temperature Tstg - 65 to 150 C Maximum junction temperature TJ 125 C 6 AT84AS004 5431B-BDC-01/06 AT84AS004 4.2 Electrical Operating Characteristics * VCCA = VCCD = 3.3V, VEE = -5V, VMINUSD = -2.2V * VINN - VINN = 1 dBFS ( single-ended driven with VINN connected to ground via 50) * PCLK = 0 dBm (differential driven) DC Electrical Characteristics at Ambient Temperature and Hot Temperature (TJ Max) Table 4-3. Test Level Parameter Symbol Min Resolution Typ Max 10 Unit Bit Power Requirements Positive Supply Voltages -analog -digital -digital outputs Positive Supply Current -analog VCCA = 3.3V -digital VCCD = 3.3V (1:2 DMUX) -digital VCCD = 3.3V (1:4 DMUX) -output VPLUSD = 2.5V 1 1 3.15 3.15 2.4 3.3 3.3 2.5 3.45 3.45 2.6 V V V 80 535 565 450 100 590 620 470 mA mA mA mA -5 - 4.75 V 620 660 mA - 2.2 - 2.1 V IVMINUSD 190 200 mA PD 6.5 7.1 W 125 125 mV mV 250 mV IVCCA IVCCD IVCCD IVPLUSD VEE Negative supply voltage VEE Negative supply current Negative supply voltage VCCA VCCD VPLUSD - 5.25 IVEE 1 Negative supply current Power Dissipation (1:2 DMUX) VMINUSD - 2.3 Analog Inputs Full-scale input voltage range Differential mode 0V common mode voltage Full-scale input voltage range Single-ended input option 0V common mode voltage VIN VINN - 125 - 125 VIN, VINN -250 0 4 Analog input power level (50 single-ended) PIN -2 dBm Analog input capacitance (die) CIN 0.3 pF Input leakage current IIN 10 A -single-ended Input resistance -differential RIN 49 50 51 RIN 98 100 102 4 7 5431B-BDC-01/06 Table 4-3. DC Electrical Characteristics at Ambient Temperature and Hot Temperature (TJ Max) (Continued) Parameter Test Level Symbol Min Typ Max Unit Clock Inputs Logic common mode compatibility for clock inputs Differential ECL to LVDS (AC coupling) Clock input common voltage range (VCLK or VCLKN) (0V common mode) VCM - 1.2 0 0.3 V Clock input power level (low-phase noise sinewave input) 50 single-ended or 100 differential PCLK -4 0 4 dBm VCLK 200 320 500 mV VCLK, VCLKN 141 226 354 mV Clock input swing (single ended with CLKN = 50 to GND) 4 Clock input swing (differential voltage) on each clock input Clock input capacitance (die) CLK Clock input resistance - Single-ended - Differential ended RCLK RCLK 0.3 45 90 50 100 pF 55 110 1.25 - 500 1.375 V V mV V 1.0 3.3 V V V Digital Data Outputs Logic compatibility 50 transmission lines, 100 (2 x 50) differential termination) - Logic low - Logic high - Differential output - Common mode LVDS 1 VOL VOH VODIFF VOCM - 1.25 250 1.125 VIL VIH 0 1.6 VIL RIL VIH RIH 0 2 10 K 1.075 1.425 350 1.25 Control Function Inputs DRRB and ASYNCRST - Logic low - Logic high RS, DRTYPE, SLEEP, STAGG, BIST, DAEN - Logic low - Logic high 1 4 SDAEN, PGEB, B/GB - Logic low - Logic high 1 DAI, DAIN - Differential input - Common mode 1 8 0.5 10 VIL VIH -2 VEE 0 VIDIFF VICM 1 100 1.25 350 Infinite V V -3 0 V V 1.6 - V mV AT84AS004 5431B-BDC-01/06 AT84AS004 Table 4-3. DC Electrical Characteristics at Ambient Temperature and Hot Temperature (TJ Max) (Continued) Test Level Parameter Symbol Min Typ Max Unit GA, SDA 1 -0.5 0.5 V CLKDACTRL, DACTRL 1 1/3 x VCCD 2/3 x VCCD V DC accuracy DNLrms 1 DNLrms 0.2 0.3 LSB Differential non-linearity (1) 1 DNL+ 0.8 1.5 LSB Integral non-linearity (1) Integral non-linearity (1) Gain central value (2) 1 1 INL 4 Input offset voltage 1 -4 + INL 1 Gain error drift Note: - 0.95 -10 -2 LSB 2 4 LSB 1 1.05 23 35 ppm/C 10 mV 1. Histogram testing at Fs = 390 Msps Fin = 100 MHz. 2. This range of gain can be set to 1 thanks to the gain adjust function. 9 5431B-BDC-01/06 Table 4-4. AC Electrical Characteristics at Ambient Temperature and Hot Temperature (TJ Max) Test Level Parameter Symbol Min Typ Max Unit AC Analog Inputs Full power input bandwidth (1) Small signal input bandwidth (10% full-scale) (1) FPBW 3 SSBW 3.3 BF - 0.5 VSWR 1.1: 1 GHz GHz 4 Gain flatness (2) Input voltage standing wave ration (3) dB 1.2: 2 AC Performance: Nominal Condition - 1 dBFS single-ended input mode (unless otherwise specified); 50% clock duty cycle; 0 dBm differential clock (CLK,CLKN) binary output data format. Effective Number of Bits Fs = 1 Gsps Fs = 1.5 Gsps Fs = 2 Gsps Fs = 2 Gsps Fin = 100 MHz Fin = 750MHz Fin = 1000 MHz Fin = 2 GHz 1 1 4 4 Fin = 100 MHz Fin = 750MHz Fin = 1000 MHz Fin = 2 GHz 1 1 4 4 ENOB 7.4 7.4 7.3 7.1 8 8 7.8 7.5 Bit SNR 50 49 48 48 52 52 51 50 dBc |THD| 46 46 45 45 52 52 49 49 dBc |SFDR| 50 50 48 48 58 58 55 54 dBc Signal to Noise Ratio Fs = 1 Gsps Fs = 1.5 Gsps Fs = 2 Gsps Fs = 2 Gsps Total Harmonic Distortion Fs = 1 Gsps Fs = 1.5 Gsps Fs = 2 Gsps Fs = 2 Gsps Fin = 100 MHz Fin = 750MHz Fin = 1000 MHz Fin = 2 GHz 1 1 4 4 Spurious Free Dynamic Range Fs = 1 Gsps Fs = 1.5 Gsps Fs = 2 Gsps Fs = 2 Gsps Fin = 100 MHz Fin = 750MHz Fin = 1000 MHz Fin = 2 GHz 1 1 4 4 Two-tone Third-order Inter-modulation Distortion Fs = 2 Gsps Fin1 = 945 MHz, Fin2 = 955 MHz [-7 dBFS] Fin1 = 1545 MHz, Fin2 = 1555 MHz [- 7 dBFS] Note: 4 4 |IMD3| 60 60 dBFS 1. See "Definitions of Terms" on page 40. 2. From DC to 1.5 GHz. 3. Specified from DC up to 2.5 GHz input signal. Input VSWR is measured on a soldered device. It assumes an external 50 2 controlled impedance line, and a 50 driving source impedance (S11 30 dB). 10 AT84AS004 5431B-BDC-01/06 AT84AS004 Table 4-5. Transient and Switching Performances Test Level Symbol Bit error rate (1) 4 BER ADC setting time (VIN-VINN = 400 mVpp) 4 TS Overvoltage recovery time 4 ORT ADC step response rise/fall time (10 - 90%) 4 80 Overshoot 5 4 % Ringback 5 2 % Parameter Min Typ Max Unit 10-13 Error/ sample Transient Performance 400 ps 500 ps 100 ps Switching Performance and Characteristics Maximum clock frequency (2) Minimum clock frequency FS Max (2) FS Maximum clock pulse width (high) Minimum clock pulse width (low) Aperture delay (2) 2 Gsps 150 Min 200 Msps TC1 0.22 2.5 ns TC2 0.22 2.5 ns 4 Aperture uncertainty TA 160 ps Jitter 150 fs rms DRRB pulse width 1 ns ASYNCRST pulse width 1 ns Output Data Data Output Delay (3) Data pipeline delay - Synchronized 1:2 ratio - Synchronized 1:4 ratio - Staggered 1:2 ratio - Staggered 1:4 ratio TOD 4 Data output rise/fall time (20% - 80%) 400 5.5 7.5 4.5/5.5 4.5/5.5/6.5/7.5 TPD TR/TF Clock cycles 400 ps Output Clock Output clock delay (3) Output clock rise/fall time (20% - 80%) Output data to output clock propagation delay TDR 4 400 TR/TF TD1/TD2 0.3 0.333 ps 400 ps 500 ps 11 5431B-BDC-01/06 Table 4-5. Transient and Switching Performances (Continued) Test Level Parameter Symbol Min Typ Max Unit FMSDA 600 DCYCSDA 40 50 60 % TSDAMIN 1.70 2.00 2.30 ns TSDAMAX 2.20 2.50 2.80 ns SDARANGE 400 550 600 ps CLKDACTRL and DACTRL Delay Cells Input frequency MHz 4 Input duty cycle Propagation delay with CLKDACTRL or DACTRL = VCCD/3 4 Propagation delay with CLKDACTRL or DACTRL = 2* VCCD/3 4 Tuning range (4) 4 Note: 1. Output error amplitude < 6 LSB. Fs = 2 Gsps TJ = 110C 2. See "Definitions of Terms" on page 40. 3. TOD and TDR propagation times are defined at package input/outputs. They are given for reference only. See"Definitions of Terms" on page 40. 4. The delay cell used in both standalone delay cell and input clock path has a characteristic that is note linear with junction temperature. The largest tuning range is obtained near ambient temperature. 4.3 Explanation of Test Levels Level Comments 1 100% production tested at 25C (for C Temperature range ). 2 100% production tested at 25C, and sample tested at specified temperatures (for V and M temperature ranges). 3 Sample tested only at specified temperatures 4 Parameter is guaranteed by design and characterization testing (thermal steady-state conditions at specified temperature). 5 Parameter is a typical value only guaranteed by design only Note: 12 Unless otherwise specified: Only minimum and maximum values are guaranteed (typical values are issued from characterization results). AT84AS004 5431B-BDC-01/06 AT84AS004 4.4 Digital Coding Differential Analog Input > 250.25 mV Voltage Level Digital Output Binary (B/GB = GND or floating) GRAY (B/GB = VEE) MSB...LSB out-of-range MSB...........LSB out-of-range >Top end of full-scale + 1/2 LSB 1111111111 1 1000000000 1 250.25 mV Top end of full-scale + 1/2 LSB 1111111111 0 1000000000 0 249.75 mV Top end of full-scale - 1/2 LSB 1111111110 0 1000000001 0 125.25 mV 3/4 full-scale + 1/2 LSB3/4 1100000000 0 1010000000 0 124.75 mV full-scale - 1/2 LSB 1011111111 0 1110000000 0 0.25 mV Mid scale + 1/2 LSB 1000000000 0 1100000000 0 -0.25 mV Mid scale - 1/2 LSB 01 1 1 1 1 1 1 1 1 0 0100000000 0 - 124.75 mV 1/4 full-scale + 1/2 LSB 0100000000 0 0110000000 0 - 124.25 mV 1/4 full-scale - 1/2 LSB 0011111111 0 0010000000 0 - 249.75 mV Bottom end of full-scale + 1/2 LSB 0000000001 0 0000000001 0 - 250.25 mV Bottom end of full-scale - 1/2 LSB 0000000000 0 0000000000 0 250.25 mV < Bottom end of full-scale - 1/2 LSB 0000000000 1 0000000000 1 13 5431B-BDC-01/06 5. Characterization Results 5.1 Nominal Conditions Unless otherwise specified: * * * * 5.2 VCCA = 3.3V, VCCD = 3.3V, VEE = -5V, VPLUSD = 2.5V, VMINUSD = - 2.2V TJ = 80C 50% clock duty cycle, binary output data format - 1 dBFS analog input Full Power Input Bandwidth * Analog input level = - 1 dBFS * Gain flatness at - 0.5 dB from DC to 1.5 GHz Figure 5-1. Full Power Input Bandwidth at - 3 dB 0,0 -0,5 -1,0 -1,5 dBFS -2,0 -0.5 dB Gain Flatness -3 dB Bandwidth -2,5 -3,0 -3,5 -4,0 -4,5 -5,0 -5,5 3300 3100 2900 2700 2500 2300 2100 1900 1700 1500 1300 1100 900 700 500 300 100 -6,0 Fin (MHz) 14 AT84AS004 5431B-BDC-01/06 AT84AS004 5.3 VSWR Versus Input Frequency Figure 5-2. VSWR Curve for the Analog Input (VIN) and Clock (CLK) 2,60 2,40 2,20 CLK VSWR 2,00 VIN 1,80 1,60 1,40 1,20 1,00 0 500 1000 1500 2000 2500 3000 3500 Frequency (MHz) 5.4 Step Response * Tr measured = 114.8 ps = sqrt (TrPulseGenerator + TrADC) * TrPulseGenerator (estimated) = 41 ps * Actual TrADC = 107 ps Figure 5-3. Step Response Rise Time (Fs = 2 Gsps, Fin = 1 GHz) 1200 1100 1000 100% 900 90% 800 700 LSB 600 500 400 300 200 10% 100 0% 0 -100 -200 0 100 200 300 400 500 600 700 800 900 1000 1100 Time (ps) 15 5431B-BDC-01/06 Dynamic Performance Versus Sampling Frequency Dynamic Parameters Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2) ENOB (Bit) Figure 5-4. 10 9 8 7 6 5 4 3 2 1 0 1000 -20 -30 SFDR (dBc) 5.5 -60 1200 1400 1600 Fs (Msps) 1800 -90 1000 2000 1200 1400 1600 Fs (Msps) 1800 2000 1200 1400 1600 Fs (Msps) 1800 2000 90 80 70 SNR (dB) -40 -50 -60 60 50 -70 40 -80 30 -90 1000 SFDR without the first 4 Harmonics -80 -30 THD (dB) Signal dependent and independent SFDR -50 -70 -20 5.6 -40 1200 1400 1600 Fs (Msps) 1800 20 1000 2000 Dynamic Performance Versus Input Frequency Figure 5-5. Dynamic Parameters Versus Input Frequency at Fs = 2 Gsps 10 -20 -30 SFDR (dBFS) ENOB (Bit) 9 8 -40 -50 -60 -70 7 -80 -90 6 0 400 800 1200 Fin (MHz) 1600 2000 400 800 1200 Fin (MHz) 0 400 800 1600 2000 60 -20 58 -30 56 -40 54 SNR (dBFS) THD (dBFS) 0 -50 -60 52 50 48 46 -70 44 -80 -90 0 16 42 40 400 800 1200 Fin (MHz) 1600 2000 1200 Fin (MHz) 1600 2 000 AT84AS004 5431B-BDC-01/06 AT84AS004 5.7 Signal Spectrum Figure 5-6. Fs = 2 Gsps, Fin = 998 MHz - 1 dBFS Analog Input, 1:4 Demultiplexing Factor, 32 kpoint FFT 20 H1 Fundamental (998 MHz) 0 ENOB = 7.8 -20 SFDR (H2) = - 58 dBFS dBc -40 FS/4 -60 -80 -100 -120 -140 0 100 200 300 400 500 600 700 800 900 1000 MHz Figure 5-7. Fs = 2 Gsps, Fin = 1998 MHz - 1 dBFS Analog Input, 1:4 Demultiplexing Factor, 32 kpoint FFT 20 H1 Fundamental image (2 GHz - 1.998 GHz = 2 MHz) 0 ENOB = 7.5 -20 SFDR (H4) = - 58 dBFS dBc -40 FS/4 -60 -80 -100 -120 -140 -160 0 100 200 300 400 500 600 700 800 900 1000 MHz 17 5431B-BDC-01/06 5.8 Dynamic Performance Sensitivity Versus Temperature and Power Supply Figure 5-8. Dynamic Parameters Versus Junction Temperature at Fs = 2 Gsps, Fin = 998 MHz, - 1 dBFS Analog Input -20 10 -30 9 -40 SFDR (dBc ENOB (Bit) 8 7 6 5 -80 3 -90 2 10 20 30 40 50 60 70 Tj (C) 80 90 10 100 110 -20 90 -30 80 -40 70 SNR (dB THD (dB) -60 -70 4 -50 -60 30 40 50 60 70 Tj (C) 80 20 30 40 50 60 70 Tj (C) 80 90 100 110 50 40 -80 30 20 20 30 40 50 60 70 Tj (C) 80 90 100 110 10 90 100 110 Dynamic Parameters at Min., Typ. and Max. Power Supplies, Fs = 2 Gsps, Fin = 998 MHz, - 1 dBFS Analog Input 10 9 SFDR (dBc) ENOB (Bit) 8 7 6 5 4 3 2 Typ. Power Supplies -40 -42 -44 -46 -48 -50 -52 -54 -56 -58 -60 -62 -64 -66 -68 -70 Max. Power Supplies -40 -42 -44 -46 -48 -50 -52 -54 -56 -58 -60 -62 -64 -66 -68 -70 Min. Power Supplies Typ. Power Supplies Max. Power Supplies Min. Power Supplies Typ. Power Supplies Max. Power Supplies 60 58 56 54 SNR (dB) THD (dB) Min. Power Supplies 52 50 48 46 44 42 40 Min. Power Supplies Typ. Power Supplies Note: 18 20 60 -70 -90 10 Figure 5-9. -50 Max. Power Supplies Minimum power supplies: VCC = 3.45,V VEE = - 4.75V Typical power supplies: VCC = 3.3V, VEE = - 5V Maximum power supplies: VCC = 3.15V, VEE = - 5.25V AT84AS004 5431B-BDC-01/06 AT84AS004 5.9 Dual Tone Performance Figure 5-10. Dual Tone Signal Spectrum at Fs = 2 Gsps, Fin1 = 1545 MHz, Fin2 = 1555 MHz (- 7 dBFS) 20 F2 =Fs - Fin2 = 445 MHz -7 dBFS 0 F1 = Fs - Fin1 = 455 MHz -7 dBFS -20 IMD3 dBFS -40 2F1 - Fin2 = 435 MHz -60 F1 + F2 = 900 Mz 2F2 - F1 = 465 Mz -80 -100 -120 -140 -160 0 100 200 300 400 500 600 700 800 900 1000 MHz 5.10 NPR Performance Figure 5-11. Digitizing of 575 MHz Broadband Pattern at 1.4 Gsps, 25 MHz Notch Centered Around 290 MHz, - 12 dBFS Loading Factor 0 NPR = 40.22 dB -20 25MHz Input antiliasing Filter roll-off 25MHz dB -40 -60 -80 -100 -120 0 50 100 150 200 250 300 350 400 450 500 550 600 650 700 F(MHz) 19 5431B-BDC-01/06 20 AGND AGND AGND VEE VCCA VCCA VCCA AGND AGND AGND AGND VEE VCCA VEE VEE SDAEN AGND AGND AGND AGND AGND VCCA VCCA SDA AGND AGND CLK CLKN AGND VEE VCCA VEE DRRB AGND AGND AGND AGND AGND VEE VEE AGND AGND VPLUSD VEE AGND VCCD VCCD VPLUSD VPLUSD VCCD VCCD VCCD B0 AOR / DRAN VPLUSD VPLUSD VPLUSD VPLUSD VCCD VPLUSD VPLUSD B0N AORN / DRA VPLUSD VPLUSD A9 A9N VCCD VPLUSD VPLUSD VCCD DGND VCCD DGND VPLUSD VCCD VCCD B2 B2N DGND VCCD DGND VCCD VCCD VPLUSD B1 B1N AGND VIN AGND AGND AGND VIN AGND AGND AGND VINN AGND AGND AGND AGND VINN GA AGND VCCA VCCA AGND AGND VCCA AGND VPLUSD VCCD DGND DA0 DAON DAI DA1N DACTRL CLKTYPE DAEN BIST VMINUSD VMINUSDCLKDACTRL DGND VEE SUB DGND VPLUSD D9 D9N DGND DOR / DRDN DORN / DRD VCCD D8N D8 VPLUSD D7N D7 VPLUSD D6N D6 VCCD D5N D5 VPLUSD D4N D4 VCCD D3N D3 VPLUSD D2N D2 VCCD D1N D1 VPLUSD D0N D0 VPLUSD C9N C9 COR / DRCN CORN / DRC VPLUSD VPLUSD VCCD VPLUSD C8N C8 VCCD VCCD VPLUSD DGND VPLUSD VPLUSD VPLUSD A8 A8N DGND VCCD VCCD VCCD A7 A7N AGND VPLUSD VPLUSD VPLUSD A6 A6N VPLUSD VPLUSD SUB VCCD A5 A5N VPLUSD VPLUSD SUB VPLUSD A4 A4N AGND VCCD VCCD VMINUSD VMINUSD VCCD DGND DGND VPLUSD VPLUSD A3 A3N DGND VPLUSD VPLUSD VEE AGND VEE VPLUSD VEE AGND VPLUSD DGND DGND A2 A2N A1 A1N DGND VEE VPLUSD VEE AGND AO A0N ASYNCRST VMINUSD VMINUSD AGND STAGG NC VMINUSD VMINUSD SLEEP B/GB VEE AGND AGND VEE VEE AGND AGND DIODE ADC PGEB VPLUSD AGND VEE VCCA VCCA VCCA VCCA VCCA VPLUSD VCCA VCCA VEE VEE VEE VEE VCCA VCCA VEE VCCA C1N C0 C7N C7 C5 C4 C3 C2 NC C6 C6N C5N C4N C3N C2N C0N RS C1 DRTYPE BOR / DRBN DRN DR B9 B9N B8N B7N B6N B5N B4N NC BORN / DRB B8 B7 B6 B5 B4 B3 B3N Figure 6-1. VCCA 6. Pin Description EBGA317 Pinout Table (View from Bottom Package) AT84AS004 5431B-BDC-01/06 AT84AS004 Table 6-1. Pin Description Symbol Pin Number Function DGND C17, C18, D17, D18, F3, F4, H3, H4, M3, M4, P3, P4, R18, T18, U16, U17 Digital ground AGND B21, B23, C21, C23, D21, D23, E21, E23, F21, F23, F26, F27, G25, G26, G27, H25, H26, J25, J26, K27, N25, P25, R22, R23, R24, R25, R26, R27, T22, t23, T24, T25, T26, T27, U22, U23, U24, U25, U26, U27, V21, V23, V24, V26, V27, W22, W25, W26, W27 Analog ground VCCA A24, A26, A27, B24, B26, B27, C24, C26, C27, D24, D26, D27, E24, E26, F25, L25, L26, M27, R21, T21, U21, ADC analog positive power supply VEE A25, B22, B25, C20, C22, C25, D20, D22, D25, E20; E22, E25, F20, F22, F24, K25, K26, L27, M25, M26, N26, N27, R20, T20 ADC analog negative power supply SUB D14, D15, R17 Connect to VEE VPLUSD C4, C5, C6, C7, C9, C11, C13, C14, C15, C16, C19, D5, D6, D7, D9, D11, D13, D19, E3, E19, F19, J3, J4, L3, L4, N3, N4, R3, R4, R19, T6, T7, T9, T11, T13, T14, T15, T19, U4, U5, U6, U7, U9, U11, U13, U14, U15 ADC and DMUX output power supply VCCD C3, C8, C10, C12, D3, D4, D8, D10, D12, D16, E4, E17, G3, G4, K3, K4, R16, T3, T4, T5, T8, T10, T12, T16, T17, U3, U8, U10, U12 DMUX digital power supply VMINUSD A19, A20, B19, B20, E18, F18, U19, U20 ADC digital negative power supply (-2.2V) CLK, CLKN H27, J27 ADC clock differential Inputs ECL/PECL/LVDS compatible VIN V25, W24 ADC in-phase analog input (double pin: one of the two has to be terminated via 50 to ground) VINN V22, W23 ADC Inverted-phase analog input (double pin: one of the two has to be terminated via 50 to ground) A0...A9 B16, B15, B14, B13, B12, B11, B10, B9, B8, B7 In-phase digital outputs port A LVDS compatible A0N...A9N A16, A15, A14, A13, A12, A11, A10, A9, A8, A7 Inverted-phase digital outputs port A LVDS compatible AOR/DRAN, AORN/DRA B6, A6 Port additional bit or port A output clock in staggered mode Power Supplies Inputs Outputs 21 5431B-BDC-01/06 Table 6-1. Pin Description (Continued) Symbol Pin Number Function B0...B9 B5, B4, B3, B2, C2, D2, E2, F2, G2, H2 In-phase digital outputs port B LVDS compatible B0N...B9N A5, A4, A3, A2, B1, C1, D1, E1, F1, G1 Inverted-phase digital outputs port B LVDS compatible BOR/DRBN, BORN/DRB J2, H1 Port B additional bit or port B output clock in staggered mode C0...C9 M2, N2, P2, R2, T2, U2, V1, V2, V3, V4 In-phase digital outputs port C LVDS compatible C0N...C9N L1, M1, N1, P1, R1, T1, U1, W2, W3, W4 Inverted-phase digital outputs port C LVDS compatible COR/DRCN, CORN/DRC V5, W5 Port C additional bit or port V output clock in staggered mode D0...D9 V6, V7, V8, V9, V10, V11, V12, V13, V14, V15 In-phase digital outputs port D LVDS compatible D0N...D9N W6, W7, W8, W9, W10, W11, W12, W13, W14, W15 Inverted-phase digital outputs port D LVDS compatible DOR/DRDN, DORN/DRD V16, W16 Port D additional bit or port D output clock in staggered mode DR, DRN J1, K2 Differential output clock LVDS compatible P27 ADC data ready reset LVCMOS (3.3V) compatible B17 DMUX asynchronous reset -Leave floating or connect to VCCD for normal mode -Connect to ground for reset mode SDAEN P26 ADC sampling delay adjust enable -SDA disabled when left floating or connected to ground -SDA enabled when connected to VEE SDA E27 ADC sampling delay adjust ( 0.5V range) A23 Pattern generator enable -Leave floating or connect to ground for normal mode -Connect to VEE for test mode B/GB A21 Binary or gray output coding selection -Leave floating or connect to ground for binary coding -Connect to VEE for gray coding GA W21 ADC gain adjust control pin ( 0.5V range) CLKTYPE V18 Connect to VCCD Control Functions Inputs DRRB ASYNCRST PGEB 22 AT84AS004 5431B-BDC-01/06 AT84AS004 Table 6-1. Pin Description (Continued) Symbol Pin Number Function A18 DMUX SLEEP mode Enable -leave floating or connect to VCCD for normal mode -connect to ground for SLEEP mode A17 DMUX staggered mode enable -leave floating or connect to VCCD for normal mode -connect to ground for STAGG mode K1 DMUX output clock mode selection -connect to ground for DR/2 type -leave floating or connect to VCCD for DR type L2 DMUX Ratio mode selection -connect to ground for 1:2 ratio -leave floating or connect to VCCD for 1:4 ratio BIST V17 DMUX BIST mode -leave floating or connect to VCCD for normal mode -connect to ground for BIST mode CLKDACTRL U18 DMUX clock delay control (from 1/3 x VCCD to 2/3 x VCCD) DACTRL W18 Standalone delay cell control (from 1/3 x VCCD to 2/3 x VCCD) DAEN W17 Standalone delay cell enable -delay cell disabled when left floating or connected to VCCD -delay cell enabled when connected to ground DAI, DAIN W19, V19 Standalone delay cell differential inputs LVDS compatible DAO, DAON W20, V20 Standalone delay cell differential outputs LVDS compatible DIODE ADC A22 ADC die junction temperature monitoring NC A1, B18, W1 No connect (leave this pin floating) SLEEP STAGG DRTYPE RS Control Functions Outputs 23 5431B-BDC-01/06 7. Main Features 7.1 Reset There are two reset signals available: DRRB and ASYNCRST. DRRB is active low while ASYNCRST is active high. These reset signals are required to start the device properly. It is recommended to apply both reset signals simultaneously. Please refer to the Application Section for more information on how to implement the reset functions. In the case of multiple channels, it is recommended to hold the input clock signal low during reset (as described in Figure 7-1) to ensure synchronization of the channels. The DRRB/ASYNCRST signal frequency should be 200 MHz maximum. The reset pulse should be 1 ns minimum. Figure 7-1. Asynchronous Reset Timing Diagram, 1:2 Mode, Simultaneous Mode (Principle of Operation) TA = 160 ps N VIN CLK 1 ns min DRRB 1 ns min ASYNCRST TOD + 5.5 cycles A0...A9 N N+2 B0...B9 N+1 N+3 N+4 N+5 DR (DR mode) DR (DR/2 mode) 24 AT84AS004 5431B-BDC-01/06 AT84AS004 Figure 7-2. Asynchronous Reset Timing Diagram, 1:4 Mode, Simultaneous Mode (Principle of Operation) TA = 160 ps N VIN CLK 1 ns min DRRB 1 ns min ASYNCRST TOD + 7.5 cycles A0...A9 N B0...B9 N+1 C0...C9 N+2 D0...D9 N+3 DR (DR mode) DR (DR/2 mode) 7.2 Control Signal Settings The SLEEP, RS, DAEN, STAGG, BIST and DRTYPE control signals use the same static buffer. ASYNCRST is activated on logic high (tied/switched to VCCD = 3.3V, or 10 k to ground, or left floating) and deactivated on logic low (grounded). SLEEP, DAEN, STAGG, BIST are activated on logic low (10 grounded), and deactivated on logic high (10 K to ground, or tied to VCCD = 3.3V, or left floating). This is illustrated in Figure 7-3. Figure 7-3. Control Signal Setting Not Control signal pin 10 GND Control signal pin 10 K connected Control signal pin GND Low level High level (`1') (`0') 25 5431B-BDC-01/06 Table 7-1. Function DMUX Mode Settings - Summary Logic Level BIST Electrical Level Description 0 10 to ground BIST 1 10 k to ground Normal conversion N/C 0 SLEEP 10 to ground Power reduction mode (the outputs are fixed at an arbitrary LVDS level) 10 to ground 1 Normal conversion N/C STAGG 0 10 to ground 1 10 k to ground Staggered mode Simultaneous mode N/C DAEN 0 10 to ground 1 10 k to ground Standalone delay adjust activated Standalone delay adjust disabled N/C RS 0 10 to ground 1 10 k to ground 1:2 ratio 1:4 ratio N/C ASYNCRST 0 10 to ground 1 10 k to ground Normal conversion Reset N/C 0 10 to ground DR/2 mode 10 k to ground DRTYPE 1 DR mode N/C 26 AT84AS004 5431B-BDC-01/06 AT84AS004 7.3 Programmable DMUX Ratio The demultiplexer ratio is programmable thanks to the RS ratio selection signal: RS DMUX Ratio 0 1:2 1 1:4 Figure 7-4. DMUX in 1:2 Ratio Output Words: Input Words: 1, 2, 3, 4, 5, 6, 7, 8... 1:2 Figure 7-5. 1 3 5 2 4 Not Used Not Used ... DMUX in 1:4 Ratio Input Words: 1, 2, 3, 4, 5, 6, 7, 8... Output Words: 1:4 7.4 Port A Port B Port C Port D Port A Port B Port C Port D 1 2 3 4 5 6 7 8 9 ... Output Mode (STAGG) Two output mode are provided: * Staggered: the output data come out of the DMUX the one after the other; * Simultaneous: the output data come out of the DMUX at the same time. In staggered mode, the output clock for each port is provided by the DRA, DRAN, DRB, DRBN, DRC, DRCN and DRD, DRDN signals which corresponds respectively to the AORN, AOR, BRON, BOR, CORN, COR, DORN and DOR. The simultaneous mode is the default mode (STAGG left floating of at logic 1). The staggered mode is activated by the means of the STAGG input (active low). 27 5431B-BDC-01/06 Figure 7-6. Simultaneous Mode in 1:4 Ratio (STAGG = 1) DR (in DR mode) DR (in DR/2 mode) Data Out Port A N Data Out Port B Data Out Port C Data Out Port D Figure 7-7. N+4 N+1 N+5 N+2 N+6 N+3 N+7 Staggered Mode in 1:2 Ratio (STAGG = 0) Data Out N Port A Data Out Port B N - 1 N+2 N+1 N+3 DRA (AORN) in DR mode DRA (AORN) in DR/2 mode DRB in DR mode DRB (BORN) in DR/2 mode DR (in DR mode) DR (in DR/2 mode) 28 AT84AS004 5431B-BDC-01/06 AT84AS004 Figure 7-8. Staggered Mode in 1:4 Ratio (STAGG = 0) Data Out Port A N N+4 DRA (AORN) in DR mode DRA (AORN) in DR/2 mode Data Out Port B N+1 N+5 DRB (BORN) in DR mode DRB (BORN) in DR/2 mode Data Out Port C N - 2 N+6 N+2 DRC (CORN (in DR mode) DRC (CORN (in DR/2 mode) Data Out Port D N -1 N+3 DRD (DORN) in DR mode DRD (DORN) in DR/2 mode DR in DR mode DR in DR/2 mode 7.5 Additional Bit In simultaneous output mode: The (AOR/DRAN, AORN/DRA), (BOR/DRBN, BORN/DRB), (COR/DRCN, CORN/DRC) and (DOR/DRDN, DORN/DRD) signals are used to process the out-of-range bit from the ADC as the ADC output data. In 1:2 ratio, (AOR, AORN) and (BOR, BORN) will output this signal at half its initial speed. In 1:4 ratio, (AOR, AORN), (BOR, BORN), (COR, CORN) and (DOR, DORN) will output this signal at 1/4 of its initial speed. In Staggered output mode: (AOR/DRAN, AORN/DRA), (BOR/DRBN, BORN/DRB), (COR/DRCN, CORN/DRC) and (DOR/DRDN, DORN/DRD) will output a Data Ready signal for each ports, centered on the corresponding data. 29 5431B-BDC-01/06 The frequency of the (DRA, DRAN), (DRB, DRBN), (DRC, DRCN) and (DRD, DRDN) depends on the DRTYPE mode (same as data in DR mode, half in DR/2 mode). In 1:2 ratio, DR/DRN and DRB/DRBN are the same. In 1:4 ratio, DR/DRN and DRD/DRDN are the same. 7.6 Output Clock Type Selection Two modes for the output clock type can be chosen: * DR mode: only the output clock rising edge is active, the output clock rate is the same as the output data rate; * DR/2 mode: both the output clock rising and falling edges are active, the output clock rate is half the output data rate. This is illustrated in Figure 7-9 and Figure 7-10. Figure 7-9. DR Mode DR Data Out Figure 7-10. DR/2 Mode DR Data Out Table 7-2. Table 8. DMUX Output Clock Type Selection Settings DRTYPE DMUX Output Clock Type 1 DR 0 DR/2 When DRTYPE is left floating, the default mode is DR. 7.7 Power Reduction Mode (SLEEP) The power reduction (SLEEP) mode allows the user to reduce the power consumption of the device (demultiplexing part in Sleep mode). In this mode, the device's consumption is reduced to 5W. The Power reduction mode is active when SLEEP is low. The device is in normal mode when SLEEP is high. 7.8 Standalone Delay Cell A standalone delay cell is provided to allow the user to add a delay on the DAI/DAIN differential input signal. The delay is controlled via the DACTRL. The tuning range is about 550 ps varying from VCCD / 3 to (2 x VCCD) / 3. This function results in a delayed output signal: DAO/DAON. The DAI/DAIN and DAO/DAON are LVDS signals. 30 AT84AS004 5431B-BDC-01/06 AT84AS004 Figure 7-11. Standalone Delay Cell Block Diagram 2 DAI/DAIN Delay (550 ps) 2 DAO/DAON DACTRL 7.9 Clock input Delay Cell A delay cell is provided to allow the user to tune the delay between clock and data at the DEMUX input. The delay is controlled via the CLKDACTRL. It ranges from -275 ps to 275 ps for CLKDACTRL varying from VCCD / 3 to (2 x VCCD) / 3. This function results in a delayed internal clock signal. Figure 7-12. Standalone Delay Cell Block Diagram 2 CLK/CLK N Delay ( - 275 to 275 ps) 2 Internal clock signal CLKDACTRL 7.10 Built-In Self Test The Built-in Self Test allows to test rapidly the DMUX block of the device. It is activated via the BIST bit (active low). When this signal is left floating, the BIST is inactive. When in BIST mode, a clock must be applied to the device, which can be set to 1:2 or 1:4 mode. The output clock mode DRTYPE can be either DR or DR/2. In the BIST mode, all the bits are either all at low or high level (even and odd bits are in phase opposition) and transition every new cycle. For proper operation of the Built-In Self Test, VCCD should be set to 3.3V minimum. 7.11 ADC Die Junction Temperature Monitoring A die junction temperature measurement setting is available, for maximum junction temperature monitoring (hot point measurement). The measurement method consists in forcing a 1 mA current into a diode mounted transistor and sensing the voltage across the DIODE pin and the closest available ground pin. The measurement setup is described in Figure 7-13 on page 32. 31 5431B-BDC-01/06 Figure 7-13. ADC Diode for Die Junction Temperature Monitoring Setup (10 in parallel of 3) DIODE 10 protection diodes AGND 1 mA Protection Diodes Caution: Respect the current source polarity. In all cases, make sure that the maximum voltage compliance of the current source is limited to a maximum of 1V or use a resistor mounted in series with the current source to avoid damages, which may occur to the transistor device (this may occur for instance if the current source is connected in reverse). The diode VBE forward voltage versus junction temperature (in steady state conditions) characteristic is given in Figure 7-14. The forward voltage drop, (VDIODE) across diode component, versus junction temperature , (including chip parasitic resistance) , is given below (IDIODE = 1 mA). 32 AT84AS004 5431B-BDC-01/06 AT84AS004 Figure 7-14. ADC DIODE Characteristic (I = 1 mA) Junction temperature Versus Diode Voltage for I= 1 mA 950 940 930 920 910 900 890 880 870 Diode voltage (mV) 860 850 840 830 820 810 800 790 780 770 760 750 740 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 Jonction temperature (C) Note: 7.12 The operating die junction temperature must be kept below 125C, to ensure long term device reliability. Pattern Generator Function The Pattern Generator function (enabled by connecting pin PGEB to ECL low or to VEE = -5V) allows to check rapidly the ADC operation thanks to a checker board pattern delivered internally to the ADC. Each output bit of the ADC should toggle from 0 to 1 successively. At the AT84AS004 output, all bits of each port are all 1 or all 0 and transition every cycle. 7.13 ADC Gain Control The ADC gain is adjustable by the means of the pin W21 of the EBGA package. The gain adjust transfer function is given below: 1.30 1.20 Typical 1.10 ADC Gain 1.00 Min 0.90 0.80 0.70 0.60 0.50 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 VGA Gain Adjust Voltage (V) 33 5431B-BDC-01/06 7.14 Sampling Delay Adjust Sampling delay adjust (SDA pin) allows to fine tune the sampling ADC aperture delay TAD around its nominal value (160ps). This functionality is enabled thanks to the SDAEN signal, which is active when tied to VEE and inactive when tied to GND This feature is particularly interesting for interleaving ADCs to increase sampling rate.The variation of the delay around its nominal value as a function of the SDA voltage is shown in the following graph (simulation result): Figure 7-15. Typical Tuning Range is 120 ps for Applied Control Voltage Varying Between 0.5 V to 0.5 V on SDA pin. 400 p Delay in the Variable Delay Cell at 60 C Delay(s) 300 p 200 p 100 p -500 m -400 m -300 m -200 m -100 m 0.00 100 m 200 m 300 m 400 m 500 m SDA Voltage Note: 34 The variation of the delay in function of the temperature is negligible. AT84AS004 5431B-BDC-01/06 AT84AS004 8. Equivalent Input/Output Schematics 8.1 Equivalent Analog Input Circuit and ESD Protection Figure 8-1. AT8AS004 Analog Input Buffer Schematic (VIN/VINN) VEE = - 5V Double Pad 260fF 50 ESD 120fF GND VIN 1mA Package Pins 1.5V 50 Controlled Transmission Lines (Bonding + Package + Ball) Die Double Pads 50 Controlled Transmission Lines (Bonding + Package + Ball) 1mA VINN 50 ESD 120fF GND VEE = - 5V Note: Equivalent Clock Input Circuit and ESD Protection Figure 8-2. AT84AS004 Clock Input Buffer Schematic (CLK/CLKN) 150 CLK 400 A Double Pad 260fF ESD 120fF VEE = -5V 50 VEE = -5V 8.2 External 50 reverse termination are required. 40pF GND ESD 215fF Double Pad 260fF VEE = -5V 50 400 A CLKB ESD 120fF Double Pad 260fP 150 VEE = -5V Note: The 100 termination mid point is on chip and AC coupled to ground through a 40 pF capacitor. 35 5431B-BDC-01/06 8.3 Equivalent Data/Clock Output Buffer Circuit and ESD Protection Figure 8-3. AT84AS004 Data (Ai/AiN...Di/DiN), Clock (DR/DRN) and DAO/DAON Output Buffer Schematic VPLUSD (2.5V 5%) 200 vccdiode ESD: vccdiode C = 435 fF 701 vccdiode ESD: vccdiode C = 435 fF 701 out 361 outn 361 ESD: gnddiode C = 272 fF gnddiode ESD: gnddiode C = 272 fF gnddiode 50.0 1.1K 1.4K 1.4K DGND (0V) SUBST (-5V) 8.4 Standalone Delay Cell Data Input (DAI/DAIN) Buffer Circuit and ESD Protection Figure 8-4. AT84AS004 Standalone Delay Cell Input DAI/DAIN Buffer Schematic VCCD (3.3V 5%) 2.00K ESD: vccdiode C = 435 fF npn in npn 200 1.25V 0.175V 2.00K ESD: vccdiode C = 435 fF 49.9 49.9 inb 200 1.25V 0.175V ESD: ESD: gnddiode gnddiode C = 272fF C = 272fF 4.00k 5.00p DGND (0V) SUBST (-5V) 36 AT84AS004 5431B-BDC-01/06 AT84AS004 8.5 Delay Cell (DACTRL/DACTRLN and CLKCTRL/CLKCTRLN) Control Input Schematic and ESD Protection Figure 8-5. AT84AS004 Delay Cell Control Input DACTRL/DACTRLN and CLKCTRL/CLKCTRLN Buffer Schematic VCCD (3.3V 5%) ESD: vccdiode C = 435 fF 10.0K 2.00K 2.00K 2.00K 698 698 2.00K in ESD: gnddiode C = 272 fF 10.0K 2.00K 600 a 2.00K DGND (0V) SUBST 8.6 DRRB Equivalent Input Schematic and ESD Protection Figure 8-6. AT84AS004 DRRB Reset Input Buffer Schematic VCC = 3.3V 1.4V VCC = 3.3V VCC = 3.3V GND 8 K DRRB -2.6V 200 130 fF 10 K 5 K 5 K VEE = -5V GND GND VEE = -5V 37 5431B-BDC-01/06 8.7 ASYNCRST Equivalent Input Schematic and ESD Protection Figure 8-7. AT84AS004 Asynchronous Reset ASYNCRST Buffer Schematic VCCD (3.3V 5%) 4.00K ESD: vccdiode C = 435 fF 25.0K 12.7K 399 399 9.32K 4.00K 4.00K 4.00K in ESD: gnddiode C = 272 fF 75 ua DGND (0V) SUBST (-5V) 8.8 ADC Gain Adjust Equivalent Input Circuits and ESD Protection Figure 8-8. AT84AS004 Gain Adjust Control Input Buffer Schematic (GA) VCC = 5 V ESD 65fF 0.9V 0V 1 k GA PAD 130fF 20 ESD 75fF 10p F VEE = - 5V GND 100 A 100 A VEE = - 5V 38 AT84AS004 5431B-BDC-01/06 AT84AS004 8.9 B/GB and PGEB Equivalent Input Schematics and ESD Protection Figure 8-9. AT84AS004 B/GB and PGEB Control Buffer Schematic GND GND GND 2k 1k ESD 65fF 5k -1.3V B/GB ESD 75fF PAD 130fF 250 A 250 A VEE = - 5V VEE = -5V 8.10 Control Signals Input Buffers and ESD Protection Figure 8-10. AT84AS004 Control Signals Buffer Schematic (RS, DRTYPE, BIST, SLEEP, STAGG, RS, DAEN) VCCD (3.3V 5%) 4.00K 1.2K 10.0K 1.2K 200 ESD: vccdiode C = 435 fF in 8K 16.00K 10 = 0 10 K = 1 10.0K ESD: gnddiode C = 272 fF DGND (0V) SUBST (-5V) 39 5431B-BDC-01/06 9. Definitions of Terms (Fs max) Maximum Sampling Frequency Sampling frequency for which ENOB < 6bit.s (Fs min) Minimum Sampling frequency Sampling frequency for which the ADC Gain has fallen by 0.5 dB with respect to the gain reference value. Performances are not guaranteed below this frequency. (BER) Bit Error Rate Probability to exceed a specified error threshold for a sample at maximum specified sampling rate. An error code is a code that differs by more than 4 LSB from the correct code. (FPBW) Full Power Input Bandwidth Analog input frequency at which the fundamental component in the digitally reconstructed output waveform has fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for input at fullscale -1 dB (- 1 dBFS). (SSBW) Small Signal Input Bandwidth Analog input frequency at which the fundamental component in the digitally reconstructed output waveform has fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for input at fullscale -10 dB (- 10 dBFS). (SINAD) Signal to Noise and Distortion Ratio Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below full-scale (- 1 dBFS), to the RMS sum of all other spectral components, including the harmonics except DC. (SNR) Signal to Noise Ratio Ratio expressed in dB of the RMS signal amplitude, set to 1dB below full-scale, to the RMS sum of all other spectral components excluding the twenty five first harmonics. Total Harmonic Distortion Ratio expressed in dB of the RMS sum of the first twenty five harmonic components, to the RMS input signal amplitude, set at 1 dB below fullscale. It may be reported in dB (i.e, related to converter -1 dB full-scale), or in dBc (i.e, related to input signal level ). Spurious Free Dynamic Range Ratio expressed in dB of the RMS signal amplitude, set at 1 dB below full-scale, to the RMS value of the highest spectral component (peak spurious spectral component). The peak spurious component may or may not be a harmonic. It may be reported in dB (i.e., related to converter -1 dB full-scale), or in dBc (i.e, related to input signal level ). (THD) (SFDR) (ENOB) Effective Number of Bits A SINAD - 1 76 + 20 log -------------FS 2ENOB = ---------------------------------------------------------------------------6 02 Where A is the actual input amplitude and V is the full-scale range of the ADC under test. Differential Non-Linearity The Differential Non Linearity for an output code i is the difference between the measured step size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum value of all DNL (i). DNL error specification of less than 1 LSB guarantees that there are no missing output codes and that the transfer function is monotonic. (INL) Integral Non-Linearity The Integral Non Linearity for an output code i is the difference between the measured input voltage at which the transition occurs and the ideal value of this transition. INL (i) is expressed in LSBs, and is the maximum value of all INL (i). (TA) Aperture Delay Delay between the rising edge of the differential clock inputs (CLK,CLKB) (zero crossing point), and the time at which (VIN,VINB) is sampled. (DNL) 40 AT84AS004 5431B-BDC-01/06 AT84AS004 (JITTER) Aperture Uncertainty Sample to sample variation in aperture delay. The voltage error due to jitter depends on the slew rate of the signal at the sampling point. (TS) Settling Time Time delay to achieve 0.2 % accuracy at the converter output when a 80% full-scale step function is applied to the differential analog input. (ORT) Over Voltage Recovery Time Time to recover 0.2 % accuracy at the output, after a 150 % full-scale step applied on the input is reduced to midscale. (TOD) Digital Data Output Delay Delay from the rising edge of the differential clock inputs (CLK,CLKB) (zero crossing point) to the next point of change in the differential output data (zero crossing) with specified load. (TDR) Data Ready Output Delay Delay from the falling edge of the differential clock inputs (CLK,CLKB) (zero crossing point) to the next point of change in the differential output data (zero crossing) with specified load. (TD1) Time Delay from Data Transition to Data Ready General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock period. (TD2) Time delay from Data Ready to Data General expression is TD2 = TC2 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock period. (TC) Encoding Clock Period TC1 = Minimum clock pulse width (high) TC = TC1 + TC2TC2 = Minimum clock pulse width (low). (TPD) Pipeline Delay Number of clock cycles between the sampling edge of an input data and the associated output data being made available, (not taking in account the TOD). (TRDR) Data Ready Reset Delay Delay between the falling edge of the Data Ready output asynchronous Reset signal (DDRB) and the reset to digital zero transition of the Data Ready output signal (DR). (TR) Rise Time Time delay for the output DATA signals to rise from 20% to 80% of delta between low level and high level. (TF) Fall Time Time delay for the output DATA signals to fall from 20% to 80% of delta between low level and high level. (PSRR) Power Supply Rejection Ratio Ratio of input offset variation to a change in power supply voltage. (NRZ) Non Return to Zero When the input signal is larger than the upper bound of the ADC input range, the output code is identical to the maximum code and the out-ofrange bit is set to logic one. When the input signal is smaller than the lower bound of the ADC input range, the output code is identical to the minimum code, and the out-of-range bit is set to logic one. (It is assumed that the input signal amplitude remains within the absolute maximum ratings). (IMD) Inter modulation distortion The two tones inter modulation distortion (IMD) rejection is the ratio of either input tone to the worst third order intermediation products. (NPR) Noise Power Ratio The NPR is measured to characterize the ADC performance in response to broad bandwidth signals. When applying a notch-filtered broadband white-noise signal as the input to the ADC under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the average in-notch power spectral density magnitudes for the FFT spectrum of the ADC output sample test. (VSWR) Voltage Standing Wave Ratio The VSWR corresponds to the ADC input insertion loss due to input power reflection. For example a VSWR of 1.2 corresponds to a 20 dB return loss (i.e.. 99% power transmitted and 1% reflected). 41 5431B-BDC-01/06 10. Thermal and Moisture Characteristics As there is no JEDEC standard definition for the thermal resistance applied to a multi-die device, only the thermal resistance for each die (ADC block powered on only or DMUX block powered on only) is provided. For easy understanding of the thermal behavior of the device, thermal data with both devices powered on are however provided. All results were computed with ANSYS thermal simulation tool and with the following assumptions: * Half geometry simulation * DC heating zone = 1.9 x 1.9 mm * MUX heating 4.0 x 4.0 mm * No air, pure conduction, no radiation 10.1 Thermal Resistance from Junction To Bottom of Balls When both blocks are powered on, the thermal simulation results in: * Temperature at the center of the ADC block = 32.9C * Temperature at the center of the DMUX block = 13.6C When each block is powered on at a time, the resulting thermal resistance from junction to bottom of balls is: * Rth Junction-bottom of balls (ADC block on only) = 7C/W * Rth Junction-bottom of balls (DMUX block on only) = 3.9C/W 10.2 Thermal Resistance from Junction To Top of Case When both blocks are powered on, the resulting thermal resistance from junction to top of case is: * Temperature at the center of the ADC block = 18.5C * Temperature at the center of the DMUX block = 4.1C When each block is powered on at a time, the resulting thermal resistance from junction to top of case is: * Rth Junction- top of case (ADC block on only) = 4.1C/W * Rth Junction- top of case (DMUX block on only) = 1.5C/W 10.3 Thermal Resistance from Junction To Board When both blocks are powered on, the resulting thermal resistance from junction to board is: * Temperature at the center of the ADC block = 57.6C * Temperature at the center of the DMUX block = 37.3C When each block is powered on at a time, the resulting thermal resistance from junction to board is: * Rth Junction- board (ADC block on only) = 8C/W * Rth Junction- board (DMUX block on only) = 4.9C/W Note: 42 Assumed board size = 53 x 43 mm AT84AS004 5431B-BDC-01/06 AT84AS004 10.4 Thermal Resistance from Junction To Ambient When both blocks are powered on, the resulting thermal resistance from junction to ambient is: * Temperature at the center of the ADC block = 106C * Temperature at the center of the DMUX block = 85.3C When each block is powered on at a time, the resulting thermal resistance from junction to ambient is: * Rth Junction- ambient (ADC block on only) = 17.1C/W * Rth Junction- ambient (DMUX block on only) = 13.9C/W 10.5 Thermal Management Recommendations In still air and 25C ambient temperature conditions, the maximum temperature of 106C + 25C = 131C is reached for the ADC block. It is consequently necessary to manage the heat from the AT84AS004 very carefully to avoid permanent damages of the device due to over temperature operation. In no air cooling conditions, an external heatsink must be placed on top of package. An electrical isolation may be necessary as the top of the package is at VEE = -5V potential. It is advised to use an external heatsink with intrinsic thermal resistance better than 4C/Watt when using air at room temperature 20~25C.At 60C, the external heatsink should have an intrinsic thermal resistance better than 3C/Watt.Figure 27 provides the outlines of the heat sink used on the AT84AS004-EB evaluation board. Figure 10-1. AT84AS004-EB Evaluation Board Heat Sink Outlines 60 x 52 2. 7 4 10 50.4 x 50.7 x 16.5 heat sink 13 x 26 Note: All units are in mm 43 5431B-BDC-01/06 10.6 Moisture Characteristics This device is sensitive to the moisture (MSL3 according to JEDEC standard). Shelf life in sealed bag : 12 months at <40C and <90% relative humidity (RH). After this bag is opened, devices that will be subjected to infrared reflow, vapor-phase reflow, or equivalent processing (peak package body temp. 220C) must be : - mounted within 168 hours at factory conditions of 30C/60% RH, or - stored at 20% RH Devices require baking, before mounting, if Humidity Indicator is >20% when read at 23C 5C. If baking is required, devices may be baked for : - 192 hours at 40C + 5C/-0C and <5% RH for low temperature device containers, or - 24 hours at 125C 5C for high-temperature device containers. 11. Applying the AT84AS004 11.1 Bypassing, Decoupling and Grounding All power supplies have to be decoupled to ground as close as possible to the signal accesses to the board by 1 F in parallel to 100 nF. Figure 11-1. AT84AS004 Power supplies Decoupling and grounding Scheme Power Supply Plane External Power Supply Access (VCCD , VCCA , VEE , 1 F 100 nF VPLUSD or V MINUSD ) Ground Note: VCCD and VCCA planes should be separated but the two power supplies can be reunited by a strap on the board. Each group of neighboring power supply pins attributed to the same value should be bypassed with at least one pair of 100 pF in parallel to 10 nF capacitors. These capacitors should be placed as close as possible to the power supply package pins. The minimum required pairs of capacitors by power supply type is: - 10 for VCCA - 15 for VCCD - 11 for VEE - 22 for VPLUSD - 3 for VMINUSD 44 AT84AS004 5431B-BDC-01/06 AT84AS004 Figure 11-2. AT84AS004 Power Supplies Bypassing Scheme AT84AS004 3 VVCCD CCD 100 pF 100 pF VVCCA CCA X 10 (min) 10 nF DGND 10 nF AGND V PLUS D 100 pF X 11 (min) 10 nF X 15 (min) V EE AGND 100 pF 10 nF X 22 (min) 10 nF X 3 (min) DGN D VMINUSD 100 pF DGN D 11.2 Analog Input Implementation Two pins are available for each positive (VIN) and negative (VINN) inputs. It is necessary to terminated one of each input pair by 50 to ground as close as possible to the EBGA package pins. This is illustrated in Figure 30. Figure 11-3. AT84AS004 Analog Input Reverse Termination Scheme AT84AS004 50 VIN (V25) GND VIN (W24) Differential or 50 Lines single- ended signal VINN (W23) 50 VINN (V22) GND The analog input of the AT84AS004 device can be indifferently entered in single-ended or differential mode. 45 5431B-BDC-01/06 Figure 11-4. AT84AS004 Analog Input Termination Scheme (Single-ended) 50 Single ended signal Full-scale amplitude = 500 mVp-p Centered on 0V common mode AT84AS004 VIN (V25) GND 50 Line VIN (W24) VIN 500 mVp-p 250 mV VINN VINN (W23) 50 VINN (V22) -250 mV 50 GND Note: The two 50 terminations connected to the two negative inputs (VINN) can be replaced by one 25 resistor to ground. Figure 11-5. AT84AS004 Analog Input Termination Scheme (Differential) AT84AS004 50 VIN (V25) GND VIN (W24) 50 Lines VINN (W23) 250 mV 250 mV Differential signal Full-scale amplitude = 500 mVp-p Centered on 0V common mode VIN VINN 125 mV VINN (V22) -125 mV 50 GND 11.3 Clock Input Implementation The AT84AS004 clock inputs (CLK/CLKN) are designed for either single-ended or differential operation but it is recommended to drive the clock differentially to optimize the device's performances at high frequencies. No external 50 termination are required for the clock inputs (CLK/CLKN) as they are already on-chip terminated by two 50 resistors connected to ground via an on-chip 40 pF capacitor. The AT84AS004 input clock can be used in either DC coupled (0V common mode) or AC coupled (ECL, LVDS for example) mode. It is recommended to use a differential sinewave signal (0 dBm or 894 mVp-p differential) centered on 0V common mode to drive the clock signals. A balun (with Sqrt(2) ratio) may then be necessary to convert the single-ended clock signal to a differential clock signal. Note: 46 If the clock frequency is fixed, then it is recommended to narrow-band filter the clock signal in order to minimize its jitter and the integrated noise over the band of interest. AT84AS004 5431B-BDC-01/06 AT84AS004 Figure 11-6. AT84AS004 Clock Input Termination Scheme (Single-ended) AT84AS004 Single - ended signal Full-scale amplitude = 0 dBm = 632 mVp-p CLK (H27) Centered on 0V common mode CLK 316 mV 50 Line 632 mV CLKN 50 - 316 mV CLKN (J27) GND Figure 11-7. AT84AS004 Clock Input Recommended Termination Scheme (Differential) AT84AS004 Differential signal Full-scale amplitude = 0 dBm = 894 mVp - p Centered on common mode CLK (H27) 50 Line CLK CLKN 223 mV 50 Line CLKN (J27) -223 mV 11.4 LVDS Input Implementation The DAI/DAIN input data of the standalone delay cell is LVDS compatible. It is 2 x 50 differentially on-chip terminated as described in Figure 11-10. Figure 11-8. AT84AS004 LVDS Input (DAI/DAIN) Termination Scheme AT84AS004 50 Line DAI 50 Line 5 pF 50 Line 50 Line DAIN 47 5431B-BDC-01/06 11.5 LVDS Output Implementation The data (Ai/AiN...Di/DiN, AOR/AORN...DOR/DORN and DAO/DAON) and clock outputs (DR/DRN) are LVDS compatible. They have to be 100 differentially terminated as described in Figure 11-9. Figure 11-9. AT84AS004 LVDS Output Termination Scheme AT84AS004 50 Line Positive Output Signal 100 50 Line Negative Output Signal 11.6 DRRB and ASYNCRST Implementation The DRRB and ASYNCRST are required to start the device properly.DRRB is active at low level while ASYNCRST is active at high level. As it is recommended to apply both reset signals simultaneously, one possible solution is to use a differential driver so that DRRB and ASYNCRST are generated as the two signals of a differential pair. This would allow for both the simultaneous application of the signals to the device a simple way to drive both signals. An example is provided below (principle of operation). Figure 11-10. AT84AS004 DRRB and ASYNCRST Driver Scheme DRRB 1 ns Pulse Source ASYNCRST Please refer to the AT84AS004 "Reset Implementation Application Note" for more information. 48 AT84AS004 5431B-BDC-01/06 AT84AS004 12. Package Information Figure 12-1. .EBGA317 Package Outline Note: The two pads at the bottom of the EBGA package are the dice moldings and should not be soldered to the board. 49 5431B-BDC-01/06 13. Ordering Information Table 13-1. 50 Ordering Information Part Number Package Temperature Range Screening AT84AS004CTP EBGA 317 Commercial C 0C < Tamb TJ < 90C Standard AT84AS004VTP EBGA 317 Industrial V -40C < Tamb TJ < 110C Standard AT84XAS004TPY EBGA 317 RoHS Ambient AT84AS004CTPY EBGA 317 RoHS Commercial C 0C < Tamb TJ < 90C Standard Please contact your local Atmel sales office AT84AS004VTPY EBGA 317 RoHS Industrial V -40C < Tamb TJ < 110C Standard Please contact your local Atmel sales office AT84AS004TP-EB EBGA 317 Ambient Prototype Evaluation kit Prototype Comments Please contact your local Atmel sales office AT84AS004 5431B-BDC-01/06 AT84AS004 Table of Contents Features ..................................................................................................... 1 Performances ............................................................................................ 1 Screening................................................................................................... 1 Applications .............................................................................................. 1 1 Description ............................................................................................... 2 2 Block Diagram .......................................................................................... 2 3 Functional Description ............................................................................ 3 4 Specifications ........................................................................................... 5 5 4.1 Absolute Maximum Ratings .................................................................................5 4.2 Electrical Operating Characteristics ....................................................................7 4.3 Explanation of Test Levels ................................................................................12 4.4 Digital Coding ....................................................................................................13 Characterization Results ....................................................................... 14 5.1 Nominal Conditions ...........................................................................................14 5.2 Full Power Input Bandwidth ...............................................................................14 5.3 VSWR Versus Input Frequency ........................................................................15 5.4 Step Response ..................................................................................................15 5.5 Dynamic Performance Versus Sampling Frequency .........................................16 5.6 Dynamic Performance Versus Input Frequency ................................................16 5.7 Signal Spectrum ................................................................................................17 5.8 Dynamic Performance Sensitivity Versus Temperature and Power Supply ......18 5.9 Dual Tone Performance ....................................................................................19 5.10 NPR Performance .............................................................................................19 6 Pin Description ....................................................................................... 20 7 Main Features ......................................................................................... 24 7.1 Reset .................................................................................................................24 7.2 Control Signal Settings ......................................................................................25 7.3 Programmable DMUX Ratio ..............................................................................27 7.4 Output Mode (STAGG) ......................................................................................27 7.5 Additional Bit .....................................................................................................29 7.6 Output Clock Type Selection .............................................................................30 i xxxxxA-BDC-01/05 7.7 Power Reduction Mode (SLEEP) ......................................................................30 7.8 Standalone Delay Cell .......................................................................................30 7.9 Clock input Delay Cell .......................................................................................31 7.10 Built-In Self Test ................................................................................................31 7.11 ADC Die Junction Temperature Monitoring .......................................................31 7.12 Pattern Generator Function ...............................................................................33 7.13A DC Gain Control ................................................................................................33 7.14 8 Equivalent Input/Output Schematics ................................................... 35 8.1 Equivalent Analog Input Circuit and ESD Protection ..........................................35 8.2 Equivalent Clock Input Circuit and ESD Protection ............................................35 8.3 Equivalent Data/Clock Output Buffer Circuit and ESD Protection ......................36 8.4 Standalone Delay Cell Data Input (DAI/DAIN) Buffer Circuit and ESD Protection 36 Delay Cell (DACTRL/DACTRLN and CLKCTRL/CLKCTRLN) Control Input Schematic and ESD Protection 37 8.5 9 Sampling Delay Adjust ......................................................................................34 8.6 DRRB Equivalent Input Schematic and ESD Protection ...................................37 8.7 ASYNCRST Equivalent Input Schematic and ESD Protection ..........................38 8.8 ADC Gain Adjust Equivalent Input Circuits and ESD Protection .......................38 8.9 B/GB and PGEB Equivalent Input Schematics and ESD Protection .................39 8.10 Control Signals Input Buffers and ESD Protection ............................................39 Definitions of Terms .............................................................................. 40 10 Thermal and Moisture Characteristics ................................................. 42 10.1 Thermal Resistance from Junction To Bottom of Balls ......................................42 10.2 Thermal Resistance from Junction To Top of Case ..........................................42 10.3 Thermal Resistance from Junction To Board ....................................................42 10.4 Thermal Resistance from Junction To Ambient .................................................43 10.5 Thermal Management Recommendations ........................................................43 10.6 Moisture Characteristics ....................................................................................44 11 Applying the AT84AS004 ...................................................................... 44 ii 11.1 Bypassing, Decoupling and Grounding .............................................................44 11.2 Analog Input Implementation .............................................................................45 11.3 Clock Input Implementation ...............................................................................46 11.4 LVDS Input Implementation ..............................................................................47 11.5 LVDS Output Implementation ............................................................................48 AT84AS004 xxxxxA-BDC-01/05 AT84AS004 11.6 DRRB and ASYNCRST Implementation ...........................................................48 12 Package Information .............................................................................. 49 13 Ordering Information ............................................................................. 50 Table of Contents....................................................................................... i iii xxxxxA-BDC-01/05 Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 Microcontrollers 2325 Orchard Parkway San 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