Features
•10-bit Resolution
•2 Gsps Sampling Rate
•Selectable 1:2 or 1:4 Demultiplexed Output
•500 mVpp Differential 100Ω or Single-ended 50Ω Analog Input
•100Ω Differential or Single-ended 50Ω Clock Input
•LVDS Output Compatibility
•Functions:
– ADC Gain Adjust
– Sampling Delay Adjust
– 1:4 Demultiplexed Simultaneous or Staggered Digital Outputs
– Data Ready Output with Asynchronous Reset
– Out-of-range Output Bit (11th Bit)
•Power Consumption: 6.5W
•Power Supplies: -5V, -2.2V, 3.3V and VPLUSD Output Power Supply
•Package
– Cavity Down EBGA 317 (Enhanced Ball Grid Array)
– 25 × 35 mm Dimensions
Performances
• 3 GHz Full Power Analog Input Bandwidth
• - 0.5 dB Gain Flatness from DC up to 1.5 GHz
• Single-tone Performance at Fs = 2 Gsps, Full First and Second Nyquist (- 1 dBFS)
– ENOB = 7.8 Effective Bits, FIN = 1000 MHz
– SNR = 51 dBc, SFDR = -55 dBc, FIN = 1000 MHz
– ENOB = 7.5 Effective Bits, FIN = 2 GHz
– SNR = 50 dBc, SFDR = -54 dBc, FIN = 2 GHz
• Dual-tone Performance (IMD3) at Fs = 2 Gsps (-7 dBFS Each Tone)
– Fin1 = 945 MHz, Fin2 = 955 MHz: IMD3 = - 60 dBFS
– Fin1 = 1545 MHz, Fin2 = 1555 MHz: IMD3 = - 60 dBFS
Screening
• Temperature Range:
–T
amb > 0°C; TJ < 90°C (Commercial C Grade)
–T
amb > - 40°C; TJ < 110°C (Industrial V Grade)
Applications
• Direct RF Down Conversion
• Broadband Digital Receivers
• Test Instrumentation
• High Speed Data Acquisition
• High Energy Physics
10-bit
2 Gsps ADC
With
1:4 DMUX
AT84AS004
5431B–BDC–01/06
2
5431B–BDC–01/06
AT84AS004
1. Description
The AT84AS004 combines a 10-bit 2 Gsps analog-to-digital converter with a 1:4 DMUX,
designed for accurate digitization of broadband signals in either first or second Nyquist zone. It
features 7.8 Effective Number of Bits (ENOB) and -55 dBFS Spurious Free Dynamic Range
(SFDR) at 2 Gsps over the full first Nyquist zone and 7.5-bit with 54 dB SFDR over full second
Nyquist.
The 1:4 demultiplexed digital outputs are LVDS logic compatible, allowing easy interfacing with
standard FPGAs or DSPs. The AT84AS004 operates at up to 2 Gsps.
The AT84AS004 comes in a 25 × 35 mm EBGA317 package. This package has the same TCE
as FR4 boards, offering excellent reliability when subjected to large thermal shocks.
2. Block Diagram
Figure 2-1. Block Diagram
VIN
VINN
CLK/CLKN
20
Port A
20
Port B
20
Port C
20
Port D
LVDS Buffers
S/H
Quantizer
Logic Block
2
Demultiplexer
1:2 or 1:4
2
DR/DRN
GA
SDA
SDA
2
AOR/AORN
2
BOR/BORN
2
COR/CORN
2
DOR/DORN
DRRB
STAGG
ASYNRST
B/GB
PGEB
SLEEP
RS
DRTYPE
BIST
3
5431B–BDC–01/06
AT84AS004
3. Functional Description
The AT84AS004 is a 10-bit 2 Gsps ADC combined with a 1:4 demultiplexer (DMUX) allowing to
lower the 11 bit output data stream (10-bit data and one out-of-range bit) by a selectable factor
of 4 or 2. The ADC works in fully differential mode from analog input through to digital outputs.
The ADC should be 50Ω reverse terminated, as close as possible to the EBGA Package input
pin (1 mm maximum). The ADC Clock input is on-chip 100Ω differentially terminated. The output
clock and the output data are LVDS logic compatible, and should be 100Ω differentially
terminated.
The AT84AS004 ADC features two asynchronous resets:
– DRRB, which ensures that the first digitized data corresponds to the first acquisition.
– ASYNCRST, which ensures that the first digitized data will be output on port A of the
DMUX.
The ADC gain can be tuned-in to unity gain by the means of the GA analog control input A Sam-
pling Delay Adjust function (SDA analog control input, activated via the SDAEN signal) may be
used to fine-tune the ADC aperture delay by ± 120 ps around its center value. The SDA function
may be of interest for interleaving multiple ADCs.The control pin B/GB is provided to select
either a binary or gray data output format.
A tunable delay cell (controlled via CLKDACTRL) is integrated between the ADC and the DMUX
on the clock path to fine tune the data vs. clock alignment at the interface between the ADC and
the DMUX. This delay can be tuned from -275 to 275 ps around default center value, featuring a
550 ps typical delay tuning range. An extra standalone delay cell is also provided, (controlled via
DACTRL analog control input and activated via DAEN). The tuning range is typically 550 ps.
A pattern generator (PGEB) is integrated in the ADC part for debug or acquisition setup. Simi-
larly, a Built-in Self Test (BIST) is provided for quick debug of the DMUX part. The output
demultiplexing 1:4 or 1:2 ratio can be selected by the means of RS digital control input.
Two modes for the output clock (via DRTYPE) can be selected:
• DR mode: only the output clock rising edge is active, the output clock rate is the same as the
output data rate
• DR/2 mode: both the output clock rising and falling edges are active, the output clock rate is
half the output data rate
The data outputs are available at the output of the AT84AS004 in two different modes:
• Staggered: even and odd bits come out with half a data period delay
• Simultaneous: even and odd bits come out at the same time
A Power reduction mode (SLEEP control input) is provided to reduce the DMUX power
consumption.
The ADC junction temperature monitoring is made possible through the DIODE input by sensing
the voltage drop across 1 diode implemented on the ADC close to chip hot point.
The AT84AS004 is delivered in an Enhanced Ball Grid Array (EBGA), very suitable for applica-
tions subjected to large thermal variations (thanks to its TCE which is similar to FR4 material
TCE).
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5431B–BDC–01/06
AT84AS004
Table 3-1. Functions Description
Name Function
VCCA Analog 3.3V power supply
VCCD Digital 3.3 V power supply
VEE Analog -5V power supply
VPLUSD Output 2.5 V power supply
VMINUSD Output -2.2V power supply
AGND Analog ground
DGND Digital ground
CLK, CLKN Input clock signals
VIN, VINN Analog input data
DRRB ADC reset
ASYNCRST DMUX asynchronous reset
DR/DRN Output clock signals
A0…A9
A0N…A9N Output data port A
AOR/DRAN,
AORN/DRA
Additional output bit port A
or output clock in staggered mode for
port A Name Function
B0…B9
B0N…B9N Output data port B DAI, DAIN Input signals for standalone delay cell
BOR/DRBN,
BORN/DRB
Additional output bit port B or output
clock in staggered mode for Port B
DAO, DAON Output signals for standalone delay
cell
GA ADC gain adjust
C0…C9
C0N…C9N Output data Port C SDAEN ADC SDA enable
SDA ADC sampling delay adjust
COR/DRCN,
CORN/DRC
Additional output bit port C
or Output clock in staggered mode for
Port C
PGEB ADC pattern generator
D0…D9
D0N…D9N Output data Port D B/GB Binary or gray output code selection
SLEEP Sleep mode selection signal
DOR/DRDN,
DORN/DRD
Additional output bit Port D or output
clock in staggered mode for Port D STAGG Staggered mode selection for data
outputs
RS DMUX ratio selection signal CLKTYPE Input clock type selection signal (to be
connected to VCCD or left floating)
CLKDACTRL Control signal for clock delay cell DRTYPE Output clock type selection signal
DACTRL Control signal for standalone delay cell BIST Built-in Self Test
DAEN Enable signal for standalone delay cell DIODE ADC Diode for die junction temperature
monitoring (ADC)
AT84AS004
2
VIN, VINN
CLK, CLKN
DRRB
DACTRL, CLKDACTRL
SLEEP
STAGG
CLKTYPE
RS
DAEN
BIST
DRTYPE
DAI, DAIN
2
2
2
[A0…A9]
[A0N…A9N]
DR, DRN
20
20
2
2
[B0…B9]
[B0N…B9N]
[C0…C9]
[C0N…C9N]
20
20 [D0…D9]
[D0N…D9N]
BOR/DRBN,
BORN/DRB
2AOR/DRAN,
AORN/DRA
2COR/DRCN,
CORN/DRC
2DOR/DRDN,
DORN/DRD
DAO, DAON
2
DIODE ADC
AGND
VCCA
3.3V VPLUSD
2.5V
VEE
-5V VCCD
3.3V
ASYNCRST
SDAEN
SDA
GA
PGEB
B/GB
DGND
VMINUSD
-2.2V
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5431B–BDC–01/06
AT84AS004
4. Specifications
4.1 Absolute Maximum Ratings
Notes: 1. Absolute maximum ratings are short term limiting values (referenced to GND = 0 V), to be applied individually, while other
parameters are within specified operating conditions. Long exposure to maximum ratings may affect device reliability.
2. All integrated circuits have to be handled with appropriate care to avoid damage due to ESD. Damage caused by inappropri-
ate handling or storage could range from performance degradation to complete failure.
Table 4-1. Absolute Maximum Ratings
Parameter Symbol Value Unit
Analog positive supply voltage VCCA GND to 6 V
Digital positive supply voltage VCCD GND to 3.6 V
Analog negative supply voltage VEE GND to - 5.5 V
Digital positive supply voltage VPLUSD GND to 3 V
Digital negative supply voltage VMINUSD GND to - 3 V
Maximum difference between
VPLUSD and VMINUSD
VPLUSD - VMINUSD 5V
Analog input voltages VIN or VINN - 1.5 to 1.5 V
Maximum difference between
VIN and VINN
VIN or VINN - 1.5 to 1.5
Clock input voltage VCLK or VCLKN -1 to 1 V
Maximum difference between
VCLK and VCLKN
VCLK - VCLKN -1 to 1 Vpp
Control input voltage GA, SDA - 1 to 0.8 V
Digital input voltage SDAEN, B/GB, PGEB, DECB - 5 to 0.8 V
ADC reset voltage DRRB -0.3 to VCCA + 0.3 V
DMUX function input voltage RS, CLKTYPE, DRTYPE, SLEEP,
STAGG, BIST, DAEN -0.3 to VCCD + 0.3 V
DMUX asynchronous reset ASYNCRST - 0.3 to VCCD + 0.3
DMUX input voltage DAI, DAIN - 0.3 to VCCD + 0.3 V
DMUX control voltage CLKDACTRL, DACTRL - 0.3 to VCCD + 0.3 V
Maximum input voltage on DIODE DIODE ADC 700 mV
Maximum input current on DIODE DIODE ADC 1 mA
Junction temperature TJ135 °C
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5431B–BDC–01/06
AT84AS004
Table 4-2. Recommended Condition of Use
Parameter Symbol Comments Recommended Value Unit
Positive supply voltage VCCA 3.3 V
Positive supply voltage VCCD 3.3 V
Negative supply voltage VEE - 5.0 V
Positive negative supply voltage VMINUSD - 2.2 V
Differential analog input voltage VIN - VINN 500 mVpp
Differential clock input level Vinclk 50Ω single-ended
(VINN grounded through 50Ω)
±125
500
mV
mVpp
Clock input power level
(ground common mode) PCLK PCLKN
50Ω single-ended clock input
or
100Ω differential clok
(recommended)
0dBm
ADC control input voltage GA, SDA - 0.5 to 0.5 V
ADC functions SDAEN, B/GB,
PGEB, DECB GND or VEE V
ADC reset DRRB GND to 3.3V V
DMUX standalone delay cell inputs DAI, DAIN GND to 3.3V V
DMUX control inputs
SLEEP, STAGG,
ASYNCRST,
BIST, RS, DAEN,
DRTYPE,
CLKDACTRL,
DACTRL
GND to 3.3V V
Operating temperature range TC; TJ
Commercial C grade industrial
V grade
0°C < TC ; TJ < 90°C
-20°C < TC; TJ < 110°C°C
Storage temperature Tstg - 65 to 150 °C
Maximum junction temperature TJ125 °C
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5431B–BDC–01/06
AT84AS004
4.2 Electrical Operating Characteristics
•V
CCA = VCCD = 3.3V, VEE = -5V, VMINUSD = -2.2V
•V
INN - VINN = 1 dBFS ( single-ended driven with VINN connected to ground via 50Ω)
•P
CLK = 0 dBm (differential driven)
Table 4-3. DC Electrical Characteristics at Ambient Temperature and Hot Temperature (TJ Max)
Parameter
Test
Level Symbol Min Typ Max Unit
Resolution 10 Bit
Power Requirements
Positive -analog
Supply -digital
Voltages -digital outputs
1
VCCA
VCCD
VPLUSD
3.15
3.15
2.4
3.3
3.3
2.5
3.45
3.45
2.6
V
V
V
-analog VCCA = 3.3V
Positive -digital VCCD = 3.3V (1:2 DMUX)
Supply -digital VCCD = 3.3V (1:4 DMUX)
Current -output VPLUSD = 2.5V
1
IVCCA
IVCCD
IVCCD
IVPLUSD
80
535
565
450
100
590
620
470
mA
mA
mA
mA
Negative supply voltage VEE
1
VEE - 5.25 - 5 - 4.75 V
Negative supply current IVEE 620 660 mA
Negative supply voltage VMINUSD - 2.3 - 2.2 - 2.1 V
Negative supply current IVMINUSD 190 200 mA
Power Dissipation (1:2 DMUX) PD6.5 7.1 W
Analog Inputs
Full-scale input voltage range
Differential mode 0V common mode voltage
4
VIN
VINN
- 125
- 125
125
125
mV
mV
Full-scale input voltage range
Single-ended input option
0V common mode voltage
VIN, VINN -250 0 250 mV
Analog input power level (50Ω single-ended) PIN -2 dBm
Analog input capacitance (die) CIN 0.3 pF
Input leakage current IIN 10 µA
-single-ended
Input resistance
-differential
4
RIN
RIN
49
98
50
100
51
102
Ω
Ω
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5431B–BDC–01/06
AT84AS004
Clock Inputs
Logic common mode
compatibility for clock inputs
4
Differential ECL to LVDS
(AC coupling)
Clock input common voltage range
(VCLK or VCLKN)
(0V common mode)
VCM - 1.2 0 0.3 V
Clock input power level
(low-phase noise sinewave input) 50Ω
single-ended or 100Ω differential
PCLK -4 0 4 dBm
Clock input swing
(single ended with CLKN = 50Ω to GND) VCLK ±200 ±320 ±500 mV
Clock input swing
(differential voltage) on each clock input VCLK, VCLKN ±141 ±226 ±354 mV
Clock input capacitance (die) CLK 0.3 pF
Clock input resistance
- Single-ended
- Differential ended
RCLK
RCLK
45
90
50
100
55
110
Ω
Ω
Digital Data Outputs
Logic compatibility LVDS
50Ω transmission lines, 100Ω (2 × 50Ω)
differential termination)
- Logic low
- Logic high
- Differential output
- Common mode
1VOL
VOH
VODIFF
VOCM
–
1.25
250
1.125
1.075
1.425
350
1.25
1.25
–
500
1.375
V
V
mV
V
Control Function Inputs
DRRB and ASYNCRST
- Logic low
- Logic high
1V
IL
VIH
0
1.6
1.0
3.3
V
V
V
RS, DRTYPE, SLEEP, STAGG, BIST, DAEN
- Logic low
- Logic high 4
VIL
RIL
VIH
RIH
0
2
10 K
0.5
10
Infinite
V
Ω
V
Ω
SDAEN, PGEB, B/GB
- Logic low
- Logic high
1V
IL
VIH -2
VEE
0
- 3
0
V
V
DAI, DAIN
- Differential input
- Common mode
1V
IDIFF
VICM
1
100
1.25
350
1.6
-
V
mV
Table 4-3. DC Electrical Characteristics at Ambient Temperature and Hot Temperature (TJ Max) (Continued)
Parameter
Test
Level Symbol Min Typ Max Unit
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5431B–BDC–01/06
AT84AS004
Note: 1. Histogram testing at Fs = 390 Msps Fin = 100 MHz.
2. This range of gain can be set to 1 thanks to the gain adjust function.
GA, SDA 1 -0.5 0.5 V
CLKDACTRL, DACTRL 1 1/3 x VCCD 2/3 x VCCD V
DC accuracy
DNLrms 1 DNLrms 0.2 0.3 LSB
Differential non-linearity (1) 1 DNL+0.8 1.5 LSB
Integral non-linearity (1) 1INL
--4 -2 LSB
Integral non-linearity (1) 1INL
+24LSB
Gain central value (2) 1 0.95 1 1.05
Gain error drift 4 23 35 ppm/°C
Input offset voltage 1 -10 10 mV
Table 4-3. DC Electrical Characteristics at Ambient Temperature and Hot Temperature (TJ Max) (Continued)
Parameter
Test
Level Symbol Min Typ Max Unit
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5431B–BDC–01/06
AT84AS004
Note: 1. See ”Definitions of Terms” on page 40.
2. From DC to 1.5 GHz.
3. Specified from DC up to 2.5 GHz input signal. Input VSWR is measured on a soldered device. It assumes an external
50Ω ± 2Ω controlled impedance line, and a 50Ω driving source impedance (S11 ≤ 30 dB).
Table 4-4. AC Electrical Characteristics at Ambient Temperature and Hot Temperature (TJ Max)
Parameter
Test
Level Symbol Min Typ Max Unit
AC Analog Inputs
Full power input bandwidth (1)
4
FPBW 3 GHz
Small signal input bandwidth (10% full-scale) (1) SSBW 3.3 GHz
Gain flatness (2) BF - 0.5 dB
Input voltage standing wave ration (3) VSWR 1.1: 1 1.2: 2
AC Performance: Nominal Condition
- 1 dBFS single-ended input mode (unless otherwise specified); 50% clock duty cycle; 0 dBm differential clock (CLK,CLKN)
binary output data format.
Effective Number of Bits
Fs = 1 Gsps Fin = 100 MHz
Fs = 1.5 Gsps Fin = 750MHz
Fs = 2 Gsps Fin = 1000 MHz
Fs = 2 Gsps Fin = 2 GHz
1
1
4
4
ENOB
7.4
7.4
7.3
7.1
8
8
7.8
7.5
Bit
Signal to Noise Ratio
Fs = 1 Gsps Fin = 100 MHz
Fs = 1.5 Gsps Fin = 750MHz
Fs = 2 Gsps Fin = 1000 MHz
Fs = 2 Gsps Fin = 2 GHz
1
1
4
4
SNR
50
49
48
48
52
52
51
50
dBc
Total Harmonic Distortion
Fs = 1 Gsps Fin = 100 MHz
Fs = 1.5 Gsps Fin = 750MHz
Fs = 2 Gsps Fin = 1000 MHz
Fs = 2 Gsps Fin = 2 GHz
1
1
4
4
|THD|
46
46
45
45
52
52
49
49
dBc
Spurious Free Dynamic Range
Fs = 1 Gsps Fin = 100 MHz
Fs = 1.5 Gsps Fin = 750MHz
Fs = 2 Gsps Fin = 1000 MHz
Fs = 2 Gsps Fin = 2 GHz
1
1
4
4
|SFDR|
50
50
48
48
58
58
55
54
dBc
Two-tone Third-order Inter-modulation Distortion
Fs = 2 Gsps
Fin1 = 945 MHz, Fin2 = 955 MHz [-7 dBFS]
Fin1 = 1545 MHz, Fin2 = 1555 MHz [- 7 dBFS]
4
4
|IMD3| 60
60
dBFS
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5431B–BDC–01/06
AT84AS004
Table 4-5. Transient and Switching Performances
Parameter
Test
Level Symbol Min Typ Max Unit
Transient Performance
Bit error rate (1) 4 BER 10-13 Error/
sample
ADC setting time (VIN-VINN = 400 mVpp) 4 TS 400 ps
Overvoltage recovery time 4 ORT 500 ps
ADC step response rise/fall time (10 - 90%) 4 80 100 ps
Overshoot 5 4 %
Ringback 5 2 %
Switching Performance and Characteristics
Maximum clock frequency (2)
4
FS Max 2 Gsps
Minimum clock frequency (2) FS Min 150 200 Msps
Maximum clock pulse width (high) TC1 0.22 2.5 ns
Minimum clock pulse width (low) TC2 0.22 2.5 ns
Aperture delay (2) TA 160 ps
Aperture uncertainty Jitter 150 fs rms
DRRB pulse width 1 ns
ASYNCRST pulse width 1 ns
Output Data
Data Output Delay (3)
4
TOD 400
Data pipeline delay
- Synchronized 1:2 ratio
- Synchronized 1:4 ratio
- Staggered 1:2 ratio
- Staggered 1:4 ratio
TPD
5.5
7.5
4.5/5.5
4.5/5.5/6.5/7.5
Clock
cycles
Data output rise/fall time (20% - 80%) TR/TF 400 ps
Output Clock
Output clock delay (3)
4
TDR 400 ps
Output clock rise/fall time (20% - 80%) TR/TF 400 ps
Output data to output clock propagation
delay TD1/TD2 0.3 0.333 500 ps
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5431B–BDC–01/06
AT84AS004
Note: 1. Output error amplitude < ±6 LSB. Fs = 2 Gsps TJ = 110°C
2. See ”Definitions of Terms” on page 40.
3. TOD and TDR propagation times are defined at package input/outputs. They are given for reference only. See”Definitions of
Terms” on page 40.
4. The delay cell used in both standalone delay cell and input clock path has a characteristic that is note linear with junction
temperature. The largest tuning range is obtained near ambient temperature.
4.3 Explanation of Test Levels
Note: Unless otherwise specified:
Only minimum and maximum values are guaranteed (typical values are issued from characterization results).
CLKDACTRL and DACTRL Delay Cells
Input frequency 4FMSDA 600 MHz
Input duty cycle DCYCSDA 40 50 60 %
Propagation delay with
CLKDACTRL or DACTRL = VCCD/3
4TSDAMIN 1.70 2.00 2.30 ns
Propagation delay
with CLKDACTRL or DACTRL = 2* VCCD/3
4TSDAMAX 2.20 2.50 2.80 ns
Tuning range (4) 4 SDARANGE 400 550 600 ps
Table 4-5. Transient and Switching Performances (Continued)
Parameter
Test
Level Symbol Min Typ Max Unit
Level Comments
1 100% production tested at 25°C (for C Temperature range ).
2100% production tested at 25°C, and sample tested at specified temperatures (for V and M temperature
ranges).
3 Sample tested only at specified temperatures
4Parameter is guaranteed by design and characterization testing (thermal steady-state conditions at specified
temperature).
5 Parameter is a typical value only guaranteed by design only
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5431B–BDC–01/06
AT84AS004
4.4 Digital Coding
Differential
Analog Input Voltage Level Digital Output
Binary (B/GB = GND or floating)
MSB…LSB out-of-range
GRAY (B/GB = VEE)
MSB………..LSB out-of-range
> 250.25 mV >Top end of full-scale + ½ LSB 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1
250.25 mV
249.75 mV
Top end of full-scale + ½ LSB
Top end of full-scale - ½ LSB
1 1 1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1 0 0
1 0 0 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 1 0
125.25 mV
124.75 mV
3/4 full-scale + ½ LSB3/4
full-scale - ½ LSB
1 1 0 0 0 0 0 0 0 0 0
1 0 1 1 1 1 1 1 1 1 0
1 0 1 0 0 0 0 0 0 0 0
1 1 1 0 0 0 0 0 0 0 0
0.25 mV
-0.25 mV
Mid scale + ½ LSB
Mid scale - ½ LSB
1 0 0 0 0 0 0 0 0 0 0
01 1 1 1 1 1 1 1 1 0
1 1 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0
- 124.75 mV
- 124.25 mV
1/4 full-scale + ½ LSB
1/4 full-scale - ½ LSB
0 1 0 0 0 0 0 0 0 0 0
0 0 1 1 1 1 1 1 1 1 0
0 1 1 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 0 0 0
- 249.75 mV
- 250.25 mV
Bottom end of full-scale + ½ LSB
Bottom end of full-scale - ½ LSB
0 0 0 0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 1 0
0 0 0 0 0 0 0 0 0 0 0
≤ 250.25 mV < Bottom end of full-scale - ½ LSB 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1
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5431B–BDC–01/06
AT84AS004
5. Characterization Results
5.1 Nominal Conditions
Unless otherwise specified:
•V
CCA = 3.3V, VCCD = 3.3V, VEE = -5V, VPLUSD = 2.5V, VMINUSD = - 2.2V
•TJ = 80°C
• 50% clock duty cycle, binary output data format
• - 1 dBFS analog input
5.2 Full Power Input Bandwidth
• Analog input level = - 1 dBFS
• Gain flatness at - 0.5 dB from DC to 1.5 GHz
Figure 5-1. Full Power Input Bandwidth at - 3 dB
-6,0
-5,5
-5,0
-4,5
-4,0
-3,5
-3,0
-2,5
-2,0
-1,5
-1,0
-0,5
0,0
100
300
500
700
900
1100
1300
1500
1700
1900
2100
2300
2500
2700
2900
3100
3300
Fin (MHz)
dBFS
-3 dB
Bandwidth
-0.5 dB Gain Flatness
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5431B–BDC–01/06
AT84AS004
5.3 VSWR Versus Input Frequency
Figure 5-2. VSWR Curve for the Analog Input (VIN) and Clock (CLK)
5.4 Step Response
• Tr measured = 114.8 ps = sqrt (TrPulseGenerator ² + TrADC²)
•Tr
PulseGenerator (estimated) = 41 ps
•Actual Tr
ADC = 107 ps
Figure 5-3. Step Response Rise Time (Fs = 2 Gsps, Fin = 1 GHz)
1,00
1,20
1,40
1,60
1,80
2,00
2,20
2,40
2,60
0 500 1000 1500 2000 2500 3000 3500
Frequency (MHz)
VSWR
CLK
VIN
-200
-100
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
0 100 200 300 400 500 600 700 800 900 1000 1100
Time (ps)
LSB
0%
100%
10%
90%
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5431B–BDC–01/06
AT84AS004
5.5 Dynamic Performance Versus Sampling Frequency
Figure 5-4. Dynamic Parameters Versus Sampling Frequency in Nyquist Conditions (Fin = Fs/2)
5.6 Dynamic Performance Versus Input Frequency
Figure 5-5. Dynamic Parameters Versus Input Frequency at Fs = 2 Gsps
0
1
2
3
4
5
6
7
8
9
10
1000 1200 1400 1600 1800 2000
Fs (Msps)
ENOB (Bit)
-90
-80
-70
-60
-50
-40
-30
-20
1000 1200 1400 1600 1800 2000
Fs (Msps)
SFDR (dBc)
Signal dependent and independent SFDR
SFDR without the first 4 Harmonics
-90
-80
-70
-60
-50
-40
-30
-20
1000 1200 1400 1600 1800 2000
Fs (Msps)
THD (dB)
20
30
40
50
60
70
80
90
1000 1200 1400 1600 1800 2000
Fs (Msps)
SNR (dB)
6
7
8
9
10
0 400 800 1200 1600 2000
Fin (MHz)
ENOB (Bit)
-90
-80
-70
-60
-50
-40
-30
-20
0 400 800 1200 1600 2000
Fin (MHz)
SFDR (dBFS)
-90
-80
-70
-60
-50
-40
-30
-20
0 400 800 1200 1600 2000
Fin (MHz)
THD (dBFS)
40
42
44
46
48
50
52
54
56
58
60
0 400 800 1200 1600 2 000
Fin (MHz)
SNR (dBFS)
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5431B–BDC–01/06
AT84AS004
5.7 Signal Spectrum
Figure 5-6. Fs = 2 Gsps, Fin = 998 MHz - 1 dBFS Analog Input, 1:4 Demultiplexing Factor,
32 kpoint FFT
Figure 5-7. Fs = 2 Gsps, Fin = 1998 MHz - 1 dBFS Analog Input, 1:4 Demultiplexing Factor,
32 kpoint FFT
-140
-120
-100
-80
-60
-40
-20
0
20
0 100 200 300 400 500 600 700 800 900 1000
MHz
dBc
SFDR (H2)
H1 Fundamental (998 MHz)
= - 58 dBFS
FS/4
ENOB = 7.8
-160
-140
-120
-100
-80
-60
-40
-20
0
20
0 100 200 300 400 500 600 700 800 900 1000
MHz
dBc
H1 Fundamental image (2 GHz - 1.998 GHz = 2 MHz)
SFDR (H4)
ENOB = 7.5
FS/4
= - 58 dBFS
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5431B–BDC–01/06
AT84AS004
5.8 Dynamic Performance Sensitivity Versus Temperature and Power Supply
Figure 5-8. Dynamic Parameters Versus Junction Temperature at Fs = 2 Gsps, Fin = 998 MHz,
- 1 dBFS Analog Input
Figure 5-9. Dynamic Parameters at Min., Typ. and Max. Power Supplies, Fs = 2 Gsps, Fin = 998 MHz,
- 1 dBFS Analog Input
Note: Minimum power supplies: VCC = 3.45,V VEE = - 4.75V
Typical power supplies: VCC = 3.3V, VEE = - 5V
Maximum power supplies: VCC = 3.15V, VEE = - 5.25V
2
3
4
5
6
7
8
9
10
10 20 30 40 50 60 70 80 90 100 110
Tj (˚C)
ENOB (Bit)
-90
-80
-70
-60
-50
-40
-30
-20
10 20 30 40 50 60 70 80 90 100 110
Tj (˚C)
SFDR (dBc
-90
-80
-70
-60
-50
-40
-30
-20
10 20 30 40 50 60 70 80 90 100 110
Tj (˚C)
THD (dB)
20
30
40
50
60
70
80
90
10 20 30 40 50 60 70 80 90 100 110
Tj (˚C)
SNR (d
B
2
3
4
5
6
7
8
9
10
Min. Power Supplies Typ. Power Supplies Max. Power Supplies
ENOB (Bit)
-70
-68
-66
-64
-62
-60
-58
-56
-54
-52
-50
-48
-46
-44
-42
-40
Min. Power Supplies Typ. Power Supplies Max. Power Supplies
SFDR (dBc)
-70
-68
-66
-64
-62
-60
-58
-56
-54
-52
-50
-48
-46
-44
-42
-40
Min. Power Supplies Typ. Power Supplies Max. Power Supplies
THD (dB)
40
42
44
46
48
50
52
54
56
58
60
Min. Power Supplies Typ. Power Supplies Max. Power Supplies
SNR (dB)
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5431B–BDC–01/06
AT84AS004
5.9 Dual Tone Performance
Figure 5-10. Dual Tone Signal Spectrum at Fs = 2 Gsps, Fin1 = 1545 MHz,
Fin2 = 1555 MHz (- 7 dBFS)
5.10 NPR Performance
Figure 5-11. Digitizing of 575 MHz Broadband Pattern at 1.4 Gsps, 25 MHz Notch Centered
Around 290 MHz, - 12 dBFS Loading Factor
-160
-140
-120
-100
-80
-60
-40
-20
0
20
0 100 200 300 400 500 600 700 800 900 1000
MHz
dBFS
F2 =Fs - Fin2 = 445 MHz
-7 dBFS
F1 = Fs - Fin1 = 455 MHz
-7 dBFS
IMD3
2F2 - F1
= 465 Mz
2F1 - Fin2
= 435 MHz
F1 + F2
= 900 Mz
-120
-100
-80
-60
-40
-20
0
0 50 100 150 200 250 300 350 400 450 500 550 600 650 700
F(MHz)
dB
25MHz
NPR = 40.22 dB
Filter roll-off
25MHz
Input antiliasing
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5431B–BDC–01/06
AT84AS004
6. Pin Description
Figure 6-1. EBGA317 Pinout Table (View from Bottom Package)
SLEEP A0N A1N A2N A3N A4N A5N A6N A7N A8N A9N B0N B1N B2N B3N
B4N
B0 B1 B2 B3
ASYNCRST AO A1 A2 A3 A4 A5 A6 A7 A8 A9
VPLUSD VPLUSD VCCD VPLUSD VCCD VPLUSD VCCD VPLUSD VPLUSD VPLUSD VCCD B4 B5N
B6NB5
VCCDVCCD
VPLUSD
VPLUSD
VCCD
VPLUSD
VCCD
VPLUSD
VPLUSD VCCD
VCCD
VCCDVCCD
VCCD
DAON
VCCD
VPLUSD B6 B7N
B7 B8N
B8 B9N
B9
VPLUSD VPLUSD DR
VCCD DRN DRTYPE
VPLUSD VPLUSD RS C0N
C0 C1N
VPLUSD VPLUSD C1 C2N
C2 C3N
VPLUSD VPLUSD C3 C4N
VCCD VCCD VCCD VCCD VCCD VCCD
VCCD VCCD VCCD VCCD
CLKDACTRL
DAI
CLKTYPE
DACTRL DAEN
BIST
VCCD
DOR
D9N
D9
VPLUSD
VPLUSD
D8
D8N D7N
D7
VPLUSD
VPLUSD VCCD
D6
D6N D5N
D5
VPLUSD
VPLUSD
D4
D4N D3N
D3
VPLUSD
VPLUSD
D2
D2N D1N
D1
VPLUSD
VPLUSD VPLUSD
D0
D0N
VPLUSD
C9N
C9
VPLUSD
C8
C8N C7N
C7
C5
C4 C5N
C6N
C6
DA1N
DA0
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VEE
VPLUSD
VPLUSD
VPLUSD
VPLUSD
CLK
VEE VEE
VEE VEE
B/GB
SUBVCCD
GA
SUB
VIN
VIN
VEE
VEE
VPLUSD
VPLUSD
VCCD
VCCA VCCA
VCCA VCCA
VCCA VCCA
VCCA VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA
VCCA VCCA
VCCA
VCCA
VCCA
VCCA
VPLUSD
SUB
VPLUSD
VPLUSD VPLUSD VPLUSD
VPLUSD VPLUSD
DRRB SDAEN
PGEB
NC
ADC
DIODE
AGND
AGND
AGND
AGND
AGNDAGNDAGND
DGND
DGND
AGND AGND AGND
AGNDAGND
AGND AGND
AGND
AGND
AGND
AGND AGND AGND AGND AGND
AGND
AGNDAGNDAGNDAGND
AGND AGND AGND AGND AGND
AGND AGND AGND AGND
AGND
AGNDAGND
DGND DGND
DGND DGND
DGND DGND
DGND DGND
DGND DGND
NC
NC
DGND
DGND
STAGG
AGND
AGND
AGND
AGND
AGND
SDA
CLKN
VEE VEE
VEE
AGND
AGND
AGND
AGND
AGND VINN
VINN
DGND
DGND
VMINUSD
VMINUSD
VMINUSD
VMINUSD
VMINUSD
VMINUSD
VMINUSDVMINUSD
/
DRDN
DRD
/
DORN
DRC
/
CORN
DRCN
/
COR
DRB
/
BORN
DRBN
/
BOR
DRA
/
AORN
DRAN
/
AOR
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5431B–BDC–01/06
AT84AS004
Table 6-1. Pin Description
Symbol Pin Number Function
Power Supplies
DGND C17, C18, D17, D18, F3, F4, H3, H4, M3,
M4, P3, P4, R18, T18, U16, U17 Digital ground
AGND
B21, B23, C21, C23, D21, D23, E21, E23,
F21, F23, F26, F27, G25, G26, G27, H25,
H26, J25, J26, K27, N25, P25, R22, R23,
R24, R25, R26, R27, T22, t23, T24, T25,
T26, T27, U22, U23, U24, U25, U26, U27,
V21, V23, V24, V26, V27, W22, W25,
W26, W27
Analog ground
VCCA
A24, A26, A27, B24, B26, B27, C24, C26,
C27, D24, D26, D27, E24, E26, F25, L25,
L26, M27, R21, T21, U21,
ADC analog positive power supply
VEE
A25, B22, B25, C20, C22, C25, D20, D22,
D25, E20; E22, E25, F20, F22, F24, K25,
K26, L27, M25, M26, N26, N27, R20, T20
ADC analog negative power supply
SUB D14, D15, R17 Connect to VEE
VPLUSD
C4, C5, C6, C7, C9, C11, C13, C14, C15,
C16, C19, D5, D6, D7, D9, D11, D13,
D19, E3, E19, F19, J3, J4, L3, L4, N3, N4,
R3, R4, R19, T6, T7, T9, T11, T13, T14,
T15, T19, U4, U5, U6, U7, U9, U11, U13,
U14, U15
ADC and DMUX output power supply
VCCD
C3, C8, C10, C12, D3, D4, D8, D10, D12,
D16, E4, E17, G3, G4, K3, K4, R16, T3,
T4, T5, T8, T10, T12, T16, T17, U3, U8,
U10, U12
DMUX digital power supply
VMINUSD A19, A20, B19, B20, E18, F18, U19, U20 ADC digital negative power supply (-2.2V)
Inputs
CLK, CLKN H27, J27 ADC clock differential Inputs
ECL/PECL/LVDS compatible
VIN V25, W24
ADC in-phase analog input (double pin:
one of the two has to be terminated via
50Ω to ground)
VINN V22, W23
ADC Inverted-phase analog input (double
pin: one of the two has to be terminated
via 50Ω to ground)
Outputs
A0…A9 B16, B15, B14, B13, B12, B11, B10, B9,
B8, B7
In-phase digital outputs port A
LVDS compatible
A0N…A9N A16, A15, A14, A13, A12, A11, A10, A9,
A8, A7
Inverted-phase digital outputs port A
LVDS compatible
AOR/DRAN, AORN/DRA B6, A6 Port additional bit or port A output clock in
staggered mode
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5431B–BDC–01/06
AT84AS004
B0…B9 B5, B4, B3, B2, C2, D2, E2, F2, G2, H2 In-phase digital outputs port B
LVDS compatible
B0N…B9N A5, A4, A3, A2, B1, C1, D1, E1, F1, G1 Inverted-phase digital outputs port B
LVDS compatible
BOR/DRBN, BORN/DRB J2, H1 Port B additional bit or port B output clock
in staggered mode
C0…C9 M2, N2, P2, R2, T2, U2, V1, V2, V3, V4 In-phase digital outputs port C
LVDS compatible
C0N…C9N L1, M1, N1, P1, R1, T1, U1, W2, W3, W4 Inverted-phase digital outputs port C
LVDS compatible
COR/DRCN, CORN/DRC V5, W5 Port C additional bit or port V output clock
in staggered mode
D0…D9 V6, V7, V8, V9, V10, V11, V12, V13, V14,
V15
In-phase digital outputs port D
LVDS compatible
D0N…D9N W6, W7, W8, W9, W10, W11, W12, W13,
W14, W15
Inverted-phase digital outputs port D
LVDS compatible
DOR/DRDN, DORN/DRD V16, W16 Port D additional bit or port D output clock
in staggered mode
DR, DRN J1, K2 Differential output clock LVDS compatible
Control Functions Inputs
DRRB P27 ADC data ready reset LVCMOS (3.3V)
compatible
ASYNCRST B17
DMUX asynchronous reset
-Leave floating or connect to VCCD for
normal mode
-Connect to ground for reset mode
SDAEN P26
ADC sampling delay adjust enable
-SDA disabled when left floating or
connected to ground
-SDA enabled when connected to VEE
SDA E27 ADC sampling delay adjust
(± 0.5V range)
PGEB A23
Pattern generator enable
-Leave floating or connect to ground for
normal mode
-Connect to VEE for test mode
B/GB A21
Binary or gray output coding selection
-Leave floating or connect to ground for
binary coding
-Connect to VEE for gray coding
GA W21 ADC gain adjust control pin (± 0.5V range)
CLKTYPE V18 Connect to VCCD
Table 6-1. Pin Description (Continued)
Symbol Pin Number Function
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5431B–BDC–01/06
AT84AS004
SLEEP A18
DMUX SLEEP mode Enable
-leave floating or connect to VCCD for
normal mode
-connect to ground for SLEEP mode
STAGG A17
DMUX staggered mode enable
-leave floating or connect to VCCD for
normal mode
-connect to ground for STAGG mode
DRTYPE K1
DMUX output clock mode selection
-connect to ground for DR/2 type
-leave floating or connect to VCCD for
DR type
RS L2
DMUX Ratio mode selection
-connect to ground for 1:2 ratio
-leave floating or connect to VCCD for
1:4 ratio
BIST V17
DMUX BIST mode
-leave floating or connect to VCCD for
normal mode
-connect to ground for BIST mode
CLKDACTRL U18 DMUX clock delay control
(from 1/3 x VCCD to 2/3 x VCCD)
DACTRL W18 Standalone delay cell control (from 1/3 x
VCCD to 2/3 x VCCD)
DAEN W17
Standalone delay cell enable
-delay cell disabled when left floating or
connected to VCCD
-delay cell enabled when connected to
ground
DAI, DAIN W19, V19 Standalone delay cell differential inputs
LVDS compatible
Control Functions Outputs
DAO, DAON W20, V20 Standalone delay cell differential outputs
LVDS compatible
DIODE ADC A22 ADC die junction temperature monitoring
NC A1, B18, W1 No connect (leave this pin floating)
Table 6-1. Pin Description (Continued)
Symbol Pin Number Function
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5431B–BDC–01/06
AT84AS004
7. Main Features
7.1 Reset
There are two reset signals available: DRRB and ASYNCRST. DRRB is active low while ASYN-
CRST is active high. These reset signals are required to start the device properly. It is
recommended to apply both reset signals simultaneously. Please refer to the Application Sec-
tion for more information on how to implement the reset functions. In the case of multiple
channels, it is recommended to hold the input clock signal low during reset (as described in
Figure 7-1) to ensure synchronization of the channels.
The DRRB/ASYNCRST signal frequency should be 200 MHz maximum. The reset pulse should
be 1 ns minimum.
Figure 7-1. Asynchronous Reset Timing Diagram, 1:2 Mode, Simultaneous Mode (Principle of Operation)
DRRB
VIN
1 ns min
CLK
N
TA = 160 ps
A0…A9
B0…B9
TOD + 5.5 cycles
N
N + 1
DR
(DR mode)
DR
(DR/2 mode)
N + 2
N + 3
N + 4
N + 5
ASYNCRST
1 ns min
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5431B–BDC–01/06
AT84AS004
Figure 7-2. Asynchronous Reset Timing Diagram, 1:4 Mode, Simultaneous Mode (Principle of Operation)
7.2 Control Signal Settings
The SLEEP, RS, DAEN, STAGG, BIST and DRTYPE control signals use the same static buffer.
ASYNCRST is activated on logic high (tied/switched to VCCD = 3.3V, or 10 kΩ to ground, or left
floating) and deactivated on logic low (grounded).
SLEEP, DAEN, STAGG, BIST are activated on logic low (10Ω grounded), and deactivated on
logic high (10 KΩ to ground, or tied to VCCD = 3.3V, or left floating).
This is illustrated in Figure 7-3.
Figure 7-3. Control Signal Setting
DRRB
A0…A9
B0…B9
C0…C9
D0…D9
VIN
1 ns min
DR
(DR mode)
CLK
DR
(DR/2 mode)
N
TA = 160 ps
TOD + 7.5 cycles
N
N + 1
N + 2
N + 3
ASYNCRST
1 ns min
10Ω 10
KΩ
GND GND
Control signal Control signal Control signal
Not
connected
Low level
(‘0’)
High level
(‘1’)
pin pin
pin
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5431B–BDC–01/06
AT84AS004
Table 7-1. DMUX Mode Settings - Summary
Function Logic Level Electrical Level Description
BIST
010Ω to ground BIST
110 kΩ to ground Normal conversion
N/C
SLEEP
010Ω to ground Power reduction mode (the outputs
are fixed at an arbitrary LVDS level)
110Ω to ground Normal conversion
N/C
STAGG
010Ω to ground Staggered mode
110 kΩ to ground Simultaneous mode
N/C
DAEN
010Ω to ground Standalone delay adjust activated
110 kΩ to ground Standalone delay adjust disabled
N/C
RS
010Ω to ground 1:2 ratio
110 kΩ to ground 1:4 ratio
N/C
ASYNCRST
010Ω to ground Normal conversion
110 kΩ to ground Reset
N/C
DRTYPE
010Ω to ground DR/2 mode
110 kΩ to ground DR mode
N/C
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5431B–BDC–01/06
AT84AS004
7.3 Programmable DMUX Ratio
The demultiplexer ratio is programmable thanks to the RS ratio selection signal:
Figure 7-4. DMUX in 1:2 Ratio
Figure 7-5. DMUX in 1:4 Ratio
7.4 Output Mode (STAGG)
Two output mode are provided:
• Staggered: the output data come out of the DMUX the one after the other;
• Simultaneous: the output data come out of the DMUX at the same time.
In staggered mode, the output clock for each port is provided by the DRA, DRAN, DRB, DRBN,
DRC, DRCN and DRD, DRDN signals which corresponds respectively to the AORN, AOR,
BRON, BOR, CORN, COR, DORN and DOR.
The simultaneous mode is the default mode (STAGG left floating of at logic 1).
The staggered mode is activated by the means of the STAGG input (active low).
RS DMUX Ratio
01:2
11:4
Input Words:
1, 2, 3, 4, 5, 6, 7, 8…
1:2
Output Words:
Port A135…
Port B 2 4
Port C Not Used
Port D Not Used
Input Words:
1, 2, 3, 4, 5, 6, 7, 8…
1:4
Output Words:
Port A 1 5 9 …
Port B 2 6
Port C 3 7
Port D 4 8
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5431B–BDC–01/06
AT84AS004
Figure 7-6. Simultaneous Mode in 1:4 Ratio (STAGG = 1)
Figure 7-7. Staggered Mode in 1:2 Ratio (STAGG = 0)
DR
(in DR mode)
Data Out
Port A
DR
(in DR/2 mode)
Data Out
Port B
Data Out
Port C
Data Out
Port D
N
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
DRB
in DR mode
Data Out
Port A
DRB (BORN)
in DR/2 mode
Data Out
Port B
N
N + 1
N + 2
N + 3-N 1
DRA
in DR mode
DRA (AORN)
in DR/2 mode
DR
(in DR mode)
DR
(in DR/2 mode)
(AORN)
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5431B–BDC–01/06
AT84AS004
Figure 7-8. Staggered Mode in 1:4 Ratio (STAGG = 0)
7.5 Additional Bit
In simultaneous output mode:
The (AOR/DRAN, AORN/DRA), (BOR/DRBN, BORN/DRB), (COR/DRCN, CORN/DRC) and
(DOR/DRDN, DORN/DRD) signals are used to process the out-of-range bit from the ADC as the
ADC output data.
In 1:2 ratio, (AOR, AORN) and (BOR, BORN) will output this signal at half its initial speed.
In 1:4 ratio, (AOR, AORN), (BOR, BORN), (COR, CORN) and (DOR, DORN) will output this sig-
nal at ¼ of its initial speed.
In Staggered output mode: (AOR/DRAN, AORN/DRA), (BOR/DRBN, BORN/DRB),
(COR/DRCN, CORN/DRC) and (DOR/DRDN, DORN/DRD) will output a Data Ready signal for
each ports, centered on the corresponding data.
NN + 4
N + 1 N + 5
-
N 2
-N 1
N + 2
N + 3
N + 6
Data Out Port A
DRA (AORN)
in DR mode
Data Out Port B
DRA (AORN)
in DR/2 mode
DRB (BORN)
in DR mode
DRB (BORN)
in DR/2 mode
Data Out Port C
DRC (CORN
(in DR mode)
DRC (CORN
(in DR/2 mode)
Data Out Port D
DRD (DORN)
in DR mode
DRD (DORN)
in DR/2 mode
DR
in DR mode
DR
in DR/2 mode
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5431B–BDC–01/06
AT84AS004
The frequency of the (DRA, DRAN), (DRB, DRBN), (DRC, DRCN) and (DRD, DRDN) depends
on the DRTYPE mode (same as data in DR mode, half in DR/2 mode).
In 1:2 ratio, DR/DRN and DRB/DRBN are the same.
In 1:4 ratio, DR/DRN and DRD/DRDN are the same.
7.6 Output Clock Type Selection
Two modes for the output clock type can be chosen:
• DR mode: only the output clock rising edge is active, the output clock rate is the same as the
output data rate;
• DR/2 mode: both the output clock rising and falling edges are active, the output clock rate is
half the output data rate.
This is illustrated in Figure 7-9 and Figure 7-10.
Figure 7-9. DR Mode
Figure 7-10. DR/2 Mode
When DRTYPE is left floating, the default mode is DR.
7.7 Power Reduction Mode (SLEEP)
The power reduction (SLEEP) mode allows the user to reduce the power consumption of the
device (demultiplexing part in Sleep mode). In this mode, the device's consumption is reduced to
5W. The Power reduction mode is active when SLEEP is low. The device is in normal mode
when SLEEP is high.
7.8 Standalone Delay Cell
A standalone delay cell is provided to allow the user to add a delay on the DAI/DAIN differential
input signal. The delay is controlled via the DACTRL. The tuning range is about 550 ps varying
from VCCD / 3 to (2 x VCCD) / 3. This function results in a delayed output signal: DAO/DAON. The
DAI/DAIN and DAO/DAON are LVDS signals.
Table 7-2. Table 8. DMUX Output Clock Type Selection Settings
DRTYPE DMUX Output Clock Type
1DR
0DR/2
DR
Data Out
DR
Data Out
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5431B–BDC–01/06
AT84AS004
Figure 7-11. Standalone Delay Cell Block Diagram
7.9 Clock input Delay Cell
A delay cell is provided to allow the user to tune the delay between clock and data at the
DEMUX input. The delay is controlled via the CLKDACTRL. It ranges from -275 ps to 275 ps for
CLKDACTRL varying from VCCD / 3 to (2 x VCCD) / 3.
This function results in a delayed internal clock signal.
Figure 7-12. Standalone Delay Cell Block Diagram
7.10 Built-In Self Test
The Built-in Self Test allows to test rapidly the DMUX block of the device. It is activated via the
BIST bit (active low). When this signal is left floating, the BIST is inactive.
When in BIST mode, a clock must be applied to the device, which can be set to 1:2 or 1:4 mode.
The output clock mode DRTYPE can be either DR or DR/2. In the BIST mode, all the bits are
either all at low or high level (even and odd bits are in phase opposition) and transition every
new cycle. For proper operation of the Built-In Self Test, VCCD should be set to 3.3V minimum.
7.11 ADC Die Junction Temperature Monitoring
A die junction temperature measurement setting is available, for maximum junction temperature
monitoring (hot point measurement). The measurement method consists in forcing a 1 mA cur-
rent into a diode mounted transistor and sensing the voltage across the DIODE pin and the
closest available ground pin. The measurement setup is described in Figure 7-13 on page 32.
DAI/DAIN
DACTRL
DAO/DAON
22
Delay
(550 ps)
CLK/CLKNInternal clock
signal
22
Delay
(-275 to 275 ps)
CLKDACTRL
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5431B–BDC–01/06
AT84AS004
Figure 7-13. ADC Diode for Die Junction Temperature Monitoring Setup (10 in parallel of 3)
Caution:
Respect the current source polarity.
In all cases, make sure that the maximum voltage compliance of the current source is limited to
a maximum of 1V or use a resistor mounted in series with the current source to avoid damages,
which may occur to the transistor device (this may occur for instance if the current source is con-
nected in reverse).
The diode VBE forward voltage versus junction temperature (in steady state conditions) charac-
teristic is given in Figure 7-14. The forward voltage drop, (VDIODE) across diode component,
versus junction temperature , (including chip parasitic resistance) , is given below (IDIODE =
1 mA).
1 mA
AGND
DIODE
Protection
Diodes
10
protection
diodes
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5431B–BDC–01/06
AT84AS004
Figure 7-14. ADC DIODE Characteristic (I = 1 mA)
Note: The operating die junction temperature must be kept below 125°C, to ensure long term device
reliability.
7.12 Pattern Generator Function
The Pattern Generator function (enabled by connecting pin PGEB to ECL low or to VEE = -5V)
allows to check rapidly the ADC operation thanks to a checker board pattern delivered internally
to the ADC. Each output bit of the ADC should toggle from 0 to 1 successively. At the
AT84AS004 output, all bits of each port are all 1 or all 0 and transition every cycle.
7.13 ADC Gain Control
The ADC gain is adjustable by the means of the pin W21 of the EBGA package.
The gain adjust transfer function is given below:
740
750
760
770
780
790
800
810
820
830
840
850
860
870
880
890
900
910
920
930
940
950
-20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130
Jonction temperature (˚C)
Diode voltage (mV)
Junction temperature Versus Diode Voltage for I= 1 mA
0.50
0.60
0.70
0.80
0.90
1.00
1.10
1.20
1.30
-0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5
VGA Gain Adjust Voltage (V)
ADC Gain
Min
Typical
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5431B–BDC–01/06
AT84AS004
7.14 Sampling Delay Adjust
Sampling delay adjust (SDA pin) allows to fine tune the sampling ADC aperture delay TAD
around its nominal value (160ps). This functionality is enabled thanks to the SDAEN signal,
which is active when tied to VEE and inactive when tied to GND
This feature is particularly interesting for interleaving ADCs to increase sampling rate.The varia-
tion of the delay around its nominal value as a function of the SDA voltage is shown in the
following graph (simulation result):
Figure 7-15. Typical Tuning Range is ± 120 ps for Applied Control Voltage Varying Between -
0.5 V to 0.5 V on SDA pin.
Note: The variation of the delay in function of the temperature is negligible.
400 p
300 p
200 p
100 p
-500 m -400 m -300 m -200 m -100 m 0.00 100 m 200 m 300 m 400 m 500 m
Delay in the Variable Delay Cell at 60 C
SDA Voltage
Delay(s)
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5431B–BDC–01/06
AT84AS004
8. Equivalent Input/Output Schematics
8.1 Equivalent Analog Input Circuit and ESD Protection
Figure 8-1. AT8AS004 Analog Input Buffer Schematic (VIN/VINN)
Note: External 50Ω reverse termination are required.
8.2 Equivalent Clock Input Circuit and ESD Protection
Figure 8-2. AT84AS004 Clock Input Buffer Schematic (CLK/CLKN)
Note: The 100Ω termination mid point is on chip and AC coupled to ground through a 40 pF capacitor.
1mA
1mA
Die Double Pads
VIN
VINN
Package
Pins
ESD
120fF
VEE = - 5V
1.5V
VEE = - 5V
ESD
120fF
50Ω Controlled
Transmission Lines
(Bonding + Package + Ball)
50Ω Controlled
Transmission Lines
(Bonding + Package + Ball)
50Ω
Double Pad
260fF
50Ω
GND
GND
50Ω
VEE = -5V
VEE =
40pF
400 µA
VEE =
ESD
120fF
ESD
215fF
ESD
120fF
CLK
CLKB
GND
VEE = -5V
Double Pad
260fF
Double Pad
260fF
Double Pad
260fP
-5V
50Ω
150Ω
400 µA
-5V
150Ω
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AT84AS004
8.3 Equivalent Data/Clock Output Buffer Circuit and ESD Protection
Figure 8-3. AT84AS004 Data (Ai/AiN…Di/DiN), Clock (DR/DRN) and DAO/DAON Output
Buffer Schematic
8.4 Standalone Delay Cell Data Input (DAI/DAIN) Buffer Circuit and ESD Protection
Figure 8-4. AT84AS004 Standalone Delay Cell Input DAI/DAIN Buffer Schematic
ESD:
gnddiode
C = 272 fF
gnddiode
ESD:
gnddiode
C = 272 fF
gnddiode
vccdiode
ESD:
vccdiode
C = 435 fF
vccdiode
ESD:
vccdiode
C = 435 fF
VPLUSD (2.5V ± 5%)
701 701
200
1.1K 1.4K 1.4K
50.0
361 361
out
outn
DGND (0V)
SUBST (-5V)
in
inb
ESD:
vccdiode
C = 435 fF
VCCD (3.3V ± 5%)
npn npn
2.00K 2.00K
4.00k
DGND (0V)
SUBST (-5V)
5.00p
ESD:
gnddiode
C = 272fF
ESD:
gnddiode
C = 272fF
49.9
49.9
1.25V ± 0.175V
1.25V ± 0.175V
ESD:
vccdiode
C = 435 fF
200200
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5431B–BDC–01/06
AT84AS004
8.5 Delay Cell (DACTRL/DACTRLN and CLKCTRL/CLKCTRLN) Control Input
Schematic and ESD Protection
Figure 8-5. AT84AS004 Delay Cell Control Input DACTRL/DACTRLN and CLKCTRL/CLKC-
TRLN Buffer Schematic
8.6 DRRB Equivalent Input Schematic and ESD Protection
Figure 8-6. AT84AS004 DRRB Reset Input Buffer Schematic
10.0K 2.00K 2.00K
DGND (0V)
10.0K 2.00K2.00K
ESD:
gnddiode
C = 272 fF
SUBST
in
ESD:
vccdiode
C = 435 fF
VCCD (3.3V ± 5%)
698 698
2.00K 2.00K
600 µa
200
Ω
8 K
10 K
130 fF
GNDVEE = -5V
DRRB
VCC = 3.3V VCC = 3.3V
GND
5 K
GND
VEE = -5V
5 K
VCC = 3.3V
1.4V
-2.6V
Ω
Ω
Ω
Ω
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5431B–BDC–01/06
AT84AS004
8.7 ASYNCRST Equivalent Input Schematic and ESD Protection
Figure 8-7. AT84AS004 Asynchronous Reset ASYNCRST Buffer Schematic
8.8 ADC Gain Adjust Equivalent Input Circuits and ESD Protection
Figure 8-8. AT84AS004 Gain Adjust Control Input Buffer Schematic (GA)
9.32K 4.00K 4.00K
DGND (0V)
25.0K 39912.7K
ESD:
gnddiode
C = 272 fF
SUBST (-5V)
in
ESD:
vccdiode
C = 435 fF
VCCD (3.3V ± 5%)
4.00K4.00K
75 ua
399
VCC = 5 V
VEE = - 5V
1
kΩ
20Ω
GA
VEE = - 5V
ESD
75fF
ESD
65fF 0.9V 0V
100 A
10pF
PAD
130fF
GND
µ
100 A
µ
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5431B–BDC–01/06
AT84AS004
8.9 B/GB and PGEB Equivalent Input Schematics and ESD Protection
Figure 8-9. AT84AS004 B/GB and PGEB Control Buffer Schematic
8.10 Control Signals Input Buffers and ESD Protection
Figure 8-10. AT84AS004 Control Signals Buffer Schematic (RS, DRTYPE, BIST, SLEEP,
STAGG, RS, DAEN)
1kΩ
2kΩ
GND
GND
GND
B/GB
VEE = -5V VEE = - 5V
ESD
75fF
ESD
65fF
PAD
130fF
250
A
-1.3V
µ
5kΩ
250 A
µ
4.00K 1.2K 1.2K 10.0K
16.00K
ESD:
gnddiode
C = 272 fF
ESD:
vccdiode
C = 435 fF
SUBST (-5V)
DGND (0V)
VCCD (3.3V ± 5%)
200
in
10Ω = 0
10 KΩ = 1
8K 10.0K
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5431B–BDC–01/06
AT84AS004
9. Definitions of Terms
(Fs max) Maximum Sampling
Frequency Sampling frequency for which ENOB < 6bit.s
(Fs min) Minimum Sampling
frequency
Sampling frequency for which the ADC Gain has fallen by 0.5 dB with
respect to the gain reference value. Performances are not guaranteed
below this frequency.
(BER) Bit Error Rate
Probability to exceed a specified error threshold for a sample at
maximum specified sampling rate. An error code is a code that differs by
more than ± 4 LSB from the correct code.
(FPBW) Full Power Input Bandwidth
Analog input frequency at which the fundamental component in the
digitally reconstructed output waveform has fallen by 3 dB with respect
to its low frequency value (determined by FFT analysis) for input at full-
scale -1 dB (- 1 dBFS).
(SSBW) Small Signal Input
Bandwidth
Analog input frequency at which the fundamental component in the
digitally reconstructed output waveform has fallen by 3 dB with respect
to its low frequency value (determined by FFT analysis) for input at full-
scale -10 dB (- 10 dBFS).
(SINAD) Signal to Noise and
Distortion Ratio
Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below
full-scale (- 1 dBFS), to the RMS sum of all other spectral components,
including the harmonics except DC.
(SNR) Signal to Noise Ratio
Ratio expressed in dB of the RMS signal amplitude, set to 1dB below
full-scale, to the RMS sum of all other spectral components excluding
the twenty five first harmonics.
(THD) Total Harmonic Distortion
Ratio expressed in dB of the RMS sum of the first twenty five harmonic
components, to the RMS input signal amplitude, set at 1 dB below full-
scale. It may be reported in dB (i.e, related to converter -1 dB full-scale),
or in dBc (i.e, related to input signal level ).
(SFDR) Spurious Free Dynamic
Range
Ratio expressed in dB of the RMS signal amplitude, set at 1 dB below
full-scale, to the RMS value of the highest spectral component (peak
spurious spectral component). The peak spurious component may or
may not be a harmonic. It may be reported in dB (i.e., related to
converter -1 dB full-scale), or in dBc (i.e, related to input signal level ).
(ENOB) Effective Number of Bits
Where A is the actual
input amplitude and V is
the full-scale range of the
ADC under test.
(DNL) Differential Non-Linearity
The Differential Non Linearity for an output code i is the difference
between the measured step size of code i and the ideal LSB step size.
DNL (i) is expressed in LSBs. DNL is the maximum value of all DNL (i).
DNL error specification of less than 1 LSB guarantees that there are no
missing output codes and that the transfer function is monotonic.
(INL) Integral Non-Linearity
The Integral Non Linearity for an output code i is the difference between
the measured input voltage at which the transition occurs and the ideal
value of this transition. INL (i) is expressed in LSBs, and is the maximum
value of all INL (i).
(TA) Aperture Delay
Delay between the rising edge of the differential clock inputs
(CLK,CLKB) (zero crossing point), and the time at which (VIN,VINB) is
sampled.
ENOB SINAD 176⋅–20 A
FS 2⁄
--------------
log+
602⋅
-----------------------------------------------------------------------------=
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5431B–BDC–01/06
AT84AS004
(JITTER) Aperture Uncertainty Sample to sample variation in aperture delay. The voltage error due to
jitter depends on the slew rate of the signal at the sampling point.
(TS) Settling Time Time delay to achieve 0.2 % accuracy at the converter output when a
80% full-scale step function is applied to the differential analog input.
(ORT) Over Voltage Recovery
Time
Time to recover 0.2 % accuracy at the output, after a 150 % full-scale
step applied on the input is reduced to midscale.
(TOD) Digital Data Output Delay
Delay from the rising edge of the differential clock inputs (CLK,CLKB)
(zero crossing point) to the next point of change in the differential output
data (zero crossing) with specified load.
(TDR) Data Ready Output Delay
Delay from the falling edge of the differential clock inputs (CLK,CLKB)
(zero crossing point) to the next point of change in the differential output
data (zero crossing) with specified load.
(TD1) Time Delay from Data
Transition to Data Ready
General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 =
1 encoding clock period.
(TD2) Time delay from Data
Ready to Data
General expression is TD2 = TC2 + TDR - TOD with TC = TC1 + TC2 =
1 encoding clock period.
(TC) Encoding Clock Period TC1 = Minimum clock pulse width (high) TC = TC1 + TC2TC2 =
Minimum clock pulse width (low).
(TPD) Pipeline Delay
Number of clock cycles between the sampling edge of an input data and
the associated output data being made available, (not taking in account
the TOD).
(TRDR) Data Ready Reset Delay
Delay between the falling edge of the Data Ready output asynchronous
Reset signal (DDRB) and the reset to digital zero transition of the Data
Ready output signal (DR).
(TR) Rise Time Time delay for the output DATA signals to rise from 20% to 80% of delta
between low level and high level.
(TF) Fall Time Time delay for the output DATA signals to fall from 20% to 80% of delta
between low level and high level.
(PSRR) Power Supply Rejection
Ratio Ratio of input offset variation to a change in power supply voltage.
(NRZ) Non Return to Zero
When the input signal is larger than the upper bound of the ADC input
range, the output code is identical to the maximum code and the out-of-
range bit is set to logic one. When the input signal is smaller than the
lower bound of the ADC input range, the output code is identical to the
minimum code, and the out-of-range bit is set to logic one. (It is
assumed that the input signal amplitude remains within the absolute
maximum ratings).
(IMD) Inter modulation distortion The two tones inter modulation distortion (IMD) rejection is the ratio of
either input tone to the worst third order intermediation products.
(NPR) Noise Power Ratio
The NPR is measured to characterize the ADC performance in
response to broad bandwidth signals. When applying a notch-filtered
broadband white-noise signal as the input to the ADC under test, the
Noise Power Ratio is defined as the ratio of the average out-of-notch to
the average in-notch power spectral density magnitudes for the FFT
spectrum of the ADC output sample test.
(VSWR) Voltage Standing Wave
Ratio
The VSWR corresponds to the ADC input insertion loss due to input
power reflection. For example a VSWR of 1.2 corresponds to a 20 dB
return loss (i.e.. 99% power transmitted and 1% reflected).
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5431B–BDC–01/06
AT84AS004
10. Thermal and Moisture Characteristics
As there is no JEDEC standard definition for the thermal resistance applied to a multi-die device,
only the thermal resistance for each die (ADC block powered on only or DMUX block powered
on only) is provided. For easy understanding of the thermal behavior of the device, thermal data
with both devices powered on are however provided.
All results were computed with ANSYS thermal simulation tool and with the following
assumptions:
• Half geometry simulation
• DC heating zone = 1.9 x 1.9 mm²
• MUX heating 4.0 x 4.0 mm²
• No air, pure conduction, no radiation
10.1 Thermal Resistance from Junction To Bottom of Balls
When both blocks are powered on, the thermal simulation results in:
• Temperature at the center of the ADC block = 32.9°C
• Temperature at the center of the DMUX block = 13.6°C
When each block is powered on at a time, the resulting thermal resistance from junction to bot-
tom of balls is:
• Rth Junction-bottom of balls (ADC block on only) = 7°C/W
• Rth Junction-bottom of balls (DMUX block on only) = 3.9°C/W
10.2 Thermal Resistance from Junction To Top of Case
When both blocks are powered on, the resulting thermal resistance from junction to top of
case is:
• Temperature at the center of the ADC block = 18.5°C
• Temperature at the center of the DMUX block = 4.1°C
When each block is powered on at a time, the resulting thermal resistance from junction to top of
case is:
• Rth Junction- top of case (ADC block on only) = 4.1°C/W
• Rth Junction- top of case (DMUX block on only) = 1.5°C/W
10.3 Thermal Resistance from Junction To Board
When both blocks are powered on, the resulting thermal resistance from junction to board is:
• Temperature at the center of the ADC block = 57.6°C
• Temperature at the center of the DMUX block = 37.3°C
When each block is powered on at a time, the resulting thermal resistance from junction to board
is:
• Rth Junction- board (ADC block on only) = 8°C/W
• Rth Junction- board (DMUX block on only) = 4.9°C/W
Note: Assumed board size = 53 x 43 mm²
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5431B–BDC–01/06
AT84AS004
10.4 Thermal Resistance from Junction To Ambient
When both blocks are powered on, the resulting thermal resistance from junction to ambient is:
• Temperature at the center of the ADC block = 106°C
• Temperature at the center of the DMUX block = 85.3°C
When each block is powered on at a time, the resulting thermal resistance from junction to ambi-
ent is:
• Rth Junction- ambient (ADC block on only) = 17.1°C/W
• Rth Junction- ambient (DMUX block on only) = 13.9°C/W
10.5 Thermal Management Recommendations
In still air and 25°C ambient temperature conditions, the maximum temperature of 106°C + 25°C
= 131°C is reached for the ADC block. It is consequently necessary to manage the heat from the
AT84AS004 very carefully to avoid permanent damages of the device due to over temperature
operation.
In no air cooling conditions, an external heatsink must be placed on top of package. An electrical
isolation may be necessary as the top of the package is at VEE = -5V potential.
It is advised to use an external heatsink with intrinsic thermal resistance better than 4°C/Watt
when using air at room temperature 20~25°C.At 60°C, the external heatsink should have an
intrinsic thermal resistance better than 3°C/Watt.Figure 27 provides the outlines of the heat sink
used on the AT84AS004-EB evaluation board.
Figure 10-1. AT84AS004-EB Evaluation Board Heat Sink Outlines
Note: All units are in mm
10
4
2.7
60 x 52
13 x 26
50.4 x 50.7 x 16.5 heat sink
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5431B–BDC–01/06
AT84AS004
10.6 Moisture Characteristics
This device is sensitive to the moisture (MSL3 according to JEDEC standard).
Shelf life in sealed bag : 12 months at <40°C and <90% relative humidity (RH).
After this bag is opened, devices that will be subjected to infrared reflow, vapor-phase reflow, or
equivalent processing (peak package body temp. 220°C) must be :
– mounted within 168 hours at factory conditions of ≤30°C/60% RH, or
– stored at ≤20% RH
Devices require baking, before mounting, if Humidity Indicator is >20% when read at 23°C ±
5°C.
If baking is required, devices may be baked for :
– 192 hours at 40°C + 5°C/-0°C and <5% RH for low temperature device containers, or
– 24 hours at 125°C ± 5°C for high-temperature device containers.
11. Applying the AT84AS004
11.1 Bypassing, Decoupling and Grounding
All power supplies have to be decoupled to ground as close as possible to the signal accesses
to the board by 1 µF in parallel to 100 nF.
Figure 11-1. AT84AS004 Power supplies Decoupling and grounding Scheme
Note: VCCD and VCCA planes should be separated but the two power supplies can be reunited by a strap
on the board.
Each group of neighboring power supply pins attributed to the same value should be bypassed
with at least one pair of 100 pF in parallel to 10 nF capacitors. These capacitors should be
placed as close as possible to the power supply package pins.
The minimum required pairs of capacitors by power supply type is:
–10 for V
CCA
–15 for V
CCD
–11 for V
EE
–22 for V
PLUSD
–3 for V
MINUSD
External Power Supply Access
(V
CCD
, V
CCA
, V
EE
,
V
PLUSD
or V
MINUSD
)
Power Supply
Plane
Ground
1 µF 100 nF
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5431B–BDC–01/06
AT84AS004
Figure 11-2. AT84AS004 Power Supplies Bypassing Scheme
11.2 Analog Input Implementation
Two pins are available for each positive (VIN) and negative (VINN) inputs. It is necessary to ter-
minated one of each input pair by 50Ω to ground as close as possible to the EBGA package
pins. This is illustrated in Figure 30.
Figure 11-3. AT84AS004 Analog Input Reverse Termination Scheme
The analog input of the AT84AS004 device can be indifferently entered in single-ended or differ-
ential mode.
3
V
CCD
VCCA
VEE
V
MINUSD
V
PLUSD
DGND
DGND
DGND
100 pF
10 nF
100 pF
10 nF
100 pF
10 nF
100 pF
10 nF
100 pF
10 nF
X 10 (min)
X 11 (min)
X 15 (min)
X 22 (min)
X 3 (min)
V
CCA
V
CCD
AGND
AGND
AT84AS004
VIN (W24)
VINN (W23)
VIN (V25)
50Ω
GND
50
GND
VINN (V22)
AT84AS004
Differential or
single-ended signal
Lines
Ω
50Ω
46
5431B–BDC–01/06
AT84AS004
Figure 11-4. AT84AS004 Analog Input Termination Scheme (Single-ended)
Note: The two 50Ω terminations connected to the two negative inputs (VINN) can be replaced by one
25Ω resistor to ground.
Figure 11-5. AT84AS004 Analog Input Termination Scheme (Differential)
11.3 Clock Input Implementation
The AT84AS004 clock inputs (CLK/CLKN) are designed for either single-ended or differential
operation but it is recommended to drive the clock differentially to optimize the device's perfor-
mances at high frequencies. No external 50Ω termination are required for the clock inputs
(CLK/CLKN) as they are already on-chip terminated by two 50Ω resistors connected to ground
via an on-chip 40 pF capacitor.
The AT84AS004 input clock can be used in either DC coupled (0V common mode) or AC cou-
pled (ECL, LVDS for example) mode. It is recommended to use a differential sinewave signal
(0 dBm or 894 mVp-p differential) centered on 0V common mode to drive the clock signals. A
balun (with Sqrt(2) ratio) may then be necessary to convert the single-ended clock signal to a dif-
ferential clock signal.
Note: If the clock frequency is fixed, then it is recommended to narrow-band filter the clock signal in
order to minimize its jitter and the integrated noise over the band of interest.
VIN (W24)
VINN (W23)
VIN (V25)
50Ω
GND
50
GND
VINN (V22)
AT84AS004
Single ended signal
Full-scale amplitude = 500 mVp-p
Centered 0V common mode
50
500
250 mV
-250 mV
VIN
VINN
on
mVp-p
Ω
Ω
50Ω Line
VIN (W24)
VINN (W23)
VIN (V25)
GND
GND
VINN (V22)
Full-scale amplitude = 500
Centered on0V common mode
250
VIN
VI
mVp-p
50Ω
50Ω
Differential signal
mV
250
mV
AT84AS004
50Ω Lines
NN
125 mV
-125 mV
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5431B–BDC–01/06
AT84AS004
Figure 11-6. AT84AS004 Clock Input Termination Scheme (Single-ended)
Figure 11-7. AT84AS004 Clock Input Recommended Termination Scheme (Differential)
11.4 LVDS Input Implementation
The DAI/DAIN input data of the standalone delay cell is LVDS compatible. It is 2 x 50Ω differen-
tially on-chip terminated as described in Figure 11-10.
Figure 11-8. AT84AS004 LVDS Input (DAI/DAIN) Termination Scheme
CLKN (J27)
CLK (H27)
50
Ω
GND
Single-ended signal
Full-scale amplitude = 0 dBm = 632 mVp-p
Centered on 0V
common mode
632
316 mV
- 316 mV
mV
50Ω Line
CLK
CLKN
AT84AS004
CLKN (J27)
CLK (H27)
AT84AS004
50Ω Line
50Ω Line
Differential signal
Full-scale amplitude = 0 dBm = 894 mVp - p
Centered on common mode
CLK CLKN
-223 mV
223 mV
AT84AS004
DAIN
DAI
5 pF
50Ω Line
50Ω Line
50Ω Line
50Ω Line
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5431B–BDC–01/06
AT84AS004
11.5 LVDS Output Implementation
The data (Ai/AiN…Di/DiN, AOR/AORN…DOR/DORN and DAO/DAON) and clock outputs
(DR/DRN) are LVDS compatible. They have to be 100Ω differentially terminated as described in
Figure 11-9.
Figure 11-9. AT84AS004 LVDS Output Termination Scheme
11.6 DRRB and ASYNCRST Implementation
The DRRB and ASYNCRST are required to start the device properly.DRRB is active at low level
while ASYNCRST is active at high level.
As it is recommended to apply both reset signals simultaneously, one possible solution is to use
a differential driver so that DRRB and ASYNCRST are generated as the two signals of a differ-
ential pair. This would allow for both the simultaneous application of the signals to the device a
simple way to drive both signals.
An example is provided below (principle of operation).
Figure 11-10. AT84AS004 DRRB and ASYNCRST Driver Scheme
Please refer to the AT84AS004 “Reset Implementation Application Note” for more information.
AT84AS004
Positive Output Signal
Negative Output Signal
50Ω Line
50Ω Line
100Ω
DRRB
1 ns Pulse Source
ASYNCRST
49
5431B–BDC–01/06
AT84AS004
12. Package Information
Figure 12-1. .EBGA317 Package Outline
Note: The two pads at the bottom of the EBGA package are the dice moldings and should not be soldered to the board.
50
5431B–BDC–01/06
AT84AS004
13. Ordering Information
Table 13-1. Ordering Information
Part Number Package Temperature Range Screening Comments
AT84AS004CTP EBGA 317
Commercial C
0°C < Tamb
TJ < 90°C
Standard
AT84AS004VTP EBGA 317
Industrial V
-40°C < Tamb
TJ < 110°C
Standard
AT84XAS004TPY EBGA 317
RoHS Ambient Prototype Please contact
your local Atmel
sales office
AT84AS004CTPY EBGA 317
RoHS
Commercial C
0°C < Tamb
TJ < 90°C
Standard
Please contact
your local Atmel
sales office
AT84AS004VTPY EBGA 317
RoHS
Industrial V
-40°C < Tamb
TJ < 110°C
Standard
Please contact
your local Atmel
sales office
AT84AS004TP-EB EBGA 317 Ambient Prototype Evaluation kit
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AT84AS004
Table of Contents
Features ..................................................................................................... 1
Performances ............................................................................................ 1
Screening................................................................................................... 1
Applications .............................................................................................. 1
1 Description ............................................................................................... 2
2 Block Diagram .......................................................................................... 2
3 Functional Description ............................................................................ 3
4 Specifications ........................................................................................... 5
4.1 Absolute Maximum Ratings .................................................................................5
4.2 Electrical Operating Characteristics ....................................................................7
4.3 Explanation of Test Levels ................................................................................12
4.4 Digital Coding ....................................................................................................13
5 Characterization Results ....................................................................... 14
5.1 Nominal Conditions ...........................................................................................14
5.2 Full Power Input Bandwidth ...............................................................................14
5.3 VSWR Versus Input Frequency ........................................................................15
5.4 Step Response ..................................................................................................15
5.5 Dynamic Performance Versus Sampling Frequency .........................................16
5.6 Dynamic Performance Versus Input Frequency ................................................16
5.7 Signal Spectrum ................................................................................................17
5.8 Dynamic Performance Sensitivity Versus Temperature and Power Supply ......18
5.9 Dual Tone Performance ....................................................................................19
5.10 NPR Performance .............................................................................................19
6 Pin Description ....................................................................................... 20
7 Main Features ......................................................................................... 24
7.1 Reset .................................................................................................................24
7.2 Control Signal Settings ......................................................................................25
7.3 Programmable DMUX Ratio ..............................................................................27
7.4 Output Mode (STAGG) ......................................................................................27
7.5 Additional Bit .....................................................................................................29
7.6 Output Clock Type Selection .............................................................................30
ii
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AT84AS004
7.7 Power Reduction Mode (SLEEP) ......................................................................30
7.8 Standalone Delay Cell .......................................................................................30
7.9 Clock input Delay Cell .......................................................................................31
7.10 Built-In Self Test ................................................................................................31
7.11 ADC Die Junction Temperature Monitoring .......................................................31
7.12 Pattern Generator Function ...............................................................................33
7.13A DC Gain Control ................................................................................................33
7.14 Sampling Delay Adjust ......................................................................................34
8 Equivalent Input/Output Schematics ................................................... 35
8.1 Equivalent Analog Input Circuit and ESD Protection ..........................................35
8.2 Equivalent Clock Input Circuit and ESD Protection ............................................35
8.3 Equivalent Data/Clock Output Buffer Circuit and ESD Protection ......................36
8.4 Standalone Delay Cell Data Input (DAI/DAIN) Buffer Circuit and
ESD Protection 36
8.5 Delay Cell (DACTRL/DACTRLN and CLKCTRL/CLKCTRLN) Control Input
Schematic and ESD Protection 37
8.6 DRRB Equivalent Input Schematic and ESD Protection ...................................37
8.7 ASYNCRST Equivalent Input Schematic and ESD Protection ..........................38
8.8 ADC Gain Adjust Equivalent Input Circuits and ESD Protection .......................38
8.9 B/GB and PGEB Equivalent Input Schematics and ESD Protection .................39
8.10 Control Signals Input Buffers and ESD Protection ............................................39
9 Definitions of Terms .............................................................................. 40
10 Thermal and Moisture Characteristics ................................................. 42
10.1 Thermal Resistance from Junction To Bottom of Balls ......................................42
10.2 Thermal Resistance from Junction To Top of Case ..........................................42
10.3 Thermal Resistance from Junction To Board ....................................................42
10.4 Thermal Resistance from Junction To Ambient .................................................43
10.5 Thermal Management Recommendations ........................................................43
10.6 Moisture Characteristics ....................................................................................44
11 Applying the AT84AS004 ...................................................................... 44
11.1 Bypassing, Decoupling and Grounding .............................................................44
11.2 Analog Input Implementation .............................................................................45
11.3 Clock Input Implementation ...............................................................................46
11.4 LVDS Input Implementation ..............................................................................47
11.5 LVDS Output Implementation ............................................................................48
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11.6 DRRB and ASYNCRST Implementation ...........................................................48
12 Package Information .............................................................................. 49
13 Ordering Information ............................................................................. 50
Table of Contents....................................................................................... i
Printed on recycled paper.
5431B–BDC–01/05
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