© 2007 Microchip Technology Inc. DS21950D-page 15
MCP3550/1/3
4.4 Different ial Analog Inputs
The MCP3550/1/3 devices accept a fully differential
analog input voltage to be connected to the VIN+ and
VIN- input pins. The differential voltage that is converted
is define d by VIN = VIN+ – V IN-. The di f fe r en tia l vol t age
range specified for ensured accuracy is from -VREF to
+VREF.
The conv erter will output v alid an d usabl e code s from -
112% to 112% of output range (see Section 5.0
“Serial Interface”) at room temperature. The ±12%
overrange is clearly specified by two overload bits in
the outp ut code: OVH and OVL. This fe ature a llo w s for
system calibration of a positive gain error.
The absolute voltage range on these input pins extends
from VSS - 0.3V to VDD + 0.3V. If the input vo lt a ges are
above or below this range, the leakage currents of the
ESD diodes will increase exponentially, degrading the
accuracy and noise performance of the converter. The
common mode of the analog inputs should be chosen
such that both the differential analog input range and
absolute voltage range on each pin are within the
specified operating range defined in Section 1.0
“Electrical Cha racteristics”.
Both the analog differential inputs and the reference
input have switched-capacitor input structures. The
input capacitors are charged and discharged alterna-
tively with the input and the reference in order to
proc ess a conversi on. The charge and discharge of th e
input capacitors create dynamic input currents at the
VIN+ and VIN- input pins inversely proportional to the
sampling capacitor. This current is a function of the
differential input voltages and their respective common
modes. The typical value of the dif ferential input imped-
ance is 2.4 MΩ, with VCM = 2.5V, VDD = V REF = 5V. The
DC leakage current caused by the ESD input diodes,
even th ough o n the order o f 1 nA, can caus e add itiona l
offset errors proportiona l to the source resistance at the
VIN+ and VIN- input pins.
From a transient response standpoint and as a first-
order approximation, these input structures form a
simple RC fil tering c ircui t with the source imped ance i n
series with the RON (switc hed resi stance when closed)
of the input switch a nd the sampling c apacitor. In order
to ensure the accuracy of the sampled charge, proper
settling time of the input circuit has to be considered.
Slow settling of the input circuit will create additional
gain error. As a rule of thumb, in order to obtain 1 ppm
absolute measurement accuracy, the sampling period
must b e 14 ti mes greater t han the in put circuit RC tim e
constant.
4.5 Voltage Reference Input Pin
The MCP3550/1/3 devices accept a single-ended
external reference voltage, to be connected on the
VREF input pin. Internally, the reference voltage for the
ADC is a differential voltage with the non-inverting input
connected to the VREF pin and the inverting input
connected to the VSS pin. The value of the reference
voltage is VREF - VSS and the common mode of the
reference is always (VREF - VSS)/2.
The MCP3550/1/3 devices accept a single-ended
reference voltage from 0.1V to VDD. The converter
output noise is dominated by thermal noise that is
independent of the reference voltage. Therefore, the
output noise is not significantly improved by lowering
the referenc e volta ge at the VREF input pin. However, a
reduced referen ce v olt age w ill signi ficant ly impro ve th e
INL performance since the INL max error is
proportional to VREF2 (see Figure 2-4).
The charg e and di scha rge of the input c apa citor c reate
dynamic input currents at the VREF input pin inversely
proportional to the sampl ing capacitor, which is a func-
tion of the input reference voltage. The typical value of
the single-ended input impedance is 2.4 MΩ, with
VDD =V
REF = 5V. The DC leakage current caused by
the ESD input diodes, though on the order of 1 nA
typica lly , can cause additi onal gain error pr oportional to
the source resistance at the VREF pin.
4.6 Power-On Reset (POR)
The MCP3550/1/3 devices contain an internal Power-
On Reset (POR) circuit that monitors power supply
voltage VDD during operation. This circuit ensures
correct de vice st art-u p at syste m power-up and power-
down events. The POR has built-in hysteresis and a
timer to give a high degree of immunity to potential
ripple and noise on the power supplies, as well as to
allow proper settl ing of t he pow er supply durin g pow er-
up. A 0 .1 µF de coupl ing capaci tor shou ld be mount ed
as close as possible t o the VDD pin, providing additional
transient immunity.
The threshold vol t ag e is s et at 2.2V, with a tol erance of
approximately ±5%. If the supply voltage falls below
this thre shold , the MC P3550 /1/3 devic es wil l be he ld in
a reset condition or in Shutdown mode. When the part
is in Shutdown mode, the power consumption is less
than 1 µA. The typical hysteresis value is around
200 mV in order to prevent reset during brown-out or
other glitches on the power supply.