M68HC05
Microcontrollers
MC68HC705J1A/D
Rev. 4, 5/ 2002
MC68HC705J1A
MC68HRC705J1A
Technical Data
MC68HSC705J1A
MC68HSR705J1A
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MC68HC705J 1A — Rev . 4.0 Technical Data
MC68HC705J1A
MC68HRC705J1A
MC68HSC705J1A
MC68HSR705J1A
Technical Data
To provide the most up-to-date information, the revision of our
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The following revision history table summarizes changes contained in
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Technical Data MC68HC705J1A — Rev. 4.0
Technical Data
Revision History
Date Revision
Level Description Page
Number(s)
May, 2002 4.0
Figure 2-2. I/O Register S umm ary — Corrected reset state for
last entry (Mask Option Register)
37
Figure 2-4. Mask Opti on Register (MOR) — Corrected reset
state 41
6.3.3 Pulldown Register A — Corrected note 91
6.4.3 Pulldown Register B — Corrected note 94
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MC68HC705J1A —Rev. 4.0 Tec hnical Data
List of S ect ions
Technical Data — MC68HC705J1A
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . .21
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Section 3. Central Processor Unit (CPU) . . . . . . . . . . . .45
Section 4. Resets and Interrupts. . . . . . . . . . . . . . . . . . .69
Section 5. Low-Power Modes. . . . . . . . . . . . . . . . . . . . . .79
Section 6. Parallel Input/Output (I/O) Ports . . . . . . . . . .87
Sec tio n 7. Comp ut er Oper at in g Pro pe rl y
(COP) Module . . . . . . . . . . . . . . . . . . . . . . . . .97
Section 8. External Interrupt Module (IRQ). . . . . . . . . .101
Section 9. Multifunction Timer Module . . . . . . . . . . . . .109
Section 10. Electrical Specifications. . . . . . . . . . . . . . .117
Section 11. Mechanical Specifications . . . . . . . . . . . . .131
Section 12. Ordering Information . . . . . . . . . . . . . . . . .135
Appendix A. MC68HRC705J1A . . . . . . . . . . . . . . . . . . .13 7
Appendix B. MC68HSC705J1A . . . . . . . . . . . . . . . . . . .141
Appendix C. MC68HSR705J1A . . . . . . . . . . . . . . . . . . .145
Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
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Technical Data MC68HC705J1A —Rev. 4.0
List of S ect ions
Li st of Sec ti o ns
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MC68HC705J1A —Rev. 4.0 Tec hnical Data
Table of Contents
Technical Data — MC68HC705J1A
Table of Contents
Section 1. General Description
1.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.4 Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 5
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.5.1 VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.5.2 OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.5.2.1 Crysta l Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.5.2.2 Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . .28
1.5.2.3 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.5.2.4 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.6 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 0
1.7 IRQ/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.8 PA0–PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.9 PB0–PB5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Sect io n 2. M em o ry
2.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.3 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.4 Input/Output Register Summary. . . . . . . . . . . . . . . . . . . . . . . .35
2.5 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
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Technical Data MC68HC705J1A —Rev. 4.0
Table of Contents
Table of Contents
2.6 EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2.6.1 EPROM/OTPROM Programming. . . . . . . . . . . . . . . . . . . . .38
2.6.2 EPROM Programming Register . . . . . . . . . . . . . . . . . . . . .39
2.6.3 EPROM Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
2.7 Mask Option Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
2.8 EPROM Programming Characteristics. . . . . . . . . . . . . . . . . . .43
Section 3. Central Processor Unit (CPU)
3.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.3 CPU Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.4 Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.5 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 8
3.5.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.5.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.5.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.5.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.5.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.6 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
3.6.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
3.6.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
3.6.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
3.6.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.6.1.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.6.1.5 Indexed, No Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.6.1.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.6.1.7 Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . .54
3.6.1.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
3.6.2 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
3.6.2.1 Registe r/Memory Instructions . . . . . . . . . . . . . . . . . . . . .55
3.6.2.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . .56
3.6.2.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .57
3.6.2.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . .59
3.6.2.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
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Table of Contents
MC68HC705J1A —Rev. 4.0 Technical Data
Table of Contents
3.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.8 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
Sec tio n 4. Rese ts and In ter rup ts
4.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.3 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.3.1 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
4.3.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
4.3.3 COP Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
4.3.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
4.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
4.4.1 Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
4.4.2 External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
4.4.3 Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
4.4.3.1 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
4.4.3.2 Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .76
4.4.4 Interrupt Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 6
Section 5. Low-Power Modes
5.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
5.3 Exiting Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . .80
5.4 Effects of Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . .81
5.4.1 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
5.4.2 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
5.4.3 COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
5.4.4 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
5.4.5 EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
5.4.6 Data-Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
5.5 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
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Technical Data MC68HC705J1A —Rev. 4.0
Table of Contents
Table of Contents
Section 6. Parallel Input/Output (I/O) Ports
6.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
6.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
6.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 9
6.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . .90
6.3.3 Pulldown Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
6.3.4 Port A LED Drive Capability. . . . . . . . . . . . . . . . . . . . . . . . .92
6.3.5 Port A I/O Pi n Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2
6.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
6.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2
6.4.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . .93
6.4.3 Pulldown Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
6.5 5.0-Volt I/O Port Electrical Characteristics . . . . . . . . . . . . . . . .95
6.6 3.3-Volt I/O Port Electrical Characteristics . . . . . . . . . . . . . . . .95
Section 7. Computer Operating Properly
( COP) Module
7.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
7.3.1 COP Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . .98
7.3.2 COP Watchdog Timeout Period. . . . . . . . . . . . . . . . . . . . . .98
7.3.3 Clearing the COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . .9 8
7.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.5 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
7.6.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
7.6.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
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Table of Contents
MC68HC705J1A —Rev. 4.0 Technical Data
Table of Contents
Section 8 . External Interrupt Module (IRQ)
8.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
8.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
8.3.1 IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
8.3.2 Optional External Interrupts . . . . . . . . . . . . . . . . . . . . . . . .104
8.4 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .106
8.5 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
8.5.1 5.0-Volt External Interrupt Timing Characteristics . . . . . . .107
8.5.2 3.3-Volt External Interrupt Timing Characteristics . . . . . . .107
Section 9. Mu l ti fu ncti o n Ti me r Modu le
9.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
9.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
9.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
9.5 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
9.5.1 Timer Status and Control Register. . . . . . . . . . . . . . . . . . .112
9.5.2 Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . .114
9.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
9.6.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
9.6.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
Section 10. Electrical Specifications
10.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
10.3 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
10.4 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .119
10.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
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Technical Data MC68HC705J1A —Rev. 4.0
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Table of Contents
10.6 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
10.7 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .121
10.8 3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . .122
10.9 Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
10.10 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
10.11 EPROM Programming Characteristics. . . . . . . . . . . . . . . . . .126
10.12 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
10.13 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
Section 11. Mech anical Specificatio ns
11.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
11.3 Plastic Dual In-Line Package (Case 738). . . . . . . . . . . . . . . .132
11.4 Small Outline Integrated Circuit (Case 751). . . . . . . . . . . . . .132
11.5 Ceramic Dual In-Line Package (Case 732) . . . . . . . . . . . . . .133
Section 12. Ordering Information
12.1 Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
12.3 MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
Appendix A. MC68HRC705J1A
A.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
A.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
A.3 RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . .138
A.4 Typical Internal Operating Frequency
for RC Oscillator Option. . . . . . . . . . . . . . . . . . . . . . . . . . .139
A.5 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . .140
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Table of Contents
MC68HC705J1A —Rev. 4.0 Technical Data
Table of Contents
Appendix B. MC68HSC70 5J1A
B.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
B.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
B.3 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .142
B.4 3.3-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .142
B.5 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
B.6 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . .144
Appendix C. MC68HSR70 5J1A
C.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
C.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
C.3 RC Oscillator Connections (External Resistor). . . . . . . . . . . .145
C.4 Typical Internal Operating Frequency at 25°C
for High-Speed RC Oscillator Option. . . . . . . . . . . . . . . . .146
C.5 RC Oscillator Connections (No External Resistor). . . . . . . . .147
C.6 Typical Internal Operating Frequency versus Temperature
(No External Resistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
C.7 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . .149
Index
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151
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Technical Data MC68HC705J1A —Rev. 4.0
Table of Contents
Table of Contents
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MC68HC705J1A —Rev. 4.0 Tec hnical Data
List of Figures
Technical Data — MC68HC705J1A
List of Figures
Figure Title Page
1-1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
1-2 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
1-3 Bypassing Layout Recommendation . . . . . . . . . . . . . . . . . .26
1-4 Crystal Connections with
Oscillator Internal Resistor Mask Option. . . . . . . . . . . . .28
1-5 Crystal Connections without
Oscillator Internal Resistor Mask Option. . . . . . . . . . . . .28
1-6 Ceramic Resonator Connections
with Oscillator Internal Resistor Mask Option . . . . . . . . .29
1-7 Ceramic Resonator Connections
without Oscil lator Internal Resistor Mask Option. . . . . . .29
1-8 External Clock Connections. . . . . . . . . . . . . . . . . . . . . . . . .30
2-1 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2-3 EPROM Programming Register (EPROG). . . . . . . . . . . . . .39
2-4 Mask Option Register (MOR). . . . . . . . . . . . . . . . . . . . . . . .41
3-1 Programming Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
3-2 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3-3 Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3-4 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3-5 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3-6 Condition Code Register (CCR). . . . . . . . . . . . . . . . . . . . . .50
4-1 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4-2 Power-On Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . .71
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Technical Data MC68HC705J1A —Rev. 4.0
List of Figures
Li st of Figu r es
Figure Title Page
4-3 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
4-4 External Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
4-5 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . .75
4-6 Interrupt Stacking Order. . . . . . . . . . . . . . . . . . . . . . . . . . . .77
4-7 Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
5-1 Stop Mode Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . .85
5-2 Stop/Halt/Wait Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . .86
6-1 Parallel I/O Port Register Summary. . . . . . . . . . . . . . . . . . .88
6-2 Port A Data Register (PORTA). . . . . . . . . . . . . . . . . . . . . . .89
6-3 Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . .90
6-4 Port A I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
6-5 Pulldown Register A (PDRA) . . . . . . . . . . . . . . . . . . . . . . . .91
6-6 Port B Data Register (PORTB). . . . . . . . . . . . . . . . . . . . . . .92
6-7 Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . .93
6-8 Port B I/O Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
6-9 Pulldown Register B (PDRB) . . . . . . . . . . . . . . . . . . . . . . . .94
7-1 COP Register (COPR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
8-1 IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .102
8-2 Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
8-3 IRQ Status and Control Register (ISCR) . . . . . . . . . . . . . .106
8-4 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . .107
9-1 Multifunction Timer Block Diagram. . . . . . . . . . . . . . . . . . .110
9-2 I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
9-3 Timer Status and Control Register (TSCR) . . . . . . . . . . . .112
9-4 Timer Counter Register (TCR). . . . . . . . . . . . . . . . . . . . . .114
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List of Figures
MC68HC705J1A —Rev. 4.0 Technical Data
List of Figures
Figure Title Page
10-1 PA0–PA7, PB0–PB5 Typical High-Side
Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .123
10-2 PA0–PA3, PB0–PB5 Typical Low-Side
Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .123
10-3 PA4–PA7 Typical Low-Side Driver Characteristics . . . . . .124
10-4 Typical Operating IDD (25°C) . . . . . . . . . . . . . . . . . . . . . . .125
10-5 Typical Wait Mode IDD (25°C) . . . . . . . . . . . . . . . . . . . . . .125
10-6 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . .128
10-7 Stop Mode Recovery Timing . . . . . . . . . . . . . . . . . . . . . . .128
10-8 Power-On Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .129
10-9 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .129
A-1 RC Oscillator Connections. . . . . . . . . . . . . . . . . . . . . . . . .138
A-2 Typical Internal Operating Frequency
for Various VDD at 25°C — RC Oscillator
Option Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
B-1 Typical High-Speed Operating IDD (25°C) . . . . . . . . . . . . .142
B-2 Typical High-Speed Wait Mode IDD (25°C) . . . . . . . . . . . .143
C-1 Typical Internal Operating Frequency
at 25°C for High-Speed RC Oscill ator Option . . . . . . . .146
C-2 RC Oscillator Connections (No External Resistor). . . . . . .147
C-3 Typical Internal Operating Frequency
versus Temperature (OSCRES Bit = 1) . . . . . . . . . . . .148
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Technical Data MC68HC705J1A —Rev. 4.0
List of Figures
Li st of Figu r es
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MC68HC705J1A —Rev. 4.0 Tec hnical Data
List of Tables
Technical Data — MC68HC705J1A
List of Tables
Table Title Page
1-1 Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
3-1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . . .55
3-2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .56
3-3 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .58
3-4 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .59
3-5 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
3-6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3-7 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
4-1 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
4-2 External Interrupt Timing (VDD = 5.0 Vdc) . . . . . . . . . . . . . . .75
4-3 External Interrupt Timing (VDD = 3.3 Vdc) . . . . . . . . . . . . . . .75
4-4 Reset/Interrupt Vector Addresses . . . . . . . . . . . . . . . . . . . . .7 7
6-1 Port A Pin Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
6-2 Port B Pin Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
9-1 Real-Time Interrupt Rate Selection . . . . . . . . . . . . . . . . . . .114
12-1 Order Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
A-1 MC68HRC705J1A (RC Oscillator Option)
Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
B-1 MC68HSC705J1A (High Speed) Order Nu mbers . . . . . . . .144
C-1 MC68HSR705J1A (High-Speed RC Oscillator Option)
Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
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Technical Data MC68HC705J1A —Rev. 4.0
List of Tables
Li st of Tables
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MC68HC705J1A —Rev. 4.0 Tec hnical Data
General Description
Technical Data — MC68HC705J1A
Section 1. General Description
1.1 Contents
1.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
1.4 Programmable Options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 5
1.5 Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.5.1 VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.5.2 OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.5.2.1 Crysta l Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
1.5.2.2 Ceramic Resonator Oscillator . . . . . . . . . . . . . . . . . . . . .28
1.5.2.3 RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.5.2.4 External Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.6 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
1.7 IRQ/VPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.8 PA0–PA7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
1.9 PB0–PB5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
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Technical Data MC68HC705J1A —Rev. 4.0
Gen eral D es cri ptio n
General Description
1.2 Introduction
The MC68HC705J1A is a member of Motorola’s low-cost,
high-performance M68HC05 Family of 8-bit microcontroller units
(MCU s). The M68HC05 Fam i ly is based on the customer- specif ied
inte grated circuit (C SIC) design strateg y. All MCUs in the fami ly use the
popular M68HC05 central processor unit (CPU) and are available with a
variety of subsystems, memory sizes and types, and package types.
On-chip memory of the MC68HC705J1A includes 1240 bytes of
erasable, programmable read-only memory (EPROM). In packages
without the transparent window for EPROM erasure, the 1240 EPROM
bytes serve as one-time programmable read-only memory (OTPROM).
The MC68HRC705J1A is a resistor-capacitor ( RC) oscillato r mask
opti on version of the M C68HC705J1 A an d is d iscussed in Appendix A.
MC68HRC705J1A.
A high -speed ver sion o f the MC68H C705J1A , the MC68 HSC705J1A , is
discussed in Appendix B. MC68HSC705J1A.
The MC68HSR705J1A, discussed in Appendix C. MC68HSR705J1A,
is a high-speed version of the MC68HRC705J1A.
A functional block diagram of the MC68HC705J1A is shown in
Figure 1-1.
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General Descripti on
Introduction
MC68HC705J1A —Rev. 4.0 Technical Data
General Description
Figure 1-1. Block Diagram
0000000011
WATCHDOG AND
ILLEGAL ADDRESS
DETECT
STATIC RAM (SRAM) — 64 BYTES
ALUCPU CONTROL
68HC05 CPU
ACCUMULATOR
INDEX REGISTER
STK PTR
PROGRAM COUNTER
CONDITION CODE
REGISTER
15-STAGE
MULTIFUNCTION
TIMER SYSTEM
DIVIDE
INTERNAL
OSCILLATOR
OSC1
OSC2
CPU REGISTERS
USER EPROM — 1240 BYTES
MASK OPTION REGISTER (EPROM)
*1 0- m A sink cap ab ility
**External interrupt capability
DATA DIRECTION REGISTER A DATA DIRECTION REGISTER B
PORT A PORT B
PB5
PB4
PB3
PB2
PB1
PB0
PA7*
PA6*
PA5*
PA4*
PA3**
PA2**
PA1**
PA0**
111HINZC
BY ³2
RESET
IRQ/VPP
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Technical Data MC68HC705J1A —Rev. 4.0
Gen eral D es cri ptio n
General Description
1.3 Features
Features of the MC68HC705J1A include:
•Perip heral modules:
–15-stage multifunction timer
–Computer operating properly (COP) watchdog
•14 bidirectional input/output (I/O) lines, including:
–10-mA sink capability on four I/O pins
–Mask option register (MOR) and software programmable
pulldowns on all I/O pins
–MOR selectable interrupt on four I/O pins, a keyboard scan
feature
•MOR selectable sensitivity on external interrupt (edge- and
level-sensitive or edge-sensitive only)
•On-chip oscillator with connections for:
– Crystal
–Ceramic resonator
–Resistor-capacitor (RC) oscillator
–External clock
•1240 bytes of EPROM/OTPROM, including eight bytes for user
vectors
•64 bytes of user random-access memory (RAM)
•Memory-mapped I/O registers
•Fully static operation with no minimum clock speed
•Power-saving stop, halt, wait, and data-retention modes
•External interrupt mask bit and acknowledge bit
•Illegal address reset
•Interna l steer ing d iode a nd p ul lup r esistor fro m RE SET pin to VDD
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General Descripti on
Programmable Options
MC68HC705J1A —Rev. 4.0 Technical Data
General Description
1.4 Programmable Options
The option s in Table 1-1 are programm abl e in the mask option r egister
(MOR).
1.5 Pin Assignments
Figure 1-2 shows the MC68HC705J1A pin assignments.
1.5.1 VDD and VSS
VDD a nd VSS are the power supply and g round pins. The MCU opera tes
from a single power supply.
Very fast signal transitions occur on the MCU pins, placing high,
short-duration current demands on the power supply. To prevent noise
problems, take special care as Figure 1-3 shows, b y pla cing the bypass
capacitors as close as possible to the MCU. C2 is an optional bulk
current bypass capacitor for use in applications that require the port pins
to source high current levels.
Table 1-1. Programmable Options
Feature Option
COP watchdog timer Enabled or disabled
External interrupt triggering Edge-sensitive only or edge- and level-sensitive
Port A IRQ pin interrupts Enabled or disabled
Port pulldown resistors Enabled or disabled
STOP instruction mode Stop m ode or halt mode
Crystal oscillator internal resistor Enabled or disabled
EPROM security Enabled or disabled
Short oscillator delay counter Enabled or disabled
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Technical Data MC68HC705J1A —Rev. 4.0
Gen eral D es cri ptio n
General Description
Figu re 1-2. Pin Assignments
Figure 1-3. Bypassing Layout Recommendation
OSC1 1
OSC2 2
PB5 3
PB4 4
PB3 5
PB2 6
PB1 7
PB0 8
RESET
20
IRQ/VPP
19
PA018
PA117
PA216
PA315
PA414
PA513
PA6
12
PA7
11
VSS 10
VDD 9
C1
C2
MCU C1
0.1 µFC2
V+
+
VDD
VSS
VDD
VSS
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General Descripti on
Pin Assignments
MC68HC705J1A —Rev. 4.0 Technical Data
General Description
1.5.2 OSC1 and OSC2
The OSC1 and OSC2 pins are the connections for the on-chip oscillator.
The oscillator can be driven by a ny of these:
1. Crystal (See Figure 1-4 and Figure 1-5.)
2. Ce ramic resonator (See Figure 1-6 and Figure 1-7.)
3. Resistor/capacitor (RC) oscillator (Refer to Appendix A.
MC68HRC705J1A and Appendix C. MC68HSR705J1A.)
4. External clock signal (See Fi gure 1-8.)
The frequency, fosc, of the oscillator or external clock source is divided
by two to produce the internal operating frequency, fop.
1.5.2.1 Crystal Oscillator
Figure 1-4 an d Fig ur e 1- 5 show a typical crystal oscillator circuit for an
AT-cut, parallel resonant crystal. Follow the crystal supplier ’s
recommendations, as the crystal parameters determine the external
component values required to provide reliable startup and maximum
stability. The load capacitance values used in the oscillator circuit design
should include all stray layout capacitances.
To mini mize out put distortion, mount the crystal an d capacitors a s close
as possible to the pins. An internal startup resistor of approximately
2MΩ is pro vided bet ween OSC1 and OS C2 for the cr ystal oscillator as
a programm abl e mask option.
NOTE: U se an AT-cut cryst al and not an AT -strip crystal becau se the MCU can
overdrive an AT-strip crystal.
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Technical Data MC68HC705J1A —Rev. 4.0
Gen eral D es cri ptio n
General Description
Figure 1-4. Crystal Connections with
Oscillator Internal Resistor Mask Option
Figure 1-5. Crystal Connections without
Oscillator Internal Resistor Mask Option
1.5.2.2 Ceramic Resonator Oscillator
To reduce cost, use a ceramic resonator instead of the crystal. The
circuits shown in Figure 1-6 and Figure 1-7 show ceramic re sonator
circuits. Follow the resonator manufacturer’s recommendations, as the
resonator parameters determine the external component values
required for maximum stability and reliable starting. The load
capacitance values used in the oscillator circuit design should include all
stray capacitances.
MCU
C1C2
XTAL
C4
C3
XTAL
C3
27 pF
C4
27 pF
OSC1
OSC2
OSC1
OSC2
VSS
VDD
VSS
MCU
C1C2
R
XTAL
C4
C3
R
10 M¾Ω
XTAL
C3
27 pF
C4
27 pF
OSC1
OSC2
VDD
VSS
OSC1
OSC2
VSS
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General Descripti on
Pin Assignments
MC68HC705J1A —Rev. 4.0 Technical Data
General Description
Mount the resonator and components as close as possible to the pins for
startup stabilization and to minimize output distortion. An internal startup
resistor of approximately 2 MΩ is provided between OSC1 and OSC2 as
a programm abl e mask option.
Figure 1-6. Ceramic Resonator Connections
with Oscillator Internal Resistor Mask Option
Figure 1-7. Ceramic Resonator Connections
without Oscillator Internal Resistor Mask Option
MCU
C1C2
CERAMIC
C4
C3
CERAMIC
C3
27 pF
C4
27 pF
RESONATOR
RESONATOR
OSC1
OSC2
OSC1
OSC2
VDD
VSS
VSS
MCU
C1C2
R
CERAMIC
C4
C3
R
10 M¾Ω
CERAMIC
C3
27 pF
C4
27 pF
RESONATOR
RESONATOR
VSS
VDD
VSS
OSC1
OSC2
OSC1
OSC2
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Technical Data MC68HC705J1A —Rev. 4.0
Gen eral D es cri ptio n
General Description
1. 5.2.3 RC Oscilla tor
Refer to Appendix A. MC68HRC705J1A and Appendix C.
MC68HSR705J1A.
1.5.2.4 External Clock
An external clock from another complementar y metal-oxide
semiconductor (CMOS)-compatible device can be connected to the
OSC1 input, with the OSC2 input not connected, as shown in
Figure 1-8. This configuration is possible regardless of whether the
crystal/ceramic resonator or the RC oscillator is enabled.
Figure 1-8. External Clock Connections
1.6 RESET
Applying a logic 0 to the RE SET pin forc es the MC U to a kn own star tup
state. An internal reset also pulls the RESET pin low. An internal resistor
to VDD pulls the RESE T pin high. A steerin g diode b etw een the RESE T
and VDD pins discharges any RESET pin voltage when power is
removed from the MCU. The RESET pin contains an internal Schmitt
trigger to improve its noise immunity as an input. Re fer to Section 4.
Resets and Interrupts for more information.
MCU
EXTERNAL
CMOS CLOCK
OSC1
OSC2
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General Descripti on
IRQ/VPP
MC68HC705J1A —Rev. 4.0 Technical Data
General Description
1.7 IRQ/VPP
The external interrupt/programming voltage pin (IRQ/VPP) drives the
asynchronous IRQ interrupt function of the CPU. Additionally, it is used
to pr ogram the u s er EPROM and mask opti on r egiste r. ( See S ect ion 2 .
Memory and Section 8. External Interrupt Module (IRQ).)
The LEVEL bit in the mask option register provides negative
edge-sensitive triggering or both negative edge-sensitive and low
level-sensitive triggering for the interrupt function.
If level-sensitive triggering is selected, the IRQ/VPP input requires an
external resistor to VDD for wired- OR operat ion. I f the IRQ/VPP pin is no t
used, it must be tied to the VDD supply.
The IRQ/VPP pin contains an internal Schmitt trigger as part of its input
to im prove noise immunity. The voltage on this pin should not exceed
VDD except when the pin is being used for programming the EPROM.
NOTE: The mask option register can enable the PA0–PA3 pins to function as
external interrupt pins.
1.8 PA0–PA7
These ei ght input/ou tput (I/O) l ines comprise por t A, a genera l-pur pose,
bidirectiona l I/O por t. See Sectio n 8. E xte rnal In ter rupt Module ( IRQ)
for information on PA0–PA3 external interrupts.
1.9 PB0–PB5
These six I /O lines comprise port B, a general-purp ose, bidirectiona l I/O
port.
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Technical Data MC68HC705J1A —Rev. 4.0
Gen eral D es cri ptio n
General Description
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MC68HC705J1A —Rev. 4.0 Tec hnical Data
Memory
Technical Data — MC68HC705J1A
Section 2. Memory
2.1 Contents
2.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.3 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.4 Input/Output Register Summary. . . . . . . . . . . . . . . . . . . . . . . .35
2.5 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.6 EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
2.6.1 EPROM/OTPROM Programming. . . . . . . . . . . . . . . . . . . . .38
2.6.2 EPROM Programming Register . . . . . . . . . . . . . . . . . . . . .39
2.6.3 EPROM Erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
2.7 Mask Option Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
2.8 EPROM Programming Characteristics. . . . . . . . . . . . . . . . . . .43
2.2 Introduction
This section describes the organization of the on-chip memory
consisting of:
•1232 bytes of user erasable, programmable read-only memory
(EPROM), plus eight bytes for user vectors
•64 bytes of user random-access memory (RAM)
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Technical Data MC68HC705J1A —Rev. 4.0
Memory
Memory
2.3 Memory Map
Port A Data Register (PORTA) $0000
Port B Data Register (PORTB) $0001
Unimplemented $0002
$0003
Data Direction Register A (DDRA) $0004
Data Direction Register B (DDRB) $0005
Unimplemented $0006
$0007
Timer Status and Control Register (TSCR) $0008
Timer Control Register (TCR) $0009
$0000 I/O Registers
32 Bytes
IRQ Status and Control Register (ISCR) $000A
↓
Unimplemented
$000B
$001F ↓
$0020 Unimplemented
160 Bytes
$000F
↓Pulldown Register Port A (PDRA) $0010
$00BF Pulldown Register Port B (PDRB) $0011
$00C0 RAM
64 Bytes Unimplemented
$0012
↓ ↓
$00FF $0017
$0100 Unimplemented
512 Bytes
EPROM Programming Register (EPROG) $0018
↓
Unimplemented
$0019
$02FF ↓
$0300 EPROM
1232 Bytes
$001E
↓Reserved $001F
$07CF
$07D0 Unimplemented
30 Bytes
COP Register (COPR)(1) $07F0
↓Mask Option Register (MOR) $07F1
$07ED
Reserved
$07F2
$07EE Test ROM
2 Bytes
↓
$07EF $07F7
$07F0 Registers and EPROM
16 Bytes
Timer Interrupt Vector High $07F8
↓Timer Interrupt Vector Low $07F9
$07FF External Interrupt Vector High $07FA
External Interrupt Vector Low $07FB
Software Interrupt Vector High $07FC
Software Interrupt Vector Low $07FD
Reset Vector High $07FE
Reset Vector Low $07FF
(1) Writi ng to bit 0 of $07F0 clears the computer
operating properl y (COP) watchdog.
Figure 2-1. Memory Map
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Memory
Input/Out put Register Summ ary
MC68HC705J1A —Rev. 4.0 Technical Data
Memory
2.4 Inpu t/Out put Register Summary
Addr.Register Name Bit 7654321Bit 0
$0000
Port A Data Register
(PORTA)
See page 89.
Read:
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Write:
Reset: Unaffected by reset
$0001
Port B Data Register
(PORTB)
See page 92.
Read: 0 0
PB5 PB4 PB3 PB2 PB1 PB0
Write:
Reset: Unaffected by reset
$0002 Unimplemented
$0003 Unimplemented
$0004
Data Direction Register A
(DDRA)
See page 90.
Read: DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset:00000000
$0005
Data Direction Register B
(DDRB)
See page 93.
Read: 0 0
DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset:00000000
$0006 Unimplemented
$0007 Unimplemented
$0008
Timer Status and Control
Register (TSCR)
See page 112.
Read: TOF RTIF
TOIE RTIE
00
RT1 RT0
Write: TOFR RTIFR
Reset:00000011
= Unimplemented R = Reserved
Figure 2-2. I/O Register Summary (Sheet 1 of 3)
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Technical Data MC68HC705J1A —Rev. 4.0
Memory
Memory
$0009
Timer Counter Register
(TCR)
See page 114.
Read: TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0
Write:
Reset:00000000
$000A
IRQ Status and Control
Register (ISCR)
See page 106.
Read:
IRQE
000IRQF000
Write: RIRQR
Reset:10000000
$000B Unimplemented
↓
$000F Unimplemented
$0010
Pulldown Register A
(PDRA)
See page 91.
Read:
Write: PDIA7 PDIA6 PDIA5 PDIA4 PDIA3 PDIA2 PDIA1 PDIA0
Reset:00000000
$0011
Pulldown Register B
(PDRB)
See page 94.
Read:
Write: PDIB5 PDIB4 PDIB3 PDIB2 PDIB1 PDIB0
Reset:00000000
$0012 Unimplemented
↓
$0017 Unimplemented
$0018
EPROM Programming
Register (EPROG)
See page 39.
Read: 0 0 0 0 0
ELAT MPGM EPGM
Write: RRRR
Reset:00000000
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved
Figure 2-2. I/O Register Summary (Sheet 2 of 3)
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Memory
RAM
MC68HC705J1A —Rev. 4.0 Technical Data
Memory
2.5 RAM
The 64 addresses from $00C0 to $00FF serve as both the user RAM and
the stack RAM. Before processing an interrupt, the central processor
unit (CPU) uses five bytes of the stack to save the contents of the CPU
regi sters. D uring a sub rout ine call , th e CP U uses two bytes o f the stack
to store the return address. The stack pointer decrements when the CPU
stores a byte on the stack and increments when the CPU retrieves a byte
from the stack.
NOTE: Be care ful when using nested subroutines or multiple interrupt levels.
The CPU may overwrite data in the RAM during a subroutine or during
the interrupt stacking operation.
$0019 Unimplemented
↓
$001E Unimplemented
$001F Reserved RRRRRRRR
$07F0
COP Register
(COPR)
See page 99.
Read:
Write: COPC
Reset: 0
$07F1
Mask Option Register
(MOR)
See page 41.
Read:
SOSCD EPMSEC OSCRES SWAIT SWPDI PIRQ LEVEL COPEN
Write:
Reset: Unaffected by reset
Addr.Register Name Bit 7654321Bit 0
= Unimplemented R = Reserved
Figure 2-2. I/O Register Summary (Sheet 3 of 3)
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Technical Data MC68HC705J1A —Rev. 4.0
Memory
Memory
2.6 EPROM/OTPROM
A microcontroller unit (MCU) with a quartz window has 1240 bytes of
erasable, programmable ROM (EPROM). The quartz window allows
EPROM erasure with ultraviolet light.
NOTE: Keep the quartz window covered with an opaque material except when
programming the MCU. Ambient light can affect MCU operation.
In an MC U without the quartz window, the EPROM cannot be erased
and serves as 1240 bytes of one-ti me programmabl e ROM (OT PROM ).
These addresses are user EPROM/OTPROM locations:
•$0300–$07CF
•$07F8–$07FF, used for user-defined interrupt and reset vectors
The computer operating properly (COP) register (COPR) is an
EPROM/OTPROM location at address $07F0.
The mask option register (MOR) is an EPROM/OTPROM location at
address $07F 1.
2.6.1 EPROM/OTPROM Programming
The two ways to program the EPROM/OTPROM are:
1. Mani pulating the control bits in the E PROM pro gramming register
to program the EPROM/OTPROM on a byte-by-byte basis
2. Programming the EP ROM/OTPROM with the M68HC705J
in-circuit simulator (M68HC705JICS) available from Freescale
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Memory
EPROM/OTPROM
MC68HC705J1A —Rev. 4.0 Technical Data
Memory
2.6.2 EPROM Programming Register
The EPROM programming register (EPROG) contains the control bits
for programming the EPROM/OTPROM.
ELAT — EPROM Bus Latch Bit
This read/write bit latches the address and data buses for
EPROM/OTPROM programming. Clearing the ELAT bit automatically
clears the EPGM bit. EPROM/OTPROM data cannot be read while
the ELAT bit is set. Reset clears the ELAT bit.
1 = Address and data buses configured for EPROM/OTP ROM
programming the EPROM
0 = Address and data buses configured for normal operation
MPGM — MOR Programming Bit
Thi s read/wr ite bi t applies prog ram mi ng power from the IRQ/VPP pin
to the mask option register. Reset clears MPGM.
1 = Programming voltage applied to MOR
0 = Programming voltage not applied to MOR
EPGM — EPROM Progra mming Bit
This read/write bit applies the voltage from the IRQ/VPP pin to the
EPROM. To write the EPGM bit, the EL AT bit must be set already.
Reset clears EPGM.
1 = Programming voltage (IRQ/VPP pin) applied to EPROM
0 = Programming voltage (IRQ/VPP pin) not applied to EPROM
Address: $0018
Bit 7654321Bit 0
Read: 0 0 0 0 0
ELAT MPGM EPGM
Write: RRRR
Reset:00000000
= Unimplemented R = Reserved
Figure 2-3. EPROM Programming Register (EPROG)
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Technical Data MC68HC705J1A —Rev. 4.0
Memory
Memory
NOTE: Writing logic 1s to both the ELAT and EPGM bits with a single instruction
sets ELAT and cl ears EPGM. ELAT must be set first by a separate
instruction.
Bits [7:3] — Reserved
Take these steps to program a byte of EPROM/OTPROM:
1. Apply the programming voltage, VPP, to the IRQ/VPP pin.
2. Set the ELAT bit.
3. Write to any EPROM/OTPROM address.
4. Set the EPGM bit and wait for a time, tEPGM.
5. Clear the ELAT bit.
2.6.3 EPROM Erasing
The erased state of an EPROM bit is logic 0. Erase the EPROM by
exposing it to 15 Ws/cm2 of ultraviolet light with a wave length of
2537 angstroms. Position the ultraviolet light source one inch from the
EPROM. Do not use a shortwave filter.
2.7 Mask Option Register
The mask option register (MOR) is an EPROM/OTPROM byte that
controls these options:
•COP watchdog (enable or di sable)
•Exter nal i n terr upt pin triggeri ng (edg e-sen si tive o nl y or ed ge- and
level-sensitive)
•Port A external interrupts (enable or disable)
•Port pulldown resistors (enable or disable)
•STOP instruction (stop mode or halt mode)
•Crystal oscillator internal resistor (enable or disable)
•EPROM security (enable or disable)
•Short oscillator delay (enable or disable)
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Memory
Mask Option Register
MC68HC705J1A —Rev. 4.0 Technical Data
Memory
Take these steps to program the mask option register:
1. Apply the programming voltage, VPP, to the IRQ/VPP pin.
2. Write to the MOR.
3. Set the MPGM bit and wait for a time, tMPGM.
4. Clear the MPGM bit.
5. Reset the MCU.
SOSCD — Short Oscillator Delay Bit
The SOSCD bit controls the oscillator stabilization counter. The
normal stabilization delay following reset or exit from stop mode is
4064 tcyc. Setting SOSCD enables a short oscillator stabilization
delay.
1 = Short oscillator delay enabled
0 = Short oscillator delay disabled
EPMSEC — EPROM Se curity Bit
The EPMSEC bit controls access to the EPROM/OTPROM.
1 = External access to EPROM/OTPROM denied
0 = External access to EPROM/OTPROM not denied
OSCRES — Oscillator Inter n al Resistor Bit
The OSCRES bit enables a 2-M Ω internal resistor in the oscillator
circuit.
1 = Oscillator internal resistor enabled
0 = Oscillator internal resistor disabled
NOTE: Program the OSCRES bit to logic 0 in devices using RC oscil lators.
Address: $07F1
Bit 7654321Bit 0
Read:
SOSCD EPMSEC OSCRES SWAIT SWPDI PIRQ LEVEL COPEN
Write:
Reset: Unaffected by reset
Figure 2-4. Mask Option Register (MOR)
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Technical Data MC68HC705J1A —Rev. 4.0
Memory
Memory
SWAIT — Stop-to-Wait Conversion Bit
The SWAIT bit enables halt mode. When the SWAIT bi t is set, the
CPU interprets the STOP instruction as a WAIT instruction, and the
MC U enters halt mode. Halt mode is the same as wait mode, except
that an oscillator stabilization delay of 1 to 4064 tcyc occurs after
exiting halt mode.
1 = Hal t mode enabled
0 = Hal t mode not enabled
SWPDI — Software Pulldown Inhibit Bit
The SWPDI bit inhibits software control of the I/O port pulldown
devi ces. The S WPDI b it over ri des t he pu lldow n inhib it bi ts in t he po rt
pulldown inhibit registers.
1 = Software pulldown control inhibited
0 = Software pulldown control not inhibited
PIRQ — Port A External Interrupt Bit
The PIRQ bit enables the PA0–PA3 pins to function as external
interrupt pins.
1 = PA0–PA3 enabled as external interrupt pins
0 = PA0–PA3 not enabled as external interrupt pins
LEVEL —External Interrupt Sen sitivity Bit
The LEVEL bit controls external interrupt triggering sensitivity.
1 = External interrupts triggered by active edges and active levels
0 = External interrupts triggered only by active edges
COPEN — COP Enable Bit
The COPEN bit enables the COP watchdog.
1 = COP watchdog enabled
0 = COP watchdog disabled
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Memory
EPROM Program ming Charac teristics
MC68HC705J1A —Rev. 4.0 Technical Data
Memory
2.8 EPROM Programming Characteris tics
Characteristic(1)
1. VDD = 5.0 Vdc ± 10% , VSS = 0 Vdc, TA = –40°C to +105°C
Symbol Min Typ Max Unit
Programming voltage
IRQ/VPP VPP 16.0 16.5 17.0 V
Programming current
IRQ/VPP IPP —¦ 3.0 10.0 mA
Pr ogr a mming ti me
Per array byt e
MOR tEPGM
tMPGM 4
4—
——
—ms
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Technical Data MC68HC705J1A —Rev. 4.0
Memory
Memory
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MC68HC705J1A —Rev. 4.0 Tec hnical Data
Central Processor Unit (CPU)
Technical Data — MC68HC705J1A
Section 3. Central Processor Unit (CPU)
3.1 Contents
3.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.3 CPU Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.4 Arithmetic/Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
3.5 CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 8
3.5.1 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.5.2 Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.5.3 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
3.5.4 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.5.5 Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .50
3.6 Instruction Set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
3.6.1 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
3.6.1.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
3.6.1.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
3.6.1.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.6.1.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.6.1.5 Indexed, No Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.6.1.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
3.6.1.7 Indexed, 16-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . .54
3.6.1.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
3.6.2 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
3.6.2.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . .55
3.6.2.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . .56
3.6.2.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .57
3.6.2.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . .59
3.6.2.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
3.7 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
3.8 Opcode Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
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Technical Data MC68HC705J1A —Rev. 4.0
Central Processor Unit (CPU)
Ce ntral Processor Unit (CPU)
3.2 Introduction
The central processor unit (CPU) consists of a CPU control unit, an
arithmetic/logic unit (ALU), and five CPU registers. The CPU control unit
fetches and decodes instructions. The ALU executes the instructions.
The CPU registers contain data, addresses, and status bits that reflect
the results of CPU operations. See Figure 3-1.
Features include:
•2.1-MHz bus frequency
•8-bit accumulator
•8-bit index register
•11-bit program counter
•6-bit stack pointer
•Condition code register (CCR) with five status flags
•62 instructions
•Eight addressing modes
•Power-saving stop, wait, halt, and data-retention modes
3.3 CPU Control Unit
The CPU control unit fetches and decodes instructions during program
operation. The control unit selects the memory locations to read and
write and coordinates the timing of all CPU operations.
3.4 Arithmetic/Logic Unit
The arithmetic/logic unit (ALU) performs the arithmetic, logic, and
manipulation operations decoded from the instruction set by the CPU
control unit. The ALU produces the results called for by the program and
sets or clears status and control bits in the condition code register
(CCR).
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Central Processor Unit (CP U)
Arithmetic/Logic Unit
MC68HC705J1A —Rev. 4.0 Technical Data
Central Processor Unit (CPU)
Figure 3-1. Programming Model
ACCUMULATOR (A)
INDEX REGISTER (X)
CONDITION CODE REGISTER (CCR)
PROGRAM COUNTER (PC)
STACK POINTER (SP)
HALF-CARRY FLAG
INTERRUPT MASK
NEGATIVE FLAG
ZERO FLAG
CARRY/BORROW FLAG
04756 321
0
ARITHMETIC/LOGIC UNIT
CPU CONTROL UNIT
04756 321
04756 32181215 1314 11 10 9
000000011
000
04756 32181215 1314 11 10 9
111HINZC
04756 321
00
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Technical Data MC68HC705J1A —Rev. 4.0
Central Processor Unit (CPU)
Ce ntral Processor Unit (CPU)
3.5 CPU Registers
The M68HC05 CPU contains five registers that control and monitor
microcontroller unit (MCU) operation:
•Accumulator
•Index register
•Stack pointer
•Program counter
•Condition code register
CPU registers are not memory mapped.
3.5.1 Accumulator
The accumulator (A) is a general-purpose 8-bit register. The CPU uses
the accumulator to hold operands and results of A LU operations.
3.5.2 Index Register
In the indexed addressing (X) modes, the CPU uses the byte in the index
regi ster to deter mine th e conditi o nal addr ess of the opera nd. Th e i ndex
register also can serve as a temporary storage location or a counter.
Bit 7654321Bit 0
Read:
Write:
Res et: Unaffec ted by re set
Figure 3-2. Accumulator (A)
Bit 7654321Bit 0
Read:
Write:
Res et: Unaffec ted by re set
Figure 3-3. Index Register (X)
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Central Processor Unit (CP U)
C PU Registers
MC68HC705J1A —Rev. 4.0 Technical Data
Central Processor Unit (CPU)
3.5.3 Stack Pointer
The stack pointer (SP) is a 16-bit register that contains the address of
the next location on the stack. During a reset or after the reset stack
pointer instruction (RSP), the stack pointer is preset to $00FF. The
address in the stack pointer decrements after a byte is stacked and
increments before a byte is unstacked.
The 10 most significant bits of th e stack po inter are perman ently f ix ed at
0000000011, so the stack pointer produces addresses from $00C0 to
$00FF. If subroutines and interrupts use more than 64 stack locations,
the stack pointer wraps around to address $00FF and begins wr iting
over the previously stored data. A subroutine uses two stack locations;
an interrupt uses five locations.
Bit
151413121110987654321
Bit
0
Read:0000000011
Write:
Reset:0000000011111111
= Unimplemented
Figu re 3-4. St ack Pointe r (SP)
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Central Processor Unit (CPU)
Ce ntral Processor Unit (CPU)
3.5.4 Program Counter
The prog ram counter (P C) is a 16-bit register that contain s the addre ss
of the next instruction or operand to be fetch ed. The five most significant
bits of the program counter are ignored and appear as 00000.
Normal ly, the ad dress in the pr ogra m counte r auto maticall y incre ments
to the next sequential memory location every time an instruction or
operand is fetched. Jump, branch, and interrupt operations load the
program counter with an address other than that of the next sequential
location.
3.5.5 Condition Code Register
The condition code r egister (CCR) is a n 8- bit registe r who se t hree mo st
significant bits are permanen tly fixed at 111. The condition code register
contai ns the interru pt mask and four fla gs that indicate the re sults of the
instruction ju st executed.
Bit
151413121110987654321
Bit
0
Read:
Write:
Reset: 0 0 0 0 0 Loaded with vector from $07FE and $07FF
Figure 3-5. Program Counter (PC)
Bit 7654321Bit 0
Read: 1 1 1 HINZC
Write:
Reset:111U1UUU
= Unimpleme nted U = Unaffected
Figure 3-6. Condition Code Register (CCR)
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Central Processor Unit (CP U)
C PU Registers
MC68HC705J1A —Rev. 4.0 Technical Data
Central Processor Unit (CPU)
H — Half-Carry Flag
The CPU sets the half-carry flag when a carr y occurs betwee n bi ts 3
and 4 of the accumulator during an ADD (add without carry) or ADC
(add with carry) operation. The half-carry flag is required for
binary-coded decimal (BCD) arithmetic operations.
I — Interrupt Mask Bit
Setting the interrupt mask disables interrupts. If an interrupt request
occurs while the interrupt mask is logic 0, the CPU saves the CPU
registers on the stack, sets the interrupt mask, and then fetches the
interrupt vector. If an interrupt request occurs while the interrupt mask
is logic 1, the interrupt request is latched. Norm ally, the CPU
processes the latched interrupt request as soon as the interrupt mask
is cleared again.
A return-from-interrupt instruction (RTI) unstacks the CPU registers,
restoring the interrupt mask to its cleared state. After any reset, the
interrupt mask is set and can be cleared only by a software
instruction.
N — Negative Flag
The CPU sets the negative flag when an ALU operation produces a
negative result.
Z — Zero Flag
The CPU sets the zero flag when an ALU operation produces a result
of $00.
C — Carry/Borrow Flag
The CPU sets the carry/borrow flag when an addition operati on
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some logical operations and data
manipulation instructions also clear or set the carry/borrow flag.
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Technical Data MC68HC705J1A —Rev. 4.0
Central Processor Unit (CPU)
Ce ntral Processor Unit (CPU)
3.6 Instruction Set
The MCU instruction set has 62 instructions and uses eight addressing
modes.
3.6.1 Addressing Modes
The CPU uses eight addressing modes for flexibility in accessing data.
The addressing modes provide eight different ways for the CPU to find
the data required to execute an instruction. The eight addressing modes
are:
•Inherent
•Immediate
•Direct
•Extended
•Indexed, no offset
•Indexed, 8-bit offset
•Indexed, 16-bit offset
•Relative
3. 6.1.1 Inherent
Inherent instructions are those that have no operand, such as return
from i nt err upt ( RTI) a nd sto p (S TOP). So me of the i nh eren t instru cti ons
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
3. 6.1.2 Immediate
Immediate instructions are those that contain a value to be used in an
operat ion wi th the value in the accumul ator o r index reg ister. Immed iate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
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Central Processor Unit (CP U)
In stru ction Set
MC68HC705J1A —Rev. 4.0 Technical Data
Central Processor Unit (CPU)
3. 6.1.3 Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcod e, and the second is the low byte of
the operan d address. In di rect addr essing, the CPU autom aticall y uses
$00 as the high byte of the operand address.
3. 6.1.4 Exte nded
Extended instructions use three bytes and can access any address in
memor y. The fir st byte is the opco de; the seco nd and th ird bytes ar e the
high and low bytes of the operand address.
When using the Freescale assem bl er, th e prog ram mer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
3.6.1.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variab le addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instru ctions are often used to move a point er through
a table or to hold the address of a frequently used RAM or input/output
(I/O) location.
3.6.1.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instru ctions ar e 2- byte in structi o ns tha t can a ccess
data w ith varia bl e addresses w ithin the firs t 511 m emory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-b it offset instructions are usefu l for selecting the kth element
in an n- element table. The ta ble ca n begin anywhe re within the first 256
memory locations and could extend as far as location 510 ($01FE).
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Central Processor Unit (CPU)
Ce ntral Processor Unit (CPU)
The k value is typically in the index register, and the address of the
beginning of the table is in the byte following the opcode.
3.6.1.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data w ith var iable addresses at any l o cation in m emo ry. T he CP U adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
As with direct and extended addressing, the Freescale assembler
determines the shortest form of indexed addressing.
3. 6.1.8 Relative
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branchi ng range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Freescale assem bl er, th e prog ram mer does not need to
calculate the offset because the assembler determines the prop er offset
and veri fies that it is within the span of the branch.
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Central Processor Unit (CP U)
In stru ction Set
MC68HC705J1A —Rev. 4.0 Technical Data
Central Processor Unit (CPU)
3.6.2 Instruction Types
The MCU instructions fall into these five categories:
•Register/memory instructions
•Read-modify-write instructions
•Jump/branch instructions
•Bit manipulation instructions
•Control instructions
3.6.2.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 3-1. Register/Memory Instructions
Instruction Mnemonic
Add memory byte and carry bit to ac cum ulator ADC
Add memory byte to accumulator ADD
AND memory byte with accumulator AND
Bit test accu mu l a to r BIT
Compare acc umulator CMP
Compare index register with memory byte CPX
EXCLU SIVE OR accumulator wi th me mo r y b yte EOR
Load accumulator with memory byte LDA
Load index register with memory byte LDX
Multiply MUL
OR accum ulator with m emory byte ORA
Subtract memory by te and carry bit from accumula tor SBC
St ore acc umulator in memory S TA
Store ind ex register in mem ory STX
Subtract memory by te from accumu lator SUB
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Central Processor Unit (CPU)
Ce ntral Processor Unit (CPU)
3.6.2.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its
contents, and write the modifi ed value b ack to the memory location o r to
the register.
NOTE: Do not use read-modify-write instructions on registers with write-only
bits.
Table 3-2. Read- Mo dify -W rit e Instruc tion s
Instruction Mnemonic
Arithm etic s hift left (same as LSL) ASL
Arithm etic shift right ASR
Bit clear BCLR(1)
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
Bit se t BSET(1)
Clear register CLR
Compl ement (one’s comple ment) COM
Decrement DEC
Increment INC
Logical shift left (same as ASL) LSL
Logical shift right LSR
Negate (two’s complement) NEG
Rotate left through carry bit ROL
Rotate right through carry bit ROR
Test for negative or zero TST(2)
2. TST is an exception to the read-modify-wri te sequence
because it does not write a re placement value.
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In stru ction Set
MC68HC705J1A —Rev. 4.0 Technical Data
Central Processor Unit (CPU)
3.6.2.3 Jump/Branch Instructions
Jump instruct ions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the C PU to interrupt the normal sequence of the
progr am co unter when a test condit ion is met. If the test condi tio n is n ot
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +1 27 from the addr ess of the next locatio n after the bran ch
instructi on. The CPU also tr ansfe rs the tested b i t to the carry/borr ow bit
of the condition code register.
NOTE: Do not use BRCLR or BRSET instructions on register s with write-only
bits.
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Central Processor Unit (CPU)
Ce ntral Processor Unit (CPU)
Table 3-3. Jump and Branch Instructions
Instruction Mnemonic
Branch if carry bit clear BCC
Branch if carry bit set BCS
Branch if equal BEQ
Branch if half-carry bit clear BHCC
Branch if half-carry bit set BHCS
Branch if higher BHI
Branch if higher or same BHS
Branch if IRQ pin high BIH
Branch if IRQ pin low BIL
Branch if lower BLO
Branch if lower or same BLS
Branch if interrupt mask clear BMC
Branch if minus BMI
Branch if interrupt mask set BM S
Branch if not equal BNE
Branch if plus BPL
Branch always BRA
Branch if bit clear BRCLR
Branch nev er BRN
Branch if bit set BRSE T
Branch to subroutine BSR
Unconditional jump JMP
Jump to subroutine JSR
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Central Processor Unit (CP U)
In stru ction Set
MC68HC705J1A —Rev. 4.0 Technical Data
Central Processor Unit (CPU)
3.6.2.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can al so test and br anch based on th e state of any bit in an y o f the
first 256 memory locations.
NOTE: D o no t use bit m anipulation instru ctions on r egister s wit h write- only bits.
Table 3-4. Bit Manipulation Instructions
Instruction Mnemonic
Bit clear BCLR
Branch if bit clear BRCLR
Branch if bit set BRSET
Bit se t BSET
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Central Processor Unit (CPU)
Ce ntral Processor Unit (CPU)
3.6.2.5 Control Instructions
These instructions act on CPU registers and control CPU operation
during program execution.
Table 3-5. Control Instructions
Instruction Mnemonic
Clear carry bit CLC
Clear interrupt m ask CLI
No operation NOP
Reset stack pointer RSP
Ret ur n from inter ru p t R T I
Return from subroutine RT S
Set carry bit SEC
Set interrupt m as k SEI
Stop oscillator and enable I RQ pin STOP
Software interru pt SW I
T ransfer accumulat or to index register TAX
Trans fer index register to accumulator T X A
Stop CPU clo ck and enable interrupts WAIT
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Central Processor Unit (CP U)
Instruction Set Summary
MC68HC705J1A —Rev. 4.0 Technical Data
Central Processor Unit (CPU)
3. 7 Ins truction Set Summary
Table 3-6. Instruction Set S ummary (Sheet 1 of 6)
Source
Form Operation Description Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
HINZC
ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
Add with Ca rry A ← (A) + (M) + (C)
—
IMM
DIR
EXT
IX2
IX1
IX
A9
B9
C9
D9
E9
F9
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
Ad d wi th ou t C arr y A ← (A) + (M)
—
IMM
DIR
EXT
IX2
IX1
IX
AB
BB
CB
DB
EB
FB
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
Logical AND A ← (A) ∧ (M) ——
—
IMM
DIR
EXT
IX2
IX1
IX
A4
B4
C4
D4
E4
F4
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
Arithm etic Shift Left ( Same as LSL) ——
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
ff
5
3
3
6
5
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
Arithmetic Shift Right ——
DIR
INH
INH
IX1
IX
37
47
57
67
77
dd
ff
5
3
3
6
5
BCC rel Branch if Carry Bit Clear PC ← (PC) + 2 + rel ? C = 0 ————— REL 24 rr 3
BCLR n opr Clear Bit n Mn ← 0 —————
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
11
13
15
17
19
1B
1D
1F
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
BCS re l Branch if Carry Bit Set (Same as BLO) PC ← (PC) + 2 + rel ? C = 1 ————— REL 25 rr 3
BEQ rel Branch if Equal PC ← (PC) + 2 + rel ? Z = 1 ————— REL 27 rr 3
BHCC rel Branch if Half-Carry Bit Clear PC ← (PC) + 2 + rel ? H = 0 ————— REL 28 rr 3
BHCS rel Branch if Half-Carry Bit Set PC ← (PC) + 2 + rel ? H = 1 ————— REL 29 rr 3
Cb0
b7 0
b0
b7 C
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Central Processor Unit (CPU)
Ce ntral Processor Unit (CPU)
BHI rel Branch if H igher PC ← (PC) + 2 + rel ? C ∨ Z = 0 ————— REL 22 rr 3
BHS re l Branc h if Higher or Same PC ← (PC) + 2 + rel ? C = 0 ————— REL 24 rr 3
BIH re l Branch if IRQ Pin High PC ← (PC) + 2 + rel ? IRQ = 1 ————— REL 2F rr 3
BIL rel Branch if IRQ Pin Low PC ← (PC) + 2 + rel ? IRQ = 0 ————— REL 2E rr 3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
Bit Test Accumulator with Memory Byte (A) ∧ (M) ——
—
IMM
DIR
EXT
IX2
IX1
IX
A5
B5
C5
D5
E5
F5
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
BLO rel Branch if Lower (Same as BCS) PC ← (PC) + 2 + rel ? C = 1 ————— REL 25 rr 3
BLS rel Branch if Lower or Same PC ← (PC) + 2 + rel ? C ∨ Z = 1 ————— REL 23 rr 3
BMC rel Branch if Interrupt Mask Clear PC ← (PC) + 2 + rel ? I = 0 ————— REL 2C rr 3
BMI rel Branch if Minus PC ← (PC) + 2 + rel ? N = 1 ————— REL 2B rr 3
BMS rel Branch if Interrupt Mask Set PC ← (PC) + 2 + rel ? I = 1 ————— REL 2D rr 3
BNE re l Branch if Not Equal PC ← (PC) + 2 + rel ? Z = 0 ————— REL 26 rr 3
BPL rel Branch if Plus PC ← (PC) + 2 + rel ? N = 0 ————— REL 2A rr 3
BRA re l Branch Always PC ← (PC) + 2 + rel ? 1 = 1 ————— REL 20 rr 3
BRCLR n opr rel Branch if Bit n Clear PC ← (PC) + 2 + rel ? Mn = 0 ————
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01
03
05
07
09
0B
0D
0F
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BRN rel Branch Never PC ← (PC) + 2 + rel ? 1 = 0 ————— REL 21 rr 3
BRSET n opr rel Branch if Bit n Set PC ← (PC) + 2 + rel ? Mn = 1 ————
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
00
02
04
06
08
0A
0C
0E
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
5
5
5
5
5
5
5
5
BSET n opr Set Bit n Mn ← 1 —————
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
10
12
14
16
18
1A
1C
1E
dd
dd
dd
dd
dd
dd
dd
dd
5
5
5
5
5
5
5
5
Table 3-6. Instruction Set S ummary (Sheet 2 of 6)
Source
Form Operation Description Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
HINZC
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Instruction Set Summary
MC68HC705J1A —Rev. 4.0 Technical Data
Central Processor Unit (CPU)
BSR re l Branch to Subroutine
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
PC ← (PC) + rel
————— REL AD rr 6
CLC Clear Carry Bit C ← 0 ———— 0INH98 2
CLI Clear Interrupt Mask I ← 0 — 0 ——— INH 9A 2
CLR op r
CLRA
CLRX
CLR op r,X
CLR ,X
Clear Byte
M ← $00
A ← $0 0
X ← $0 0
M ← $00
M ← $00
—— 01—
DIR
INH
INH
IX1
IX
3F
4F
5F
6F
7F
dd
ff
5
3
3
6
5
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
Compare Accumulator with Memory Byte (A) – (M) ——
IMM
DIR
EXT
IX2
IX1
IX
A1
B1
C1
D1
E1
F1
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
COM op r
COMA
COMX
COM op r,X
COM ,X
Complement Byt e (One’s C omplement)
M ← (M) = $FF – (M)
A ← (A) = $FF – (A)
X ← (X) = $FF – (X)
M ← (M) = $FF – (M)
M ← (M) = $FF – (M)
——
1
DIR
INH
INH
IX1
IX
33
43
53
63
73
dd
ff
5
3
3
6
5
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
Compare Index Register with Memory Byte (X) – (M) ——
IMM
DIR
EXT
IX2
IX1
IX
A3
B3
C3
D3
E3
F3
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
DEC op r
DECA
DECX
DEC op r,X
DEC ,X
Decrement Byte
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
——
—
DIR
INH
INH
IX1
IX
3A
4A
5A
6A
7A
dd
ff
5
3
3
6
5
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EXCLUSIVE OR Accumulator with Memory Byte A ← (A) ⊕ (M) ——
—
IMM
DIR
EXT
IX2
IX1
IX
A8
B8
C8
D8
E8
F8
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
INC opr
INCA
INCX
INC opr,X
INC ,X
Inc rem ent Byt e
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
——
—
DIR
INH
INH
IX1
IX
3C
4C
5C
6C
7C
dd
ff
5
3
3
6
5
Table 3-6. Instruction Set S ummary (Sheet 3 of 6)
Source
Form Operation Description Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
HINZC
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Technical Data MC68HC705J1A —Rev. 4.0
Central Processor Unit (CPU)
Ce ntral Processor Unit (CPU)
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
Unconditional Jump PC ← Jump Address —————
DIR
EXT
IX2
IX1
IX
BC
CC
DC
EC
FC
dd
hh ll
ee ff
ff
2
3
4
3
2
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
Jump to Subroutine
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
—————
DIR
EXT
IX2
IX1
IX
BD
CD
DD
ED
FD
dd
hh ll
ee ff
ff
5
6
7
6
5
LDA #opr
LDA op r
LDA op r
LDA op r,X
LDA op r,X
LDA ,X
Load Accumulator with Memory Byte A ← (M) ——
—
IMM
DIR
EXT
IX2
IX1
IX
A6
B6
C6
D6
E6
F6
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
LDX #opr
LDX op r
LDX op r
LDX op r,X
LDX op r,X
LDX ,X
Loa d Index Regist er with Memo ry Byte X ← (M) ——
—
IMM
DIR
EXT
IX2
IX1
IX
AE
BE
CE
DE
EE
FE
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
LSL op r
LSLA
LSLX
LSL op r,X
LSL ,X
Logical Shif t Left (Same as AS L) ——
DIR
INH
INH
IX1
IX
38
48
58
68
78
dd
ff
5
3
3
6
5
LSR op r
LSRA
LSRX
LSR op r,X
LSR ,X
Logical Shif t R ight —— 0
DIR
INH
INH
IX1
IX
34
44
54
64
74
dd
ff
5
3
3
6
5
M UL Unsigned Multiply X : A ← (X) × (A) 0 ——— 0INH42 11
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
Negate Byte (T wo’s Complement)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
——
DIR
INH
INH
IX1
IX
30
40
50
60
70
dd
ff
5
3
3
6
5
NOP No Operation ————— INH 9D 2
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
Logical OR Accumulato r wi th Memor y A ← (A) ∨ (M) ——
—
IMM
DIR
EXT
IX2
IX1
IX
AA
BA
CA
DA
EA
FA
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
Table 3-6. Instruction Set S ummary (Sheet 4 of 6)
Source
Form Operation Description Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
HINZC
Cb0
b7 0
b0
b7 C0
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Central Processor Unit (CP U)
Instruction Set Summary
MC68HC705J1A —Rev. 4.0 Technical Data
Central Processor Unit (CPU)
ROL opr
ROLA
ROLX
ROL opr ,X
ROL ,X
Ro ta te Byte Le ft throug h Carry Bit ——
DIR
INH
INH
IX1
IX
39
49
59
69
79
dd
ff
5
3
3
6
5
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
Ro ta te Byte Righ t thro ugh Carr y Bit ——
DIR
INH
INH
IX1
IX
36
46
56
66
76
dd
ff
5
3
3
6
5
RSP Reset Stack Pointer SP ← $00FF ————— INH 9C 2
RTI Return from Interrupt
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pul l (PCH)
SP ← (SP) + 1; Pull (PCL)
INH 80 9
RTS Return from Subr outine SP ← (SP) + 1; Pul l (PCH)
SP ← (SP) + 1; Pull (PCL) ————— INH 81 6
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
Subtract Memory Byte and Carry Bit from
Accumulator A ← (A) – (M) – (C) ——
IMM
DIR
EXT
IX2
IX1
IX
A2
B2
C2
D2
E2
F2
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
SEC Set Carry Bit C ← 1 ———— 1INH99 2
SEI Set Interrupt Mask I ← 1 — 1 ——— INH 9B 2
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
Store Accumulator in M emory M ← (A) ——
—
DIR
EXT
IX2
IX1
IX
B7
C7
D7
E7
F7
dd
hh ll
ee ff
ff
4
5
6
5
4
STOP Stop Oscillator and Enable IRQ Pin — 0 ——— INH 8E 2
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
Store Index Register In Memory M ← (X) ——
—
DIR
EXT
IX2
IX1
IX
BF
CF
DF
EF
FF
dd
hh ll
ee ff
ff
4
5
6
5
4
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
Subtract Memory Byte from Accumulator A ← (A) – (M) ——
IMM
DIR
EXT
IX2
IX1
IX
A0
B0
C0
D0
E0
F0
ii
dd
hh ll
ee ff
ff
2
3
4
5
4
3
Table 3-6. Instruction Set S ummary (Sheet 5 of 6)
Source
Form Operation Description Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
HINZC
Cb0
b7
b0
b7 C
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Technical Data MC68HC705J1A —Rev. 4.0
Central Processor Unit (CPU)
Ce ntral Processor Unit (CPU)
3.8 Opcode Map
See Table 3-7.
SWI Software Interrupt
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interru p t Ve c tor Low Byte
— 1 ——— INH 83 10
TAX Trans fe r Accum u la tor to Inde x Reg is ter X ← (A) ————— INH 97 2
TST opr
TSTA
TSTX
TST opr,X
TST ,X
Test Memory Byte for Negative or Zero (M) – $00 ——
—
DIR
INH
INH
IX1
IX
3D
4D
5D
6D
7D
dd
ff
4
3
3
5
4
TXA Transfer Index Register to Accumulator A ← (X) ————— INH 9F 2
WAIT Stop CPU Clock and Enable Interrupts —
——— INH 8F 2
A Accumulator opr O peran d ( on e or tw o by te s)
C Carry/borrow flag PC Program counter
CCR Condition code register PCH Program counter high byte
dd Direct address of operand PC L Program counter low byte
dd rr Direc t address of operand and relative offset of branch instr uction REL Relative addressing mode
DI R Direct ad dressing mod e rel Relative program c ounter offset byte
ee ff High and low bytes of offset in indexed, 16-bit offset addressing rr Relative program counter offset byte
EXT Extended addressing mode SP Stack pointer
ff Offset byte in indexed, 8-b it offset addressing X Index register
H Half-carry flag Z Zero flag
hh ll High and low byt es of operan d address in extended addressi ng # Immediate v alue
I Inte rrupt mask ∧Logica l A ND
ii Immediate operand byte ∨Lo gi ca l O R
IMM Immediate addressing mode ⊕Logica l E XC L U SIV E OR
INH Inherent addressing mode ( ) Contents of
IX Indexed, no offset ad dressing mode –( ) Negatio n ( two’s compl ement)
IX1 Indexed, 8- bit offset addressin g mode ←Loaded with
IX2 Indexed, 16-bit offset add ressing mode ? If
M Memory location : Concatenated with
N Negative flag
Set or cleared
nAny bit —Not affected
Table 3-6. Instruction Set S ummary (Sheet 6 of 6)
Source
Form Operation Description Effect
on CCR
Address
Mode
Opcode
Operand
Cycles
HINZC
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MC68HC705J1A —Rev. 4.0 Technical Data
Central Processor Unit (CPU)
Central Processor Unit (CPU)
Opcode Map
Table 3-7. Opcode Map
Bit Manipulation Branch Read-Modify-Write Control Register/Memory
DIR DIR REL DIR INH INH IX1 IX INH INH IMM DIR EXT IX2 IX1 IX
0123456789ABCDEF
05
BRSET0
3DIR
5
BSET0
2DIR
3
BRA
2REL
5
NEG
2DIR
3
NEGA
1INH
3
NEGX
1INH
6
NEG
2IX1
5
NEG
1IX
9
RTI
1INH
2
SUB
2IMM
3
SUB
2DIR
4
SUB
3EXT
5
SUB
3IX2
4
SUB
2IX1
3
SUB
1IX
0
15
BRCLR0
3DIR
5
BCLR0
2DIR
3
BRN
2REL
6
RTS
1INH
2
CMP
2IMM
3
CMP
2DIR
4
CMP
3EXT
5
CMP
3IX2
4
CMP
2IX1
3
CMP
1IX
1
25
BRSET1
3DIR
5
BSET1
2DIR
3
BHI
2REL
11
MUL
1INH
2
SBC
2IMM
3
SBC
2DIR
4
SBC
3EXT
5
SBC
3IX2
4
SBC
2IX1
3
SBC
1IX
2
35
BRCLR1
3DIR
5
BCLR1
2DIR
3
BLS
2REL
5
COM
2DIR
3
COMA
1INH
3
COMX
1INH
6
COM
2IX1
5
COM
1IX
10
SWI
1INH
2
CPX
2IMM
3
CPX
2DIR
4
CPX
3EXT
5
CPX
3IX2
4
CPX
2IX1
3
CPX
1IX
3
45
BRSET2
3DIR
5
BSET2
2DIR
3
BCC
2REL
5
LSR
2DIR
3
LSRA
1INH
3
LSRX
1INH
6
LSR
2IX1
5
LSR
1IX
2
AND
2IMM
3
AND
2DIR
4
AND
3EXT
5
AND
3IX2
4
AND
2IX1
3
AND
1IX
4
55
BRCLR2
3DIR
5
BCLR2
2DIR
3
BCS/BLO
2REL
2
BIT
2IMM
3
BIT
2DIR
4
BIT
3EXT
5
BIT
3IX2
4
BIT
2IX1
3
BIT
1IX
5
65
BRSET3
3DIR
5
BSET3
2DIR
3
BNE
2REL
5
ROR
2DIR
3
RORA
1INH
3
RORX
1INH
6
ROR
2IX1
5
ROR
1IX
2
LDA
2IMM
3
LDA
2DIR
4
LDA
3EXT
5
LDA
3IX2
4
LDA
2IX1
3
LDA
1IX
6
75
BRCLR3
3DIR
5
BCLR3
2DIR
3
BEQ
2REL
5
ASR
2DIR
3
ASRA
1INH
3
ASRX
1INH
6
ASR
2IX1
5
ASR
1IX
2
TAX
1INH
4
STA
2DIR
5
STA
3EXT
6
STA
3IX2
5
STA
2IX1
4
STA
1IX
7
85
BRSET4
3DIR
5
BSET4
2DIR
3
BHCC
2REL
5
ASL/LSL
2DIR
3
ASLA/LSLA
1INH
3
ASLX/LSLX
1INH
6
ASL/LSL
2IX1
5
ASL/LSL
1IX
2
CLC
1INH
2
EOR
2IMM
3
EOR
2DIR
4
EOR
3EXT
5
EOR
3IX2
4
EOR
2IX1
3
EOR
1IX
8
95
BRCLR4
3DIR
5
BCLR4
2DIR
3
BHCS
2REL
5
ROL
2DIR
3
ROLA
1INH
3
ROLX
1INH
6
ROL
2IX1
5
ROL
1IX
2
SEC
1INH
2
ADC
2IMM
3
ADC
2DIR
4
ADC
3EXT
5
ADC
3IX2
4
ADC
2IX1
3
ADC
1IX
9
A5
BRSET5
3DIR
5
BSET5
2DIR
3
BPL
2REL
5
DEC
2DIR
3
DECA
1INH
3
DECX
1INH
6
DEC
2IX1
5
DEC
1IX
2
CLI
1INH
2
ORA
2IMM
3
ORA
2DIR
4
ORA
3EXT
5
ORA
3IX2
4
ORA
2IX1
3
ORA
1IX
A
B5
BRCLR5
3DIR
5
BCLR5
2DIR
3
BMI
2REL
2
SEI
1INH
2
ADD
2IMM
3
ADD
2DIR
4
ADD
3EXT
5
ADD
3IX2
4
ADD
2IX1
3
ADD
1IX
B
C5
BRSET6
3DIR
5
BSET6
2DIR
3
BMC
2REL
5
INC
2DIR
3
INCA
1INH
3
INCX
1INH
6
INC
2IX1
5
INC
1IX
2
RSP
1INH
2
JMP
2DIR
3
JMP
3EXT
4
JMP
3IX2
3
JMP
2IX1
2
JMP
1IX
C
D5
BRCLR6
3DIR
5
BCLR6
2DIR
3
BMS
2REL
4
TST
2DIR
3
TSTA
1INH
3
TSTX
1INH
5
TST
2IX1
4
TST
1IX
2
NOP
1INH
6
BSR
2REL
5
JSR
2DIR
6
JSR
3EXT
7
JSR
3IX2
6
JSR
2IX1
5
JSR
1IX
D
E5
BRSET7
3DIR
5
BSET7
2DIR
3
BIL
2REL
2
STOP
1INH
2
LDX
2IMM
3
LDX
2DIR
4
LDX
3EXT
5
LDX
3IX2
4
LDX
2IX1
3
LDX
1IX
E
F5
BRCLR7
3DIR
5
BCLR7
2DIR
3
BIH
2REL
5
CLR
2DIR
3
CLRA
1INH
3
CLRX
1INH
6
CLR
2IX1
5
CLR
1IX
2
WAIT
1INH
2
TXA
1INH
4
STX
2DIR
5
STX
3EXT
6
STX
3IX2
5
STX
2IX1
4
STX
1IX
F
INH = Inherent REL = Relative
IMM = Immediate IX = Indexe d, No Offset
DIR = Direct IX1 = Indexed, 8-Bit Offset
EXT = Extended IX2 = Indexed, 16-Bit Offset
0MSB of Opcode in Hexadecimal
LSB of Opc ode in H exadecimal 05
BRSET0
3DIR
Number of Cycles
Opcode Mnemo nic
Number of Bytes/Addressing Mode
LSBMSB LSB
MSB
LSB MSB
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Technical Data MC68HC705J1A —Rev. 4.0
Central Processor Unit (CPU)
Ce ntral Processor Unit (CPU)
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MC68HC705J1A —Rev. 4.0 Tec hnical Data
Resets and Interrupts
Technical Data — MC68HC705J1A
Section 4. Resets and Interrupts
4.1 Contents
4.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
4.3 Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
4.3.1 Power-On Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
4.3.2 External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
4.3.3 COP Watchdog Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
4.3.4 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
4.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
4.4.1 Software Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
4.4.2 External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
4.4.3 Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
4.4.3.1 Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
4.4.3.2 Timer Overflow Interrupt . . . . . . . . . . . . . . . . . . . . . . . . .76
4.4.4 Interrupt Processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 6
4.2 Introduction
Reset initializes the microcontroller un it (MCU) by returning the program
counter to a known address and by forcing control and status bits to
known states.
Interrupts temporarily change the sequence of program execution to
respond to events that occur during processing.
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Technical Data MC68HC705J1A —Rev. 4.0
Resets and Interrupts
Resets and In ter rupts
4.3 Resets
A reset immediately stops the operation of the instruction being
executed, initializes certain control and status bits, and loads the
program counter with a user-defined reset vector address. These
sources can generate a reset:
•Power-on reset (POR) circuit
•RESET pin
•Computer operating properly (COP) watchdog
•Illegal address
Figure 4-1. Reset Sources
DQ
CK
S
RESET
LATCH
INTERNAL CLOCK
RST TO CPU AND
RESET PIN
VDD
PERIPHERAL
MODULES
ILLEGAL ADDRESS
COP WATCHDOG
POWER-ON RESET
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Resets and Interrupts
Resets
MC68HC705J1A —Rev. 4.0 Technical Data
Resets and Interrupts
4.3.1 Power-On Reset
A positive transition on the VDD pin generates a power-on reset.
NOTE: The power-on reset is strictly for power-up conditions and cannot be
used to detect drops in power supply voltage.
A 4064-tcyc (internal clock cycle) delay after the oscillator becomes
active allows the clock generator to stabilize. If any reset source is active
at the end of this delay, the MCU remains i n the reset condition until all
reset sources are inactive.
Figure 4-2. Power-On Reset Timing
OSCILLATOR STABILIZATION DELAY
VDD
OSC1 PIN
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
Notes:
INTERNAL
DATA BUS
1. Power-on reset threshold is typically between 1 V and 2 V.
2. Internal clock, internal address bus, and internal data bus are not available externally.
$07FE $07FE $07FE $07FE $07FE $07FE $07FF
NEW PCH NEW PCL
(NOTE 1)
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Technical Data MC68HC705J1A —Rev. 4.0
Resets and Interrupts
Resets and In ter rupts
4.3.2 External Reset
A logic 0 applied to the RESET pin for 1 1/2 tcyc generates an external
reset. A Schmitt trigger senses the logic level at the RESET pin.
Figure 4-3. External Reset Timing
4.3.3 COP Watchdog Reset
A timeout of the COP watchdog generates a COP reset. The COP
watchdog is part of a software error detection system and must be
cleared periodically to start a new timeout period. To clear the COP
watchdog and prevent a COP reset, write a logic 0 to bit 0 (COPC) of the
COP register at location $07F0.
4.3.4 Illegal Address Reset
An opco de fetch from an address not in ra ndom-access m emory (RA M)
or erasable, programmable read-only memory (EPROM) generates a
reset.
Table 4-1. External Reset Timing
Characteristic Symbol Min Max Unit
RESET pulse width tRL 1.5 —tcyc
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
Notes:
INTERNAL
DATA BUS
$07FE $07FE $07FE $07FE $07FF NEW PC
1. Internal clock, internal addres s bus, and int ernal data bus are not available externally.
2. The next rising edge of the internal c lock after the rising edge of RESET initiates the reset sequence.
NEW
PCH
tRL
NEW PC
NEW
PCL DUMMY OP
CODE
RESET
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Resets and Interrupts
Interrupts
MC68HC705J1A —Rev. 4.0 Technical Data
Resets and Interrupts
4.4 Interrupts
These sources can generate interrupts:
•Software interrupt (SWI) instruction
•External interrupt pins:
– IRQ/VPP
–PA0–PA3
•Timer:
–Real-time interrupt flag (RTIF)
–Timer overflow flag (TOF)
An interrupt temporarily stops the program sequence to process a
particular event. An interrupt does not stop the operation of the
instructi on bein g exe cuted, but takes effect when the curre nt i n struction
completes its execution. Interrupt processing automatically saves the
CPU registers on the stack and loads the program counter with a
user-defined interrupt vector address.
4.4.1 Software Interrupt
The software interrupt (SWI) instruction causes a non-maskable
interrupt.
4.4.2 External Interrupt
An interrupt signal on the IRQ/VPP pin latches an external interrupt
request. When the CPU co mpletes its current instruction, it tests the IRQ
latch. If the IRQ latch is set, the CP U then tests the I bit in the condition
code register. If the I bit is clear, the CPU then begins the interrupt
sequence.
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Technical Data MC68HC705J1A —Rev. 4.0
Resets and Interrupts
Resets and In ter rupts
The CPU clears the IRQ latch during interrupt processing, so that
another interrupt signal on the IRQ /VPP pin can latch another interrupt
request during the interrupt service routine. As soon as the I bit is cleared
during the return from interrupt, the CPU can recognize the new interrupt
request. Figure 4-4 shows the IRQ/VPP pin interrupt logic.
Figure 4-4. External Interrup t Logic
Setting the I bit in the condition code register disables external interrupts.
The port A external interrupt bit (PIRQ) in the mask option register
enables pins PA0–PA3 to function as external interrupt pins.
The e xtern al inter rup t sen sitivity bit ( LE VEL) i n th e m ask op tion r egister
controls interrupt triggering sensitivity of external interrupt pins. The
IRQ/VPP pin can be negativ e-e dge trigg ered onl y or nega tive-ed ge and
low-level triggered. Port A external interrupt pins can be positive-edge
triggered onl y or both positive-edge and high-level triggered. The
leve l-sensiti ve trigge ri ng option allo ws multiple extern al interrupt
sources to be wire-ORed to an external interrupt pin. An external
inte rrupt requ est, shown in Figure 4-5, is latched as long as any source
is holding an external interrupt pin low.
PIRQ
LEVEL-SENSITIVE TRIGGER
PA3
PA2
PA1
IRQ
PA0
VDD
(MOR LEVEL BIT)
RESET
IRQ VECTOR FETCH
EXTERNAL
INTERRUPT
REQUEST
(MOR)
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQF
IRQR
IRQE
DQ
CK
IRQ
CLR
LATCH
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Resets and Interrupts
Interrupts
MC68HC705J1A —Rev. 4.0 Technical Data
Resets and Interrupts
Figure 4-5. External Interrupt Timing
Table 4-2. External Interrupt Timing (VDD = 5.0 Vd c)(1)
1. VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = –40°C to +1 0 5 °C, unless otherwise noted
Characteristic Symbol Min Max Unit
Interrupt pulse width low (edge-triggered ) tILIH 125 —ns
Interrupt pulse period tILIL Note(2)
2. The minimum, tILIL, should not be l ess than the number of interrupt service routine cycles
plus 19 tcyc.
—tcyc
Table 4-3. External Interrupt Timing (VDD = 3.3 Vd c)(1)
1. VDD = 3.3 Vdc ±10%, VSS = 0 Vdc, TA = –40°C to +1 0 5 °C, unless otherwise noted
Characteristic Symbol Min Max Unit
Interrupt pulse width low (edge-triggered ) tILIH 250 —ns
Interrupt pulse period tILIL Note(2)
2. The minimum, tILIL, should not be l ess than the number of interrupt service routine cycles
plus 19 tcyc.
—tcyc
IRQ (INTERNAL)
tILIH
tILIL
tILIH
IRQ PIN
IRQ1
IRQn
.
.
.
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Technical Data MC68HC705J1A —Rev. 4.0
Resets and Interrupts
Resets and In ter rupts
4.4.3 Timer Interrupts
The timer can generate these interrupt requests:
•Real time
•Timer overflow
Setting the I bit in the condition code register disables timer interrupts.
4.4.3.1 Real-Time Interrupt
A real-time interrupt occurs if the real-time interrupt flag, RTIF, becomes
set while the real-time interrupt enable bit, RTIE, is also set. RTIF and
RTIE are in the timer status and control register.
4.4.3.2 Timer Overflow Interrupt
A timer ove rflow interrupt request o ccurs if the timer overfl ow flag, TOF,
becomes set while the timer overflow interrupt enable bit, TOIE, is also
set. TOF and TOIE are in the timer status and control register.
4.4.4 Interrupt Processing
The CPU takes these actions to begin servicing an interrupt:
•Stores the CPU registers on the stack in the order shown in
Figure 4-6
•Sets the I bit in the condition code register to prevent further
interrupts
•Loads the program counter with the contents of the appropriate
interrupt vector locations:
–$07FC and $07FD (software interrupt vector)
–$07FA and $07FB (external interrupt vector)
–$07F8 and $07F9 (timer interrupt vector)
The return-from-interrupt (RTI) instruction causes the CPU to recover
the CPU registers from the stack as shown in Figure 4-6.
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Resets and Interrupts
Interrupts
MC68HC705J1A —Rev. 4.0 Technical Data
Resets and Interrupts
Figure 4-6. Interrupt Stacking Order
Table 4-4. Reset/Interrupt Vector Addresses
Function Source Local
Mask Global
Mask Priority
(1 = Highest) Vector
Address
Reset
Power-on
RESET pin
COP
watchdog(1)
illegal address
1. The COP watchdog is pr ogrammable in the mask opti on register.
None None 1 $07FE–$07FF
Software
interrupt
(SWI) User code None None Same priority
as instru ction $07FC–$07FD
External
interrupt IRQ/VPP pin IRQE I bit 2 $07FA–$07FB
Timer
interrupts RTIF bit
TOF bit RTIE bit
TOIE bit I bit 3 $07F8–$07F9
CONDITION CODE REGISTER
$00C0 (BOTTOM OF STACK)
$00C1
$00C2
•
•
•
ACCUMULATOR
INDEX REGISTER
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
•
•
•
•
•
•
•
•
•
$00FD
$00FE
$00FF (TOP OF STACK)
1
2
3
4
5
5
4
3
2
1
UNSTACKING
ORDER
STACKING
ORDER
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Technical Data MC68HC705J1A —Rev. 4.0
Resets and Interrupts
Resets and In ter rupts
Figure 4-7. Interrupt Flowchart
EXTERNAL
INTERRUPT?
I BIT SET?
TIMER
INTERRUPT?
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
RTI
INSTRUCTION?
STACK PC, X, A, CCR
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
YES
YES
YES
YES
YES UNSTACK CCR, A, X, PC
EXECUTE INSTRUCTION
CLEAR IRQ LATCH
NO
NO
NO
NO
NO
FROM RESET
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MC68HC705J1A —Rev. 4.0 Tec hnical Data
Low-Power Modes
Technical Data — MC68HC705J1A
Section 5. Low-Power Modes
5.1 Contents
5.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
5.3 Exiting Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . . . .80
5.4 Effects of Stop and Wait Modes . . . . . . . . . . . . . . . . . . . . . . . .81
5.4.1 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81
5.4.2 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
5.4.3 COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
5.4.4 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
5.4.5 EPROM/OTPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
5.4.6 Data-Retention Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
5.5 Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
5.2 Introduction
The microcontroller unit (MCU) can enter these low-power standby
modes:
•Stop mode — The STOP instruction puts the MCU in its lowest
power-consumption mode.
•Wait mode — The WAIT instruction puts the MCU in an
intermediate power-consumption mode.
•Halt mode — Halt mode is identical to wait mode, except that an
oscillator stabilization delay of 1 to 4064 internal clock cycles
occurs when the MCU exits halt mode. The stop-to-wait
conversion bit, SWAIT, in the mask option register, enables halt
mode.
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Technical Data MC68HC705J1A —Rev. 4.0
Low-Power Modes
Low-Power Modes
Enabling halt mode prevents the computer operating properly
(COP) wa tchdog from being inadvertently turned off by a STOP
instruction.
•Data-retention mode — In data-retention mode, the MCU retains
RAM contents and CPU register contents at VDD voltages as low
as 2.0 Vdc. The data-retention feature allows the MCU to remain
in a low power-consu mption state du ring which it retains data, but
the CPU cannot execute in structions.
5.3 Exiting Stop and Wait M odes
The events described in this subsection bring the MCU out of stop mode
and load the program counter with the reset vector or with an interrupt
vector.
Exiting stop mode:
•External reset — A logic 0 on the RESET pin resets the MCU,
starts the CPU clock, and l oads the program counter with the
contents of locations $07FE and $07FF.
•External interrupt — A high-to-low transition on the IRQ/VPP pin or
a l ow-to-high transit io n on an enabled por t A exte rnal interr upt pi n
starts the CPU clock and loads the program counter with the
contents of locations $07FA and $07FB.
Exiting wait mode:
•External reset — A logic 0 on the RESET pin resets the MCU,
starts the CPU clock, and l oads the program counter with the
contents of locations $07FE and $07FF.
•External interrupt — A high-to-low transition on the IRQ/VPP pin or
a l ow-to-high transit io n on an enabled por t A exte rnal interr upt pi n
starts the CPU clock and loads the program counter with the
contents of locations $07FA and $07FB.
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Low-Power Modes
Effects of St op and Wai t Modes
MC68HC705J1A —Rev. 4.0 Technical Data
Low-Power Modes
•COP watchdog reset — A timeout of the COP watchdog resets the
MCU, starts the CPU clock, and loads the program counter with
the contents of loca tions $07FE and $07FF. Softw are can enable
timer interrupts so that the MCU periodically can exit wait mode to
reset the COP watchdog.
•Ti mer int errupt — Real-ti me interr upt requests an d timer overfl ow
interrupt requests start the MCU clock and load the program
counter with the contents of locations $07F8 and $07F9.
5.4 Effects of St op and Wait Mo des
The STOP and WAIT instructions have the effects described in this
subsection on MCU modules.
5.4.1 Clock Generation
The STOP instruction:
The STOP in struction disables the internal oscillator, stopping the
CPU clock and all peripheral clocks.
After exiting stop mode, the CPU clock and all enabled peripheral
clocks begin running after the oscillator stabilization delay.
NOTE: The oscillator stabilization delay holds the MCU in reset for the first 4064
internal clock cycles.
The WAIT instru ction:
The WAIT instruction disables the CPU clock.
After exiting wait mode, the CPU clock and all enabled peripheral
clocks immediately begin r u nning.
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Technical Data MC68HC705J1A —Rev. 4.0
Low-Power Modes
Low-Power Modes
5.4.2 CPU
The STOP instruction:
•Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts
•Disables the CPU clock
After exiting stop mode, the CPU clock begins running after the
oscillator stabilization delay.
After ex it from stop mo de by e xternal int errupt, the I bit rema ins clear.
After exit from stop mode by reset, the I bit is set.
The WAIT instru ction:
•Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts
•Disables the CPU clock
After exit from wait mode by interrupt, the I bit remains clear.
After exit from wait mode by reset, the I bit is set.
5.4.3 COP Watchdog
The STOP instruction:
•Clears the COP watchdog counter
•Disables the COP watchdog clock
NOTE: To prevent the STOP instruction from disabling the COP watchdog,
program the stop-to-wait conversion bit (SWAIT) in the mask option
register to logic 1.
After exit from stop mode by external interr upt, the COP watchdog
counter immediately begins counting from $0000 and continues
counting throughout the oscillator stabilization delay.
NOTE: Immediately after exiting stop mode by external interrupt, service the
COP to ensure a full COP timeout period.
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Low-Power Modes
Effects of St op and Wai t Modes
MC68HC705J1A —Rev. 4.0 Technical Data
Low-Power Modes
After exit from stop mode by reset:
•The COP watchdog counter immediately begins counting from
$0000.
•The COP watchdo g counter is cleared at the end of the oscillator
stabilization delay and begins counting from $0000 again.
The WAIT instru ction:
The WAIT instruction has no effect on the COP watchdog.
NOTE: T o prevent a COP timeo ut du ring wait mode, exit wa it mod e periodi cally
to service the COP.
5.4.4 Timer
The STOP instruction:
•Clears the RTIE, TOFE, RTIF, and TOF bits in the timer status and
control register, disabling timer interrupt requests and removing
any pending timer interrupt requests
•Disables the clock to the timer
After exiting stop mode by external interrupt, the timer immediately
resumes counting from the last value before the STOP instruction and
continues counting throughout the oscillator stabilization delay.
After exiting stop mode by reset and after the oscillator stabilization
delay, the timer resumes oper ation from its reset state.
The WAIT instru ction:
The WAIT instruction has no effect on the timer.
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Technical Data MC68HC705J1A —Rev. 4.0
Low-Power Modes
Low-Power Modes
5.4.5 EPROM/OTPROM
The STOP instruction:
The ST OP instruction during erasable, programmable read-only
memor y (E P ROM) p rogr amm ing cl ear s the EP GM b it in the EP ROM
programming register, removing the programming voltage from the
EPROM.
The WAIT instru ction:
The WAIT instruction has no effect on EPROM/one-time
programmable read-only memory (OTPROM) operation.
5.4.6 Data-Retention Mode
In data-retention mode, the MCU retains random-access memory (RAM)
contents and CP U registe r conten ts at VDD volta ges as low as 2.0 Vdc.
The data-retention feature allows the MCU to remain in a low
power-consumption state during which it retains data, but the CPU
cannot execute instructions.
To put the MCU in data-retention mode:
1. Drive the RESET pin to logic 0.
2. Lower the VDD voltage. The RESET pin must remain low
cont inuou sly during data-ret ention mode .
To take the MCU out of data-retention mode:
1. Return VDD to normal operating voltage.
2. Return the RESET pin to logic 1.
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Low-Power Modes
Timing
MC68HC705J1A —Rev. 4.0 Technical Data
Low-Power Modes
5.5 Timing
Figure 5-1. Stop Mode Recovery Timing
tILIH
OSCILLATOR STABILIZATION DELAY
OSC
tRL
RESET
IRQ/VPP
IRQ/VPP
INTERNAL
CLOCK
INTERNAL
ADDRESS
Notes:
1. Intern al clock in g fro m OSC1 pi n
2. Edge-triggered external interrupt mask option
3. Edge- and level-triggered external interrupt mask option
4. R eset vector shown as example
RESET OR INTERRUPT
VECTOR FETCH
$07FE $07FE $07FE $07FE $07FE $07FF
(NOTE 4)
BUS
(NOTE 3)
(NOTE 2)
(NOTE 1)
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Technical Data MC68HC705J1A —Rev. 4.0
Low-Power Modes
Low-Power Modes
Figure 5-2. Stop/Halt/Wait Flowchart
STOP
SWAIT
BIT SET?
CLEAR I BIT IN CCR
SET IRQE BIT IN ISCR
CLEAR TOF, RTIF, TOIE, AND RTIE BITS IN TSCR
TURN OFF INTERNAL OSCILLATOR
EXTERNAL
RESET?
EXTERNAL
INTERRUPT?
NO
NO
NO
TURN ON INTERNAL OSCILLATOR
RESET STABILIZATION TIMER
YES
YES
HALT
YES
END OF
STABILIZATION
DELAY?
YES
NO
YES
NO
NO
NO
COP
RESET?
TIMER
INTERRUPT?
EXTERNAL
INTERRUPT?
EXTERNAL
RESET?
CLEAR I BIT IN CCR
SET IRQE BIT IN ISCR
TURN OFF CPU CLOCK
TIMER CLOCK ACTIVE
YES
YES
YES
YES
NO
NO
NO
CLEAR I BIT IN CCR
SET IRQE BIT IN ISCR
TURN OFF CPU CLOCK
TIMER CLOCK ACTIVE
YES
YES
YES
NO NO
TURN ON CPU CLOCK
1. LOAD PC WITH RESET VECTOR
OR
2. SERVICE INTERRUPT
a. SAVE CPU REGISTERS ON STACK
b. SET I BIT IN CCR
c. LOAD PC WITH INTERRUPT VECTOR
EXTERNAL
RESET?
WAIT
EXTERNAL
INTERRUPT?
TIMER
INTERRUPT?
COP
RESET?
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MC68HC705J1A —Rev. 4.0 Tec hnical Data
Parallel Input/Output (I/O) Ports
Technical Data — MC68HC705J1A
Section 6. Parallel Input/Output (I/O) Ports
6.1 Contents
6.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
6.3 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
6.3.1 Port A Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 9
6.3.2 Data Direction Register A. . . . . . . . . . . . . . . . . . . . . . . . . . .90
6.3.3 Pulldown Register A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91
6.3.4 Port A LED Drive Capability. . . . . . . . . . . . . . . . . . . . . . . . .92
6.3.5 Port A I/O Pi n Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2
6.4 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92
6.4.1 Port B Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2
6.4.2 Data Direction Register B. . . . . . . . . . . . . . . . . . . . . . . . . . .93
6.4.3 Pulldown Register B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
6.5 5.0-Volt I/O Port Electrical Characteristics . . . . . . . . . . . . . . . .95
6.6 3.3-Volt I/O Port Electrical Characteristics . . . . . . . . . . . . . . . .95
6.2 Introduction
Fourteen bidirectional pins form one 8-bit input/output (I/O) port and one
6-bit I/O port. Al l the bidirectional port pins are pro grammable as inputs
or outputs.
NOTE: Con nect any unused I/O pins to an app ropriate logic lev el, either VDD or
VSS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
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Technical Data MC68HC705J1A —Rev. 4.0
Parallel Input/Output (I/ O) Ports
Parallel Input/Output (I/O) Ports
Addr.Register Name Bit 7654321Bit 0
$0000
Port A Data Register
(PORTA)
See page 89.
Read:
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Write:
Reset: Unaffected by reset
$0001
Port B Data Register
(PORTB)
See page 92.
Read: 0 0
PB5 PB4 PB3 PB2 PB1 PB0
Write:
Reset: Unaffected by reset
$0004
Data Direction Register A
(DDRA)
See page 90.
Read:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset:00000000
$0005
Data Direction Register B
(DDRB)
See page 93.
Read: 0 0
DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset:00000000
$0010
Pulldown Register A
(PDRA)
See page 91.
Read:
Write: PDIA7 PDIA6 PDIA5 PDIA4 PDIA3 PDIA2 PDIA1 PDIA0
Reset:00000000
$0011
Pulldown Register B
(PDRB)
See page 94.
Read:
Write: PDIB5 PDIB4 PDIB3 PDIB2 PDIB1 PDIB0
Reset: 000000
= Unimplemented
Figure 6-1. Parallel I/O Port Register Summary
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Parallel Input/Output (I/ O) Ports
Port A
MC68HC705J1A —Rev. 4.0 Technical Data
Parallel Input/Output (I/O) Ports
6.3 Port A
Port A is an 8-bit bidirectional port.
6.3.1 Port A Data Register
The port A data register (PORTA) contains a latch for each port A pin.
PA[7:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of
each port A pin is under the control of the corresponding bit in data
direction register A. Reset has no effect on port A data.
Address: $0000
Bit 7654321Bit 0
Read:
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Write:
Reset: Unaffected by reset
Figure 6-2. Port A Data Register (PORTA)
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Technical Data MC68HC705J1A —Rev. 4.0
Parallel Input/Output (I/ O) Ports
Parallel Input/Output (I/O) Ports
6.3.2 Data Direction Register A
Data direction register A (DDRA) determines whether e ach port A pin is
an input or an output.
DDRA[7:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears
DDRA[7:0], configuring all port A p ins as inp uts.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: A void glitch es on port A pi ns by writing to the p ort A data register befo re
changing data direction register A bits from 0 to 1.
Figure 6-4 shows the I/O logic of port A.
Figure 6-4. Port A I/O Circuitry
Address: $0004
Bit 7654321Bit 0
Read:
DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Write:
Reset:00000000
Figure 6-3. Data Direction Register A (DDRA)
READ DDRA
WRITE DDRA
RESET
WRITE PORTA
READ PORTA
PAx
INTERNAL DATA BUS
DDRAx
PAx
PDRAx
SWPDI
100-µA
PULLDOWN
(PA0–PA3 TO
IRQ MODULE)
WRITE PDRA
10-mA SINK CAPABILITY
(PINS PA4–PA7 ONLY)
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Parallel Input/Output (I/ O) Ports
Port A
MC68HC705J1A —Rev. 4.0 Technical Data
Parallel Input/Output (I/O) Ports
Writing a logic 1 to a DDRA bit enables the output buffer for the
corresponding port A pin; a logic 0 disables the output buffer.
When bit DDRAx is a logic 1, reading address $0000 reads the PAx data
latch. When bit DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the sta te of its dat a d i rection bit. Table 6-1 s ummarizes the ope ration
of the port A pins.
6.3.3 Pulldown Register A
Pull down registe r A (PD RA) inhib its the p ulldown d evices on por t A pins
programmed as inputs.
NOTE: If the SWPDI bit in the mask op tion register is programmed to logic 1,
reset initializes all port A pins as inputs with disabled pulldown devices.
PDIA[7:0] — Pulldown Inhibit A Bits
PDIA[7:0] disable the port A pulldown devices. Reset clears
PDIA[7:0].
1 = Corresponding port A pulldown device disabled
0 = Corresponding port A pulldown device not disabled
Table 6-1. Port A Pin Operation
Data Direction Bit I/O Pin Mode Accesses to Data Bit
Read Write
0 Input, high-impedanc e Pin Latch(1)
1. Writ ing affects the da ta register but does not aff ect input.
1 Output Latch Latch
Address: $0010
Bit 7654321Bit 0
Read:
Write: PDIA7 PDIA6 PDIA5 PDIA4 PDIA3 PDIA2 PDIA1 PDIA0
Reset:00000000
= Unimplemented
Figure 6-5. Pu lldown Register A (PDRA)
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Technical Data MC68HC705J1A —Rev. 4.0
Parallel Input/Output (I/ O) Ports
Parallel Input/Output (I/O) Ports
6.3.4 Port A LED Drive Capability
The outputs for the upper four bits of port A (PA4–PA7) can drive
light-emitting diodes (LEDs). PA4–PA7 can sink approximately 10 mA of
current to VSS.
6.3.5 Port A I/O Pin Interrupts
If the PIRQ bit in the mask option register is programmed to logic 1,
PA0–PA3 pins function as external interrupt pins. See Section 8.
External Interrupt Module (IRQ).
6.4 Port B
Port B is a 6-bit bidirectional port.
6.4.1 Port B Data Register
The port B data register (PORTB) contains a latch for each port B pin.
PB[5:0] — Port B Data Bits
These read/write bits are software programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.
Address: $0001
Bit 7654321Bit 0
Read: 0 0
PB5 PB4 PB3 PB2 PB1 PB0
Write:
Reset: Unaffected by reset
= Unimplemented
Figure 6-6. Port B Data Register (PORTB)
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Parallel Input/Output (I/ O) Ports
Port B
MC68HC705J1A —Rev. 4.0 Technical Data
Parallel Input/Output (I/O) Ports
6.4.2 Data Direction Register B
Data direction register B (DDRB) determines whether e ach port B pin is
an input or an output.
DDRB[5:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[5:0], configuring all port B p ins as inp uts.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE: A void glitch es on port B pi ns by writing to the p ort B data register befo re
changing data direction register B bits from 0 to 1.
Figure 6-8 shows the I/O logic of port B.
Figure 6-8. Port B I/O Circuitry
Address: $0005
Bit 7654321Bit 0
Read: 0 0
DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
Write:
Reset:00000000
= Unimplemented
Figure 6-7. Data Direction Register B (DDRB)
READ DDRB
WRITE DDRB
RESET
WRITE PORTB
READ PORTB
PBx
INTERNAL DATA BUS
DDRBx
PBx
PDRBx
SWPDI
100-µA
PULLDOWN
WRITE PDRB
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Technical Data MC68HC705J1A —Rev. 4.0
Parallel Input/Output (I/ O) Ports
Parallel Input/Output (I/O) Ports
Writing a logic 1 to a DDRB bit enables the output buffer for the
corresponding port B pin; a logic 0 disables the output buffer.
When bit DDRBx is a logic 1, reading address $0001 reads the PBx data
latch. When bit DDRBx is a logic 0, reading address $0001 reads the
voltage level on the pin. The data latch can always be written, regardless
of the sta te of its dat a d i rection bit. Table 6-2 s ummarizes the ope ration
of the port B pins.
6.4.3 Pulldown Register B
Pull down registe r B (PD RB) inhib its the p ulldown d evices on por t B pins
programmed as inputs.
NOTE: If the SWPDI bit in the mask op tion register is programmed to logic 1,
reset initializes all port B pins as inputs with disabled pulldown devices.
PDIB[7:0] — Pulldown Inhibit B Bits
PDIB[7:0] disable the port B pulldown devices. Reset clears
PDIB[7:0].
1 = Corresponding port B pulldown device disabled
0 = Corresponding port B pulldown device not disabled
Table 6-2. Port B Pin Operation
Data Direction Bit I/O Pin Mode Accesses to Data Bit
Read Write
0 Input, high-impedanc e Pin Latch(1)
1. Writ ing affects the da ta register, but does not affect input .
1 Output Latch Latch
Address: $0011
Bit 7654321Bit 0
Read:
Write: PDIB5 PDIB4 PDIB3 PDIB2 PDIB1 PDIB0
Reset: 000000
= Unimplemented
Figure 6-9. Pu lldown Register B (PDRB)
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Parallel Input/Output (I/ O) Ports
5.0-Volt I/O Port Electrical Characteristics
MC68HC705J1A —Rev. 4.0 Technical Data
Parallel Input/Output (I/O) Ports
6.5 5.0-Volt I/O Port Electrical Characteristics
6.6 3.3-Volt I/O Port Electrical Characteristics
Characteristic(1)
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +1 05°C, un les s otherwise noted
Symbol Min Typ(2)
2. Typical values r eflect average m easurements at midpoint of volta ge range, 25°C.
Max Unit
Current drain per pin exc luding PA4–PA7 I —25 —mA
Out put high voltage
(ILoad = –0.8 mA) PA0–PA7, PB0–PB5 VOH VDD –0.8 ——V
Out put low voltage
(ILoad = 1.6 mA) PA0–PA3, PB0–PB5
(ILoad = 10.0 m A ) PA4 –PA7 VOL —
——
—0.4
0.4 V
Input high voltage
PA0–PA7, PB0–PB5 VIH 0.7 x VDD —VDD V
Input low voltage
PA0–PA7, PB0–PB5 VIL VSS —0.2 x VDD V
I/O ports hi-z leakage current
PA0–PA7, PB0–PB5 (w ithout individual pulldown activated) IIL —0.2 ±1µA
Input pulldown current
PA0–PA7, PB0–P B5 (with indiv i dual pulldown activated) IIL 35 80 200 µA
Characteristic(1)
1. VDD = 3.3 Vdc ± 10%, VSS= 0 Vdc, TA = –40°C to +105°C, unless otherwise noted
Symbol Min Typ(2)
2. Typical values r eflect average m easurements at midpoint of volta ge range, 25°C.
Max Unit
Current drain per pin exc luding PA4–PA7 I —25 —mA
Output hi gh voltage
(ILoad = –0.2 mA) PA0–PA7, PB0–PB5 VOH VDD –0.3 ——V
Output l ow voltage
(ILoad = 0.4 mA) PA0–PA3, PB0–PB5
(ILoad = 5.0 mA) PA4–PA7 VOL —
——
—0.3
0.3 V
Input high volt age
PA0–PA7, PB0–PB5 VIH 0.7 x VDD —VDD V
Input low voltage
PA0–PA7, PB0–PB5 VIL VSS —0.2 x VDD V
I/O ports hi-z leakage current
PA0–PA7, PB0–PB5 (w ithout individual pulldown activated) IIL —0.1 ±1µA
Input pulld own current
PA0–PA7, PB0–P B5 (with indiv i dual pulldown activated) IIL 12 30 100 µA
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Technical Data MC68HC705J1A —Rev. 4.0
Parallel Input/Output (I/ O) Ports
Parallel Input/Output (I/O) Ports
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MC68HC705J1A —Rev. 4.0 Tec hnical Data
Computer Operat ing Properly (COP) Module
Technical Data — MC68HC705J1A
Section 7. Computer Operating Properly (COP) Module
7.1 Contents
7.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
7.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
7.3.1 COP Watchdog Timeout . . . . . . . . . . . . . . . . . . . . . . . . . . .98
7.3.2 COP Watchdog Timeout Period. . . . . . . . . . . . . . . . . . . . . .98
7.3.3 Clearing the COP Watchdog . . . . . . . . . . . . . . . . . . . . . . . .9 8
7.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.5 COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
7.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
7.6.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
7.6.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
7.2 Introduction
The computer operating properly (COP) watchdog resets the
microcontroller (MCU) in case of software failur e. Software that is
operating properly periodically services the COP watchdog and prevents
COP reset. The COP watchdog function is programmable by the
COPEN bit in the mask option register.
Features include:
•Protection from runaway software
•Wait and halt mode operation
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Technical Data MC68HC705J1A —Rev. 4.0
Computer Operating Properly (COP) Module
Compute r Operating Properly (COP) Module
7 .3 Operati on
Operation of the COP is described in this subsection.
7.3.1 COP Watchdog Timeout
Four counter stages at the end of the timer make up the COP watchdog.
The COP resets the MCU if the timeout period occurs before the COP
watchdog timer is cleared by application software and the IRQ/VPP pin
voltage is between VSS and VDD. Periodically clearing the counter start s
a new timeout period and prevents COP reset. A COP watchdog timeout
indicates that the software is not executing instructions in the correct
sequence.
NOTE: The internal clock drives the COP watchdog. Therefore, the COP
watchdog cannot generate a reset for errors that cause the internal clock
to stop.
The COP watchdog depends on a power supply voltage at or above a
minimum specification and is not guaranteed to protect against
brownout.
7.3.2 COP Watchdog Timeout Period
The C OP wa tchdog time r function is imple mented by dividi ng the output
of the rea l-time int err upt circui t ( RTI) by eight. T he RTI se lect bits i n the
timer status and control register control RTI output, and the selected
output drives the COP watchdog. See timer status and control register
in Section 9. Multifunction Timer Module.
NOTE: The minimum COP timeout period is seven times the RTI period. The
COP i s cleared a synchronously wi th the value in the R TI divider ; hence,
the COP timeout period will vary between 7x and 8x the RTI period.
7.3.3 Clearing the COP Watchdog
To clear the COP watchdog and prevent a COP reset, write a logic 0 to
bit 0 (COPC) of the COP register at location $07F0 (see Figure 7-1).
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Computer Operat ing Properly (COP) Module
Interrupts
MC68HC705J1A —Rev. 4.0 Technical Data
Computer Operat ing Properly (COP) Module
Clearing the COP bit disables the COP watchdog timer regardless of the
IRQ/VPP pin voltage.
If the main program executes within the COP timeout period, the clearing
routi ne should be e xecuted onl y o nce. If the main pro gram take s longe r
than the COP timeout period, the clearing routine must be executed
more than once.
NOTE: Place the clearing routine in the main program and not in an interrupt
routine. Clearing the COP watchdog in an interrupt routine might prevent
COP watchdog timeouts even th ough the main program is not operating
properly.
7.4 Interrupts
The COP watchdog does not generate interrupts.
7.5 COP Register
The COP register (COPR) is a write-only register that returns the
contents of EPROM location $07F0 when read.
COPC — COP Clear Bit
This write-only bit resets the COP watchdog. Reading address $07F0
returns undefined results.
Address: $07F0
Bit 7654321Bit 0
Read:
Write: COPC
Reset: 0
= Unimplemented
Figure 7-1. COP Register (COPR)
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Technical Data MC68HC705J1A —Rev. 4.0
Computer Operating Properly (COP) Module
Compute r Operating Properly (COP) Module
7.6 Low-Power Modes
The STOP and WAIT instructions have these effects on the COP
watchdog.
7.6.1 Stop Mode
The STOP in struction clears the COP watchdog counter and disables
the clock to the COP watchdog.
NOTE: To prevent the STOP instruction from disabling the COP watchdog,
program the stop-to-wait conversion bit (SWAIT) in the mask option
register to logic 1.
Upon exit from stop mode by external reset:
•The counter begins counting from $0000.
•The counter is clear ed a gain after t he oscillator sta bilization delay
and begins counting from $0000 again.
Upon exit from stop mode by external interrupt:
•The counter begins counting from $0000.
•The counter is not cleared again after the oscillator stabilization
delay and continues counting throughout the oscillator
stabilization delay.
NOTE: Immediately after exiting stop mode by external interrupt, service the
COP to ensure a full COP timeout period.
7.6.2 Wait Mode
The WAIT instruction has no effect on the COP watchdog.
NOTE: T o prevent a COP timeo ut du ring wait mode, exit wa it mod e periodi cally
to service the COP.
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MC68HC705J1A —Rev. 4.0 Tec hnical Data
External Interrupt Module (IRQ)
Technical Data — MC68HC705J1A
Section 8. External Interrupt Module (IRQ)
8.1 Contents
8.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
8.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
8.3.1 IRQ/VPP Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
8.3.2 Optional External Interrupts . . . . . . . . . . . . . . . . . . . . . . . .104
8.4 IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . .106
8.5 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .107
8.5.1 5.0-Volt External Interrupt Timing Characteristics . . . . . . .107
8.5.2 3.3-Volt External Interrupt Timing Characteristics . . . . . . .107
8.2 Introduction
The external interrupt (IRQ) module provides asynchronous external
interrupts to the CPU. These sources can generate external interrupts:
• IRQ/VPP pin
•PA0–PA3 pins
Features include:
•Dedicated external inte rrupt pin (IRQ/VPP)
•Selectable interrupt on four input/output (I/O) pins (PA0–PA3)
•Programmable edge-only or edge- and level-interrupt sensitivity
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Technical Data MC68HC705J1A —Rev. 4.0
External Interrupt Module (IRQ)
External Interrupt Module (IRQ)
8 .3 Operati on
The interrupt request/programming voltage pin (IRQ/VPP) and port A
pins 0–3 (PA0–PA3) provide external interrupts. The PIRQ bit in the
mask option register (MOR) enables PA0–PA3 as IRQ interrupt sources,
which are combined into a single ORing function to be latched by the
IRQ latch. Figure 8-1 shows the structure of the IRQ module.
After completing its current instruction, the CPU tests the IRQ latch. If the
IRQ latch is set, the CPU then tests the I bit in the condition code register
and the IRQE bit in the IRQ status and control register. If the
I bit is clear and the IRQE bit is set, the CPU then begins the interrupt
sequence. This interrupt is serviced by the interrupt service routine
located at $07FA and $07FB.
The CPU clears the IRQ latch while it fetches the interrupt vector, so that
another external interrupt request can be latched during the interrupt
service routine. As soon as the I bit is cleared during the return from
interrupt, the CPU can recognize the new interrupt request. Figure 8-2
shows the sequence of events caused by an interrupt.
Figure 8-1. IRQ Module Block Diagram
PIRQ
LEVEL-SENSITIVE TRIGGER
PA3
PA2
PA1
IRQ
PA0
VDD
(MOR LEVEL BIT)
RESET
IRQ VECTOR FETCH
EXTERNAL
INTERRUPT
REQUEST
(MOR)
TO BIH & BIL
INSTRUCTION
PROCESSING
IRQF
IRQR
IRQE
DQ
CK
IRQ
CLR
LATCH
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External Interrupt Module (IRQ)
Operation
MC68HC705J1A —Rev. 4.0 Technical Data
External Interrupt Module (IRQ)
Figure 8-2. Interrupt Flowchart
EXTERNAL
INTERRUPT?
I BIT SET?
TIMER
INTERRUPT?
FETCH NEXT
INSTRUCTION
SWI
INSTRUCTION?
RTI
INSTRUCTION?
STACK PCL, PCH, X, A, CCR
SET I BIT
LOAD PC WITH INTERRUPT VECTOR
YES
YES
YES
YES
YES UNSTACK CCR, A, X, PCH, PCL
EXECUTE INSTRUCTION
CLEAR IRQ LATCH
NO
NO
NO
NO
NO
FROM RESET
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Technical Data MC68HC705J1A —Rev. 4.0
External Interrupt Module (IRQ)
External Interrupt Module (IRQ)
8.3.1 IRQ/VPP Pin
An interrupt signal on the IRQ/VPP pin latches an external interrupt
request. The LEVEL bit in the mask option register provides negative
edge-sensitive triggering or both negative edge-sensitive and low
level-sensitive triggering for the interrupt function.
If edge- and level- sensitive triggering is selected, a falling edge or a low
level on the IRQ/VPP pin latches an external interrupt request. Edge- and
level-sensitive triggering allows the use of multiple wired-OR external
interrupt sources. An external interrupt request is latched as long as any
source is holding the IRQ/VPP pin low.
If level-sensitive triggering is selected, the IRQ/VPP input requires an
external resistor to VDD for wired- OR operat ion. I f the IRQ/VPP pin is no t
used, it must be tied to the VDD supply.
If edge-sensitive-only triggering is selected, a falli ng edge on the
IRQ/VPP pin latches an external interrupt request. A subsequent external
interrupt request can be latched only after the voltage level on the
IRQ/VPP pin returns to logic 1 and then falls again to lo gic 0.
The IRQ/VPP pin contains an internal Schmitt trigger as part of its input
to im prove noise immunity. The voltage on this pin can affect the mode
of operation and should not exceed VDD.
8.3.2 Optional External Interrupts
The inp uts for the low er fou r bits of por t A (P A0–PA3) can be conne cted
to the IRQ pin input of the CPU if enabled by the P IRQ bit in the mask
opti on register . This capa bility allows keyboard scan applicati ons wher e
the transitions or levels on the I/O pins will b ehave the same as the
IRQ/VPP pin except for the inverted phase (logic 1, rising edge). The
active state of the IRQ/VPP pin is a logic 0 (falling edge).
The PA0–PA3 pins are selected as a grou p to function as IRQ interrupts
and are enabled by the IRQE bit in the IRQ status and control register.
The P A0–PA3 pi ns can b e positive-ed ge trigger ed only or positive -edge
and high-level triggered.
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External Interrupt Module (IRQ)
Operation
MC68HC705J1A —Rev. 4.0 Technical Data
External Interrupt Module (IRQ)
If edge - and l evel-sensitiv e trigger ing is sel ected, a risin g edge or a high
level on a PA0–PA3 pin latches an external interru pt request. Edge- and
level-sensitive triggering allows the use of multiple wired-OR external
inte rrupt so urces. As l ong as any source is hol ding a PA0–PA3 pin high ,
an external interrupt request is latched, and the CPU continues to
execute the interrupt service routine.
If edge-sensitive only triggering is selected, a rising edg e on a PA0–PA3
pin latches an external interrupt request. A subsequent external interrupt
request can be latched only after the voltage level of the previous
interrupt signal returns to logic 0 and then rises again to logic 1.
NOTE: T he b ranch i f inter rup t pin i s high ( BIH) and bra nch i f int err upt pi n is l ow
(BIL) instructions apply only to the level on the IRQ/VPP pin itself and not
to the output of the logic OR function with the PA0–PA3 pins. T he state
of the individual port A pins can be checked by reading the appropriate
port A pins as inputs.
Enabled PA0–PA3 pins cause an IRQ interrupt regardless of whether
these pins are configured as inputs or outputs.
The IRQ pin has an internal Schmitt trigger. The optional external
interrupts (PA0–PA3) do not have internal Schmitt triggers.
The interrupt mask bit (I) in the condition code register (CCR) disables
all maskable interrupt requests, including external interrupt requests.
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Technical Data MC68HC705J1A —Rev. 4.0
External Interrupt Module (IRQ)
External Interrupt Module (IRQ)
8.4 IRQ S tatus and Control Register
The IRQ status and control register (ISCR) controls and monitors
operation of the IRQ module. All unused bits in the ISCR read as
logic 0s. The IRQF bit is cleared and the IRQE bit is set by reset.
IRQR — Interrupt Request Reset Bit
This write-only bit clears the external interrupt request flag.
1 = Clears external interrupt and IRQF bit
0 = No effect on external interrupt and IRQF bit
IRQF — External Interrupt Request Flag
The exter nal i nterrupt re quest fl ag is a clearable, rea d-on l y bit that is
set when an external interrupt request is pending. Reset clears the
IRQF bit.
1 = External interrupt request pending
0 = No external interrupt request pending
IRQE — External Interrupt Request Enable Bit
This read/write bit enables external interrupts. Reset sets the IRQE
bit.
1 = External interrupt requests enabled
0 = External interrupt requests disabled
The STOP and WAIT instructions set the IRQE bit so that an external
inte rru pt can bring the MCU out of these low-pow er mo des. In addition,
reset sets the I bit which masks all interrupt sources.
Address: $000A
Bit 7654321Bit 0
Read:
IRQE
000IRQF000
Write: RIRQR
Reset:10000000
= Unimplemented R = Reserved
Figure 8-3. IRQ Status and Control Register (ISCR)
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External Interrupt Module (IRQ)
External Interrupt Timing
MC68HC705J1A —Rev. 4.0 Technical Data
External Interrupt Module (IRQ)
8.5 Ext ernal Interru pt Timing
Figure 8-4. External Interrupt Timing
8.5.1 5.0-Volt External Interrupt Timing Ch aracteristics
8.5.2 3.3-Volt External Interrupt Timing Ch aracteristics
Characteristic(1)
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, T A = –40°C to + 10 5 °C, unless otherwise noted
Symbol Min Max Unit
IRQ inte rrupt pulse width low (edge-triggered) tILIH 1.5 —tcyc(2)
2. tcyc = 1 /fop; fop = fosc/2.
IRQ inte rrupt pulse width (edge- and level-triggered) tILIH 1.5 Note(3)
3. The mini m um , tILIL, should not be less than the number of interrupt ser vice routine cycles plus 19 tcyc.
tcyc
PA0–PA3 interrupt pulse width high (edge-triggered) tILIL 1.5 —tcyc
PA0–PA3 interrupt pulse width high (edge- and level-t riggered) tILIH 1.5 Note(3) tcyc
Characteristic(1)
1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, T A = –40°C to + 10 5 °C, unless otherwise noted
Symbol Min Max Unit
IRQ inte rrupt pulse width low (edge-triggered) tILIH 1.5 —tcyc(2)
2. tcyc = 1 /f op; fop = f osc/2.
IRQ interrupt pulse width (edge- and level-trigg ered) tILIH 1.5 Note(3)
3. The mini m um , tILIL, should not be less than the number of interrupt ser vice routine cycles plus 19 tcyc.
tcyc
PA0–PA3 interrupt pulse width high (edge-triggered) tILIL 1.5 —tcyc
PA0–PA3 interrupt pulse width high (edge- and level-triggered) tILIH 1.5 Note(3) tcyc
IRQ (INTERNAL)
tILIH
tILIL
tILIH
IRQ PIN
IRQ1
IRQn
.
.
.
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Technical Data MC68HC705J1A —Rev. 4.0
External Interrupt Module (IRQ)
External Interrupt Module (IRQ)
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MC68HC705J1A —Rev. 4.0 Tec hnical Data
Multifunction Timer Module
Technical Data — MC68HC705J1A
Section 9. Multifunction Timer Module
9.1 Contents
9.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
9.3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
9.4 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
9.5 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112
9.5.1 Timer Status and Control Register. . . . . . . . . . . . . . . . . . .112
9.5.2 Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . .114
9.6 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
9.6.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
9.6.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115
9.2 Introduction
The multifunction timer provides a timing reference with programmable
real-time interrupt (RTI ) capability. Figure 9-1 shows the timer
organization.
Features include:
•Timer overflow
•Four selectable interrupt rates
•Computer operating properly (COP) watchdog timer
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Technical Data MC68HC705J1A —Rev. 4.0
Multifunction Timer Module
Multifunction Timer Module
Figure 9- 1. Mult ifunction Timer Block Diagram
CLEAR COP TIMER
TIMER COUNTER REGISTER
BITS [0:7] OF 15-STAGE
OVERFLOW ÷ 4INTERNAL CLOCK
(XTAL ÷ 2)
TIMER STATUS/CONTROL REGISTER
TOF
RTIF
TOIE
RTIE
TOFR
RTIFR
RT1
RT0
RTI RATE SELECT
÷ 2÷ 2÷ 2÷ 2÷ 2÷ 2÷ 2
BITS [8:14] OF 15-STAGE RIPPLE COUNTER
÷ 8S
R
Q
INTERRUPT
REQUEST
COP RESET
INTERNAL DATA BUS
RESET
RIPPLE COUNTER
RESET
RESET
RESET
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Multifunction Timer Module
Operation
MC68HC705J1A —Rev. 4.0 Technical Data
Multifunction Timer Module
9 .3 Operation
A 15-stage ripple counter, preceded by a prescaler that divides the
internal clock signal by four, provides the timing reference for the timer
functions. The value of the first eight timer stages can be read at any
time by accessing the timer counter register at address $0009. A timer
overflow function at the eighth stage al lows a timer int errupt every 1024
internal clock cycles.
The next four stages lead to the real-time interrupt (RTI) circuit. The RT1
and RT0 bits in the timer status and control register at address $0008
allow a timer interrupt every 16,384, 32,768, 65,536, or 131,072 clock
cycles. The last four stages drive the selectable COP system. For
information on the COP, refer to the Section 7. Comput er Operating
Pro pe rly (COP) Modu le.
Addr.Register Name Bit 7654321Bit 0
$0008
Timer Status and Control
Register (TSCR)
See page 112.
Read: TOF RTIF
TOIE RTIE
00
RT1 RT0
Write: TOFR RTIFR
Reset:00000011
$0009
Timer Counter Register
(TCR)
See page 114.
Read: TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0
Write:
Reset:00000000
= Unimplemented
Figure 9-2. I/O Register S ummary
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Technical Data MC68HC705J1A —Rev. 4.0
Multifunction Timer Module
Multifunction Timer Module
9.4 Interrupts
These ti mer sources can generate interrupts:
•Timer overflow flag (TOF) — The TOF bit is set when the first eight
stages of the counter roll over from $FF to $00. The timer overflow
interrupt enable bit, TOIE, enables TOF interrupt requests.
•Real-time interrupt flag (RTIF) — The RTIF bit is set when the
selected RTI output becomes active. The real-tim e interrupt
enable bit, RTIE, enables RTIF interrupt requests.
9.5 I/O Registers
These registers control and monitor the timer operation:
•Timer status and control register (TSCR)
•Timer counter register (TCR)
9.5.1 Timer Status and Contro l Register
The read/write timer status and control register (TSCR) performs these
functions:
•Flags timer interrupts
•Enables timer interrupts
•Resets timer interrupt flags
•Selects real-time interrupt rates
Address: $0008
Bit 7654321Bit 0
Read: TOF RTIF
TOIE RTIE
00
RT1 RT0
Write: TOFR RTIFR
Reset:00000011
= Unimplemented
Figure 9-3. Timer Status and Control Register (TSCR)
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Multifunction Timer Module
I/O Registers
MC68HC705J1A —Rev. 4.0 Technical Data
Multifunction Timer Module
TOF — Timer Overflow Flag
This read-only flag becomes set when the first eight stages of the
counter roll over from $FF to $00. TOF generates a timer overflow
inte rru pt r eque st if TOIE is a lso se t. C lear T OF by wri ting a logi c 1 to
the TOFR bit. Writing to TOF has no effect. Reset clears TOF.
RTIF — Real-Time Interrupt Flag
This read-only flag becomes set when the selected RTI output
becomes act ive. RTIF generates a real-time interrupt request if RTIE
is also set. Clear RTIF by writing a logic 1 to the RTIFR bit. Writing
to RTIF has no effect. Reset clears RTIF.
TOIE — Timer Overflow Interrupt Enable Bit
This read/write bit enables timer overflow interrupts. Reset clears
TOIE.
1 = Timer overflow interr upts enabled
0 = Timer overflow interr upts disabled
RTIE — Real-Time Interrupt Enable Bit
This read/write bit enables real-time interrupts. Reset clears RTIE.
1 = Real-time interrupts enabled
0 = Real-time interrupts disabled
TOFR — Timer Overflow Flag Reset Bit
Writing a logic 1 to this write-only bit clears the TOF bit. TOFR always
reads as logic 0. Reset clears TOFR.
RTIFR — Real-Time Interrupt Flag Reset Bit
Writing a logic 1 to this write-only bit clears the RTIF bit. RTIFR
always reads as logic 0. Reset clears RTIFR.
RT1 and RT 0 — Real-Time Interrupt Se lect Bits
These read/write bits select one of four real-time interrupt rates, as
shown in Table 9-1. Because the selected RTI output drives the COP
watchdog, changing the real-tim e interrupt rate also changes the
counting rate of the COP watchdog. Reset sets RT1 and RT0.
NOTE: Changing RT1 and RT0 when a COP timeout is imminent can cause a
real-time interrupt request to be missed or an additional real-time
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Technical Data MC68HC705J1A —Rev. 4.0
Multifunction Timer Module
Multifunction Timer Module
interrupt request to be generated. To prevent this occurrence, clear the
COP timer before changing RT1 and RT0.
9.5.2 Timer Counter Register
A 15-stage ripple counter is the core of the timer. The value of the first
eight stages is readable at any time from the read-only timer counter
register (TCR) shown in Figure 9-4.
Power-on clears the entire counter chain and the internal clock begins
clocking the coun ter. After 4064 cycles (or 16 cycles if the S OSCD bit in
the mask option register is set), the power-on reset circuit is released,
clearing the counter again and allowing the MCU to come out of reset.
A timer overflow function at the eighth counter stage allows a timer
interrupt every 1024 internal clock cycles.
Table 9-1. Real-Time Interrupt Rate Selection
RT1:RT0 Number
of Cycles
to RTI
RTI
Period(1)
1. At 2-MHz bus, 4- MHz XTAL, 0.5 µs per cy cle
Number
of Cycles
to COP Reset
COP Ti m eout
Period(1)
0 0 214 = 16,3 8 4 8.2 ms 217 = 131,072 65.5 ms
0 1 215 = 32,7 6 8 16.4 ms 218 = 262,144 131.1 ms
1 0 216 = 65,5 3 6 32.8 ms 219 = 524,288 262.1 ms
1 1 217 = 131,072 65.5 ms 220 = 1,048,576 524 .3 ms
Address: $0009
Bit 7654321Bit 0
Read: TMR7 TMR6 TMR5 TMR4 TMR3 TMR2 TMR1 TMR0
Write:
Reset:00000000
= Unimplemented
Fi gu re 9-4. Tim er Co un ter Register ( TCR )
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Multifunction Timer Module
Low-Power Modes
MC68HC705J1A —Rev. 4.0 Technical Data
Multifunction Timer Module
9.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low
power-consumption standby states.
9.6.1 Stop Mode
The STOP in struction has these effects on the timer:
•Clears the timer counter
•Clears interrupt flags (TOF and RTIF) and interr upt enable bits
(TOF E and R TI E) i n TSCR , re moving any pending tim er in terr upt
requests and disabling further timer interrupts.
9.6.2 Wait Mode
The timer remains active after a WAIT instruction. Any enabled timer
interrupt request can bring the MCU out of wait mode.
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Technical Data MC68HC705J1A —Rev. 4.0
Multifunction Timer Module
Multifunction Timer Module
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MC68HC705J1A —Rev. 4.0 Tec hnical Data
Electrical Spec ifications
Technical Data — MC68HC705J1A
Section 10. Electrical Specifications
10.1 Contents
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
10.3 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
10.4 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .119
10.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
10.6 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
10.7 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .121
10.8 3.3-Volt DC Electrical Characteristics . . . . . . . . . . . . . . . . . .122
10.9 Driver Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123
10.10 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
10.11 EPROM Programming Characteristics. . . . . . . . . . . . . . . . . .126
10.12 5.0-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
10.13 3.3-Volt Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
10.2 Introduction
This section contains electrical and timing specifications.
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Technical Data MC68HC705J1A —Rev. 4.0
Electrical Spec ifications
Electrical Specifications
10.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table here. Keep VIn and VOut within the range
VSS ≤(VIn or VOut)≤ VDD. Connect unused inputs to the appropria te
voltage level, either V SS or VDD.
NOTE: This device is not guaranteed to operate properly at the maximum
ratings. Refer to 10.7 5.0-Volt DC Electrical Characteristics and
10.8 3.3-Volt DC E lectrical Character istics for guaranteed operati ng
conditions.
Rating(1)
1. Volt ages a re referenced to VSS.
Symbol Value Unit
Supply voltage VDD –0.3 to +7.0 V
Current drain per pin (excluding
VDD, V SS, and PA4–PA7) I25mA
Input voltage VIn VSS – 0.3 to VDD + 0. 3 V
IRQ/VPP pin VPP VSS – 0. 3
to 2 x VDD + 0.3 V
Storage temperature range TSTG –65 to +150 °C
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Ele ctrical Specifications
Operating Temperature Range
MC68HC705J1A —Rev. 4.0 Technical Data
Electrical Spec ifications
10.4 Operating Temperature Range
10.5 Therm al Chara ct erist ics
Package Type Symbol Value
(TL to TH)Unit
MC68HC705J1AP(1), DW(2), S(3)
1. P = plastic dual in-li ne package (PDIP)
2. DW = small out li ne integrated ci rcuit (SOIC)
3. S = cerami c DIP (ce rdi p)
TA0 to 70 °C
MC68HC705J1AC(4)P, CDW, CS
4. C = extended temperature range
TA–40 to +85 °C
MC68HC705J1AV(5)P, VDW, VS
5. V = automotive temperature range
TA–40 to +105 °C
Characteristic Symbol Value Unit
Therm al resistance
MC68HC705J1AP(1)
MC68HC705J1ADW(2)
MC68HC705J1AS(3)
1. P = plastic dual in-li ne package (PDIP)
2. DW = small out li ne integrated ci rcuit (SOIC)
3. S = cerami c DIP (ce rdi p)
θJA 60 °C/W
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Technical Data MC68HC705J1A —Rev. 4.0
Electrical Spec ifications
Electrical Specifications
10.6 Power Considerations
The average chip junction temperature, TJ, in °C can be obtained from:
TJ = TA + (PD x θJA)(1)
Where:
TA = ambient temperature in °C
θJA = package thermal resistance, junction to ambient in °C/W
PD = PINT + PI/O
PINT = ICC × VCC = chip internal power di ssipation
PI/O = power dissipation on input and output pins (user-determined)
For most applications, PI/O < P INT and can be neglected.
Ignoring PI/O, the relationship between PD and TJ is approximately:
(2)
Solving equations (1) and (2) for K gives:
= PD x (TA + 273°C) + θJA x (PD)2(3)
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring PD (at equilibrium) for a
known TA. Using this value of K, the values of PD and TJ can be obtained
by solving equations (1) and (2) iteratively for any value of TA.
PD = TJ + 273°C
K
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Ele ctrical Specifications
5.0-Volt DC Electrical Characteristics
MC68HC705J1A —Rev. 4.0 Technical Data
Electrical Spec ifications
10.7 5.0-Volt DC Electrical Characteristics
Characteristic(1)
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, T A = –40°C to +105°C, unless otherwise not ed
Symbol Min Typ(2)
2. Typical values at midpoint of volta ge range, 25°C only
Max Unit
Outp ut voltage
ILoad = 10.0 µA
ILoad = –10.0 µAVOL
VOH
—
VDD – 0.1 —
—0.1
—V
Outp ut high voltage
(ILoad = –0.8 mA) PA0–PA7, PB0–PB5 VOH VDD – 0.8 ——V
O utput low vo lta g e
(ILoad = 1.6 mA) PA0–PA3, PB0–PB5
(ILoad = 10.0 mA) PA4–PA7 VOL ——0.4
0.4 V
Input high vol tage
PA0–PA7, PB0–PB 5 , IR Q/VPP, RESET, OSC 1 VIH 0.7 × VDD —VDD V
Input low voltage
PA0–PA7, PB0–PB 5 , IR Q/VPP, RESET, OSC 1 VIL VSS —0.2 × VDD V
Supply current
Run mode(3)
Wai t m o de (4)
Stop mod e(5)
25°C
–40 to 105°C
3. Run mode IDD is measured using exte rnal squa re wave clock source (fosc = 4.2 MHz); all input s 0.2 V from rail; no dc l oads;
less than 50 pF on all outputs; CL = 20 pF on OSC2
4. Wait mode IDD: only timer system active. Wait mode is affected linearly by OSC2 capacitance. Wait mode is measured
with all por ts configured as inputs; V IL = 0.2 V; VIH = VDD – 0.2 V. Wai t mode IDD is measur ed using exte rnal squar e wave
clock source (fosc = 4.2 MHz); all inputs 0.2 V from rail; no dc lo ads; less than 50 pF on all out puts; CL = 20 pF on OSC2.
5. Stop mode IDD is measured with OSC1 = VSS. Stop mode IDD is measured with all port s configured as input s; VIL = 0.2 V;
VIH = VDD – 0.2 V
IDD
—
—
—
—
3.5
0.45
0.2
2.0
6.0
2.75
10
20
mA
mA
µA
µA
I/O p orts hi-z leak age current
PA0–PA7, PB0–PB5 (without individual pulldown activated) IIL —0.2 ±1µA
Input pulldown current
PA0–PA7, PB0–PB5 (with i ndivi dual pulldown acti vated) IIL 35 80 200 µA
Input pullup current
RESET IIL –15 –35 –85 µA
Input current(6)
RESET, IRQ/VPP, OSC1
6. Only input high current rated to +1 µA on RESET.
IIn —0.2 ±1µA
Capacitance
Ports (as inputs or outputs)
RESET, IRQ/VPP, OSC1, O SC2 COut
CIn
—
——
—12
8pF
Crystal/ceramic resonator oscillator mode internal resistor
OSC1 to OSC2(7)
7. The Rosc value selected for RC oscillator versions of this device is unspecified. See Appendi x C. MC68HSR705J1A for
additional information.
Rosc 1.0 2.0 3.0 MΩ
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Technical Data MC68HC705J1A —Rev. 4.0
Electrical Spec ifications
Electrical Specifications
10.8 3.3-Volt DC Electrical Characteristics
Characteristic(1)
1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, T A = –40°C to +105°C, unless otherwise not ed
Symbol Min Typ(2)
2. Typical values at midpoint of volta ge range, 25°C only
Max Unit
Outp ut voltage
ILoad = 10.0 µA
ILoad = –10.0 µAVOL
VOH
—
VDD– 0.1 —
—0.1
—V
Outp ut high voltage
(ILoad = –0.2 mA) PA0–PA7, PB0–PB5 VOH VDD – 0.3 ——V
Outp ut low voltage
(ILoad = 0.4 mA) PA0–PA3, PB0–PB5
(ILoad = 5.0 mA) PA4–PA7 VOL ——0.3
0.3 V
Input high vol tage
PA0–PA7, PB0–PB 5 , IR Q/VPP, RESET, OSC 1 VIH 0.7 × VDD —VDD V
Input low voltage
PA0–PA7, PB0–PB 5 , IR Q/VPP, RESET, OSC 1 VIL VSS —0.2 × VDD V
Supply current
Run Mode(3)
Wai t M o de (4)
Stop Mod e(5)
25°C
–40 to 105°C
3. Run mode IDD is measured using exte rnal squa re wave clock source (fosc = 2.0 MHz); all input s 0.2 V from rail; no dc l oads;
less than 50 pF on all outputs; CL = 20 pF on OSC2
4. Wait mode IDD: only timer system active. Wait mode is affected linearly by OSC2 capacitance. Wait mode is measured
with all por ts configured as inputs; V IL = 0.2 V; VIH = VDD – 0.2 V. Wai t mode IDD is measur ed using exte rnal squar e wave
clock source (fosc = 2.0 MHz); all inputs 0.2 V from rail; no dc lo ads; less than 50 pF on all out puts; CL = 20 pF on OSC2.
5. Stop mode IDD is measur ed with OSC1 = VSS. Stop mode IDD is measured with all ports configured as inputs ; VIL = 0.2 V;
VIH = VDD – 0.2 V
IDD
—
—
—
—
1.2
0.25
0.1
1.0
4.0
1.5
5
10
mA
mA
µA
µA
I/O ports hi-z leakage current
PA0–PA7, PB0–PB5 (without individual pulldown activated) IIL —0.1 ±1µA
Input pulldown current
PA0–PA7, PB0–PB5 (with i ndivi dual pulldown acti vated) IIL 12 30 100 µA
Input pullup current
RESET IIL –10 –25 –45 µA
Input current(6)
RESET, IRQ/VPP, OSC1
6. Only input high current rated to +1 µA on RESET.
IIn —0.1 ±1µA
Capacitance
Ports (as inputs or outputs)
RESET, IRQ/VPP, OSC1, OSC2 COut
CIn
—
——
—12
8pF
Crystal/ceram ic res onator oscillator mode internal resistor
OSC1 to OSC2(7)
7. The Rosc value selected for RC oscillator versions of this devic e is unspecified. See Appendix C. MC68H SR705J1A for
additional information.
Rosc 1.0 2.0 3.0 MΩ
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Ele ctrical Specifications
Driver Charact eristics
MC68HC705J1A —Rev. 4.0 Technical Data
Electrical Spec ifications
10.9 Driver Characteristics
Figure 10-1. PA0–PA7, PB0–PB5 Typical High-Side Driver Characteristics
Fi gure 10-2. PA0 –PA3, PB0–PB5 Typical Low-Side Driver Characteristics
Notes:
1. At VDD = 5.0 V, device s are specified and tested for (VDD – VOH) ≤ 800 mV @ IOH = –0.8 mA.
2. At VDD = 3.3 V, device s are specified and tested for (VDD – VOH) ≤ 300 mV @ IOH = –0.2 mA.
800 mV
700 mV
600 mV
500 mV
400 mV
300 mV
200 mV
100 mV
00−1.0 mA −2.0 mA −3.0 mA −4.0 mA −5.0 mA
VDD = 5.0 V
IOH
V
DD
- V
OH
85 °C
25 °C NOMINAL PROCESSING
−40 °C
25 °C NOMINAL PROCESSING
800 mV
700 mV
600 mV
500 mV
400 mV
300 mV
200 mV
100 mV
00−1.0 mA −2.0 mA −3.0 mA −4.0 mA −5.0 mA
VDD = 3.3 V
IOH
V
DD
- V
OH
85 °C
−40 °C
SEE NOTE 1
SEE NOTE 2
105 °C
105 °C
400 mV
350 mV
300 mV
250 mV
200 mV
150 mV
100 mV
50 mV
00 2.0 mA 4.0 mA 6.0 mA 8.0 mA 10.0 mA
VDD = 3.3 V
IOL
V
OL
85 °C
–40 °C
25°C NOMINAL PROCESSING
SEE NOTE 2
Notes:
1. At VDD = 5.0 V, devices are specifi ed and tested for VOL ≤ 400 mV @ IOL = 1.6 mA.
2. At VDD = 3.3 V, devices are specifi ed and tested for VOL ≤ 300 mV @ IOL = 0.4 mA.
105 °C
400 mV
350 mV
300 mV
250 mV
200 mV
150 mV
100 mV
50 mV
00 2.0 mA 4.0 mA 6.0 mA 8.0 mA 10.0 mA
VDD = 5.0 V
IOL
V
OL
85 °C
–40 °C
25°C NOMINAL PROCESSING
SEE NOTE 2
105 °C
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Technical Data MC68HC705J1A —Rev. 4.0
Electrical Spec ifications
Electrical Specifications
Fi gure 10-3. PA4 –PA7 Ty pical Low-Side Driver Characteristics
800 mV
700 mV
600 mV
500 mV
400 mV
300 mV
200 mV
100 mV
00 10 mA 20 mA 30 mA 40 mA 50 mA
VDD = 5.0 V
IOL
V
OL
85 °C
25 °C NOMINAL PROCESSING
800 mV
700 mV
600 mV
500 mV
400 mV
300 mV
200 mV
100 mV
00 10 mA 20 mA 30 mA 40 mA 50 mA
IOL
85 °C
−40 °C
25 °C NOMINAL PROCESSING
V
OL
SEE NOTE 2
SEE NOTE 1
Notes:
1. At VDD = 5.0 V, devices are specified and t ested for VOL ≤ 400 mV @ IOL = 10.0 mA.
2. At VDD = 3.3 V, devices are specified and t ested for VOL ≤ 300 mV @ IOL = 5.0 mA.
105 °C
105 °C
−40 °C
VDD = 3.3 V
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Ele ctrical Specifications
Typical Supply Currents
MC68HC705J1A —Rev. 4.0 Technical Data
Electrical Spec ifications
10.10 Typical Supply Currents
Figure 10-4. Typical Operating IDD (25°C)
Figure 10-5. Typical Wait Mode IDD (25°C)
6.0 mA
5.0 mA
4.0 mA
3.0 mA
2.0 mA
1.0 mA
0
0 1.0 MHz 2.0 MHz
3.0 V
4.5 V
3.6 V
5.5 V
SUPPLY CURRENT (I
DD
)
Notes:
1. At VDD = 5.0 V, device s are specif ied and tested f or IDD ≤ 6.0 mA @ fOP = 2.1 MHz .
2. At VDD = 3.3 V, device s are specif ied and tested f or IDD ≤ 4.0 mA @ fOP = 1.0 MHz .
SEE NOTE 1
SEE NOTE 2
INTERNAL OPERATING FREQUENCY (fOP)
700 µA
600 µA
500 µA
400 µA
300 µA
200 µA
100 µA
0
0 1.0 MHz 2.0 MHz
3.0 V
4.5 V
3.6 V
5.5 V
SUPPLY CURRENT (I
DD
)
INTERNAL OPERATING FREQUENCY (fOP)
Notes:
1. At VDD = 5.0 V, devices are specified and tested for IDD ≤ 2.75 mA @ fOP = 2.1 MHz.
2. At VDD = 3.3 V, devices are specified and tested for IDD ≤ 1.5 mA @ fOP = 1.0 MHz.
SEE NOTE 1
SEE NOTE 2
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Technical Data MC68HC705J1A —Rev. 4.0
Electrical Spec ifications
Electrical Specifications
10.11 EPROM Programming Characteristics
10.12 5.0-Volt Control Timing
Characteristic(1)
1. VDD = 5.0 Vdc ± 10% , VSS = 0 Vdc, TA = –40°C to +1 0 5 °C, unless otherwise noted
Symbol Min Typ Max Unit
Programming voltage
IRQ/VPP VPP 16.0 16.5 17.0 V
Programming current
IRQ/VPP IPP —3.0 10.0 mA
Pr ogr a mming ti me
Per array byt e
MOR tEPGM
tMPGM
4
4—
——
—ms
Characteristic(1)
1. VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +105°C, unless otherwise not ed
Symbol Min Max Unit
Oscillator frequency
Cry st al o s c illator o pt io n
External clock source fosc —
dc 4.2
4.2 MHz
Internal operating frequency (fosc ÷ 2)
Cry st al o s c illator
External clock fop —
dc 2.1
2.1 MHz
Cycle time (1 ÷ fOP)t
cyc 476 —ns
RESET pulse width low tRL 1.5 —tcyc
IRQ i nte rrupt pulse width low (edge-trigge red) tILIH 1.5 —tcyc
IRQ interrupt pulse width low (edge- and level-triggered) tILIL 1.5 Note(2)
2. The maximum width, tILIL or tILIH, should not be more than the num ber of cycles it takes to execute the interrupt service
routine plus 19 tcyc or th e int err upt service rout ine will be re-entered.
tcyc
PA0–PA3 interrupt pulse width high (edge-triggered) tIHIL 1.5 —tcyc
PA0–PA3 interrupt pulse width (edge- and level-tri ggered) tIHIH 1.5 Note(2) tcyc
OSC1 pulse width tOH, tOL 200 —ns
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Ele ctrical Specifications
3.3-Volt Control Timing
MC68HC705J1A —Rev. 4.0 Technical Data
Electrical Spec ifications
10.13 3.3-Volt Control Timing
Characteristic(1)
1. VDD = 3.3 Vdc ± 10%, VSS = 0 Vdc, TA = –40°C to +105°C, unless otherwise not ed
Symbol Min Max Unit
Oscillator frequency
Cry st al os c illator o pt io n
External clock source fosc —
dc 2.0
2.0 MHz
Internal operating frequency (fosc ÷ 2)
Cry st al o s c illator
External clock fop —
dc 1.0
1.0 MHz
Cycle time (1 ÷ fOP)t
cyc 1000 —ns
RESET pulse width low tRL 1.5 —tcyc
IRQ interrupt pulse width low (edge-triggered) tILIH 1.5 —tcyc
IRQ interrupt pulse width low (edge- and level-trigg ered) tILIL 1.5 Note(2)
2. The maximum width, tILIL or tILIH, should not be more than the number of cycles it takes to execute t he interrupt service
routine plus 19 tcyc or th e int err upt service rout ine will be re-entered.
tcyc
PA0–PA3 interrupt pulse width high (edge-triggered) tIHIL 1.5 —tcyc
PA0–PA3 interrupt pulse width (edge- and level-tri ggered) tIHIH 1.5 Note(2) tcyc
OSC1 pulse width tOH, tOL 400 —ns
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Technical Data MC68HC705J1A —Rev. 4.0
Electrical Spec ifications
Electrical Specifications
Figure 10-6. External Interrup t Timing
Figure 10-7. Stop Mode Recovery Timing
IRQ (INTERNAL)
tILIH
tILIL
tILIH
IRQ PIN
IRQ1
IRQn
.
.
.
tILIH
4064 tcyc
OSC (NOTE 1)
tRL
RESET
IRQ (NOTE 2)
IRQ (NOTE 3)
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
Notes:
1. Inte rnal clocking from OSC1 p in
2. Edge-t riggered external interrupt mask option
3. Edge- and level-t riggered external int errupt mask option
4. Reset vec tor shown as example
RESET OR INTERRUPT
VECTOR FETCH
07FE 07FE 07FE 07FE 07FE 07FF
(NOTE 4)
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Ele ctrical Specifications
3.3-Volt Control Timing
MC68HC705J1A —Rev. 4.0 Technical Data
Electrical Spec ifications
Figure 10-8. Power-On Reset Timing
Figure 10-9. External Reset Timing
07FE
4064 tcyc
VDD
OSC1 PIN
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
Notes:
INTERNAL
DATA BUS
07FE 07FE 07FE 07FE 07FE 07FF
(NOTE 1)
1. Power-o n reset thr eshold is typi cally between 1 V and 2 V.
2. Inte rnal clock, internal address bus, and inter nal data bus are not available externally.
NEW
PCH
NEW
PCL
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
Notes:
INTERNAL
DATA BUS
07FE 07FE 07FE 07FE 07FF NEW PC
1. Int ernal clock, i nternal address bus, and interna l data bus are not avail able extern all y.
2. The next ri sing edge of the internal clock after the rising edge of RESET init iates the reset se quence.
NEW
PCH
tRL
NEW PC
NEW
PCL DUMMY OP
CODE
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Technical Data MC68HC705J1A —Rev. 4.0
Electrical Spec ifications
Electrical Specifications
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MC68HC705J1A —Rev. 4.0 Tec hnical Data
Mechanical Specifications
Technical Data — MC68HC705J1A
Section 11. Mechanical Specifications
11.1 Contents
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
11.3 Plastic Dual In-Line Package (Case 738). . . . . . . . . . . . . . . .132
11.4 Small Outline Integrated Circuit (Case 751). . . . . . . . . . . . . .132
11.5 Ceramic Dual In-Line Package (Case 732) . . . . . . . . . . . . . .133
11.2 Introduction
The MC68HC705J1A, the resistor-capacitor (RC) oscillator, and
high-speed option devices described in Appendix A.
MC68HRC705J1A, Appendix B. MC68HSC705J1A, and Appendix C.
MC68HSR705J1A are available in the following packages:
•738-03 — plastic dual in-line package (PDIP)
•751D-04 — small outline integrated circuit (SOIC)
•732-03 — ceramic DIP (cerdip) (windowed)
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Technical Data MC68HC705J1A —Rev. 4.0
Mechanical Specifications
Mechanical Specifications
11.3 Plastic Dual In-Line Package (Case 738)
11.4 Small Outline Integrated Circuit (Case 751)
1.070
0.260
0.180
0.022
0.070
0.015
0.140
15°
0.040
1.010
0.240
0.150
0.015
0.050
0.008
0.110
0°
0.020
25.66
6.10
3.81
0.39
1.27
0.21
2.80
0°
0.51
27.17
6.60
4.57
0.55
1.77
0.38
3.55
15°
1.01
0.050 BSC
0.100 BSC
0.300 BSC
1.27 BSC
2.54 BSC
7.62 BSC
MIN MINMAX MAX
INCHES MILLIMETERS
DIM
A
B
C
D
E
F
G
J
K
L
M
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
-A-
C
K
N
E
GF
D 20 PL
J 20 PL
L
M
-T-
SEATING
PLANE
110
1120
0.25 (0.010) T A
M M
0.25 (0.010) T B
M M
B
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A
B
C
D
F
G
J
K
M
P
R
0.510
0.299
0.104
0.019
0.035
0.012
0.009
7°
0.415
0.029
0.499
0.292
0.093
0.014
0.020
0.010
0.004
0°
0.395
0.010
12.95
7.60
2.65
0.49
0.90
0.32
0.25
7°
10.55
0.75
12.65
7.40
2.35
0.35
0.50
0.25
0.10
0°
10.05
0.25
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.150
(0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.13
(0.005) TOTAL IN EXCESS OF D DIMENSION
AT MAXIMUM MATERIAL CONDITION.
1.27 BSC 0.050 BSC
-A-
-B- P 10 PL
110
1120
-T-
D 20 PL
K
C
SEATING
PLANE
R X 45°
M
0.010 (0.25) B
M M
0.010 (0.25) T A B
MS S
G 18 PL
F
J
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Mechanical Spec ifications
Ceramic Dual In-Line Package (Case 732)
MC68HC705J1A —Rev. 4.0 Technical Data
Mechanical Specifications
11.5 Ceramic Dual In-Line Package (Case 732)
NOTES:
1. LEADS WITHIN 0.010 DIAMETER, TRUE
POSITION AT SEATING PLANE, AT MAXIMUM
MATERIAL CONDITION.
2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
3. DIMENSIONS A AND B INCLUDE MENISCUS.
DIM MIN MAX
INCHES
A0.940 0.990
B0.260 0.295
C0.150 0.200
D0.015 0.022
F0.055 0.065
G0.100 BSC
H0.020 0.050
J0.008 0.012
K0.125 0.160
L0.300 BSC
M0 15
N0.010 0.040
__
A
20
110
11
B
FC
SEATING
PLANE
D
HGK
NJM
L
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Technical Data MC68HC705J1A —Rev. 4.0
Mechanical Specifications
Mechanical Specifications
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MC68HC705J1A —Rev. 4.0 Tec hnical Data
Technical Data — MC68HC705J1A
Se ction 11.
Section 12. Orde ring Information
12.1 Contents
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
12.3 MCU Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
12.2 Introduction
This section contains ordering information for the available package
types.
12.3 MCU Order Numb ers
Table 12-1 lists the MC order numbers.
Table 12-1. Order Numbers
Package
Type Case
Outline Pin
Count Operating
Temperature Order Number(1)
1. Refer to Appendix A. MC68HRC705J1A, Appendix B. MC68HSC705J1A , and
Appendix C. MC68HSR705J1A for ordering information on opti onal high-speed and
resistor- capacito r oscillator devices.
PDIP 738-03 20 0 to 70°C
–40 to +85°C
–40 to +105°C
MC68HC705J1AP(2)
MC68HC705J1AC(3)P
MC68HC705J1AV(4)P
2. P = Plastic dual i n-l ine package (PDIP)
3. C = Extended temperature range
4. V = Automotive t em perature range
SOIC 751D-04 20 0 to 70 °C
–40 to +85°C
–40 to +105°C
MC68HC705J1ADW(5)
MC68HC705J1ACDW
MC68HC705J1AVDW
5. DW = Small outline integrat ed circuit (SOIC)
Cerdip 732-03 20 0 to 70°C
–40 to +85°C
–40 to +105°C
MC68HC705J1AS(6)
MC68HC705J1ACS
MC68HC705J1AVS
6. S = Ceramic dual i n-l ine package (ce rdi p)
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Technical Data MC68HC705J1A —Rev. 4.0
Ordering Information
Ordering Information
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MC68HC705J1A —Rev. 4.0 Tec hnical Data
MC68HRC705J1A
Technical Data — MC68HC705J1A
Appendix A. MC68HRC705J1A
A.1 Co ntents
A.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
A.3 RC Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . .138
A.4 Typical Internal Operating Frequency
for RC Oscillator Option. . . . . . . . . . . . . . . . . . . . . . . . . . .139
A.5 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . .140
A.2 Introdu ct ion
This appendix introduces the MC68HRC705J1A, a r esistor-capacitor
(RC) oscillator mask option version of the MC68HC705J1A. All of the
information in this document applies to the MC68HRC705J1A with the
exceptions given in this appendix.
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Technical Data MC68HC705J1A —Rev. 4.0
MC68HRC705J1A
MC68HRC705J1A
A.3 RC Oscillator Connections
For greater cost reduction, the RC oscillator mask option allows the
confi gura tion sh own i n Fig ur e A-1 to dr ive the on- chip o scilla tor. Moun t
the RC components as close as possible to the pins for startup
stabilization and to minimize output distortion.
Figure A-1. RC Oscillator Connections
NOTE: The optional internal resistor is not recommended for configurations that
use the RC oscillator connections as shown in Figure A-1. For such
configurations, the oscillator inte rnal resistor (OSCRES) bit of the mask
option register should be programmed to a logic 0.
MCU
VDD
VSS
C1C2
OSC1
OSC2
R
OSC1
OSC2
R
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MC68HRC705J1A
Typical Internal Operating Frequency for RC Oscillator Option
MC68HC705J1A —Rev. 4.0 Technical Data
MC68HRC705J1A
A.4 Typical Internal Operating Frequency for RC Oscillator Option
Figure A-2 shows typical internal operating frequencies at 25°C for the
RC oscillator option.
NOTE: Tolerance f or resistance is ±50%. When selecting resistor size, consider
the tolerance to ensure that the resulting oscillator frequency does not
exceed the maximum operating frequency.
Figure A-2. Typical Internal Operating Frequency
for Various V DD at 25°C — RC Oscillator Option Only
0.01
0.1
1
10
1 10 100 1000 10000
RESISTANCE (kΩ)
FREQUENCY (MHz)
3.0 V
3.6 V
4.5 V
5.0 V
5.5 V
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Technical Data MC68HC705J1A —Rev. 4.0
MC68HRC705J1A
MC68HRC705J1A
A.5 Package Types and Order Numbers
Table A-1. MC68HRC705J1A (RC Oscillator Option)
Order Numbers
Package
Type Case
Outline Pin
Count Operating
Temperature Order Number(1)
1. Refer to Section 12. Ordering Information for standard part ordering info rmation.
PDIP 738-03 20 0 to 70°C
–40 to +85°C
–40 to +105°C
MC68HRC705J1AP(2)
MC68HRC705J1AC(3)P
MC68HRC705J1AV(4)P
2. P = plastic dual in-li ne package (PDIP)
3. C = extended temperature range
4. V = automotive temperature range
SOIC 751D-04 20 0 to 70 °C
–40 to +85°C
–40 to +105°C
MC68HRC705J1ADW(5)
MC68HRC705J1ACDW
MC68HRC705J1AVDW
5. DW = small out li ne integrated ci rcuit (SOIC)
Cerdip 732-03 20 0 to 70°C
–40 to +85°C
–40 to +105°C
MC68HRC705J1AS(6)
MC68HRC705J1ACS
MC68HRC705J1AVS
6. S = ceramic dual in- li ne package (cerd ip)
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MC68HC705J1A —Rev. 4.0 Tec hnical Data
MC68HSC705J1A
Technical Data — MC68HC705J1A
Appendix B. MC68 HSC705J1A
B.1 Co ntents
B.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
B.3 5.0-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .142
B.4 3.3-Volt DC Electrical Characteristics. . . . . . . . . . . . . . . . . . .142
B.5 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142
B.6 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . .144
B.2 Introdu ct ion
This appendix introduces the MC68HSC705J1A, a high-speed version
of the MC68HC705J1A. All of the information in this document applies to
the MC68HSC705J1A with the exceptions given in this appendix.
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Technical Data MC68HC705J1A —Rev. 4.0
MC68HSC705J1A
MC68HSC705J1A
B.3 5.0-V olt D C Ele ctr ic al Cha ra ct er ist ics
B.4 3.3-V olt D C Ele ctr ic al Cha ra ct er ist ics
B. 5 Typical Supply Cu rrents
Figu re B-1. Typical High-Speed Operating IDD (25°C)
Characteristic Symbol Min Typ Max Unit
Supply current (fOP = 4.0 MHz)
Run
Wait IDD —4.25
0.57 7.0
3.25 mA
Characteristic Symbol Min Typ Max Unit
Supply current (fOP = 2.1 MHz)
Run
Wait IDD —1.4
0.28 4.25
1.75 mA
6.0 mA
5.0 mA
4.0 mA
3.0 mA
2.0 mA
1.0 mA
0
0 1.0 MHz 2.0 MHz 3.0 MHz 4.0 MHz
3.0 V
4.5 V
3.6 V
5.5 V
SUPPLY CURRENT (I
DD
)
INTERNAL OPERATING FREQUENCY (fOP)
Notes:
1. A t V DD = 5.0 V, high-speed devices are specified and tested f or
IDD ≤ 7.0 mA @ fOP = 4.0 MHz.
2. A t V DD = 3.3 V, high-speed devices are specified and tested f or
IDD ≤ 4. 25 m A @ fOP = 2.1 MHz.
SEE NOTE 1
SEE NOTE 2
7.0 mA
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MC68HSC705J1A
Typical Supply Currents
MC68HC705J1A —Rev. 4.0 Technical Data
MC68HSC705J1A
Figure B-2. Typical High-Speed Wait Mod e IDD (25°C)
700 µA
600 µA
500 µA
400 µA
300 µA
200 µA
100 µA
0
0 1.0 MHz 2.0 MHz 3.0 MHz 4.0 MHz
3.0 V
4.5 V
3.6 V
5.5 V
SUPPLY CURRENT (I
DD
)
INTERNAL OPERATING FREQUENCY (fOP)
Notes:
1. At VDD = 5.0 V, high-speed devices are specified and test ed for
IDD ≤ 3.25 mA @ fOP = 4.0 MHz.
2. At VDD = 3.3 V, high-speed devices are specified and test ed for
IDD ≤ 1.75 mA @ fOP = 2.1 MHz.
SEE NOTE 1
SEE NOTE 2
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Technical Data MC68HC705J1A —Rev. 4.0
MC68HSC705J1A
MC68HSC705J1A
B.6 Package Types and Order Numbers
Table B-1. MC68HSC705J1A (High Speed) Order Numbers
Package
Type Case
Outline Pin
Count Operating
Temperature Order Number(1)
1. Refer to Section 12. Ordering Information for standard part ordering info rmation.
PDIP 738-03 20 0 to 70°C
–40 to +85°CMC68HSC705J1AP(2)
MC68HSC705J1AC(3)P
2. P = plastic dual in-li ne package (PDIP)
3. C = extended temperature range
SOIC 751D-04 20 0 to 70 °C
–40 to +85°CMC68HSC705J1ADW(4)
MC68HSC705J1ACDW
4. DW = small out li ne integrated ci rcuit (SOIC)
Cerdip 732-03 20 0 to 70°C
–40 to +85°C MC68HSC705J1AS(5)
MC68HSC705J1ACS
5. S = ceramic dual in- li ne package (cerd ip)
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MC68HC705J1A —Rev. 4.0 Tec hnical Data
MC68HSR705J1A
Technical Data — MC68HC705J1A
Appendix C. MC68 HSR705J1A
C.1 Co ntents
C.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
C.3 RC Oscillator Connections (External Resistor). . . . . . . . . . . .145
C.4 Typical Internal Operating Frequency at 25°C
for High-Speed RC Oscillator Option. . . . . . . . . . . . . . . . .146
C.5 RC Oscillator Connections (No External Resistor). . . . . . . . .147
C.6 Typical Internal Operating Frequency versus Temperature
(No External Resistor) . . . . . . . . . . . . . . . . . . . . . . . . . . . .148
C.7 Package Types and Order Numbers . . . . . . . . . . . . . . . . . . .149
C.2 Introdu ct ion
This appendix introduces the MC68HSR705J1A, a high-speed version
of the MC68HRC705J1 A. All of the informa tion in th is document a pplies
to the MC68HSR705J1A with the exceptions given in this appendix.
C.3 RC Oscillator Connections (External Resistor)
Refer to Appendix A. MC68HRC705J1A for a description of the
resistor-capacitor (RC) oscillator connections with external resistor.
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Technical Data MC68HC705J1A —Rev. 4.0
MC68HSR705J1A
MC68HSR705J1A
C.4 Typical Internal Operating Frequency at 25°C
for High-Speed RC Oscillator Option
Figure C-1. Typical Internal Operating Frequency
at 25°C for High-Speed RC Oscillator Option
For lower frequency operation characteristics, refer to Appendix A.
MC68HRC705J1A.
NOTE: Tolerance for resistance is ±50 percent. When selecting resistor size,
consider t he tolerance t o ensure tha t resulting oscillator fre quency does
not exceed the maximum operating frequency.
1
10
110 100
RESISTANCE (kΩ)
FREQUENCY (MHz)
3.0 V
3.6 V
4.5 V
5.0 V
5.5 V
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MC68HSR705J1A
RC Oscillator Connections (No External Resistor)
MC68HC705J1A —Rev. 4.0 Technical Data
MC68HSR705J1A
C.5 RC Oscillator Connections (No External Resistor)
For maximum cost reduction, the RC oscillator mask connections shown
in Fi gure C-2 allow the on-chip oscillator to be driven with no external
components. This can be accomplished by programming the oscil lator
internal resistor (OSCRES) bit in the mask option register to a logic 1.
When programm ing the OSCRE S bit for the MC68HSR705J1A, an
internal resistor is selected which yields typical internal oscillator
frequencies as shown in Figure C-3. The internal resistance for this
device is different than the resistance of the selectable internal resistor
on the MC68HC705J1A and the MC68HSC705J1A devices.
NOTE: This option is not available on the ROM version of this device
(MC68HC05J1A).
Figure C-2. RC Oscillator Connections (No External Resistor)
MCU
VDD
VSS
C1C2
OSC1
OSC2
OSC1
OSC2
R
EXTERNAL CONNECTIONS LEFT OPEN
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Technical Data MC68HC705J1A —Rev. 4.0
MC68HSR705J1A
MC68HSR705J1A
C.6 Typical Internal Operating Frequency versus Temperature
(N o Ex te rn al Res ist or )
Figure C-3. Typical Internal Operating Frequency
versus Temperature (OSCRES Bit = 1)
NOTE: Due to process variations, operating voltages, and temperature
requirements, the internal resistance and tolerance are unspecified.
Typi cally for a given voltage and tempe ratu re, the fre quency should not
vary more than ±500 kHz. H owever, th is data is n ot guarant eed. It is the
user’s responsibility to ensure that the resulting internal operating
frequency meets the user’s requirements.
3.0 V
3.6 V
4.5 V
5.0 V
5.5 V
FREQUENCY (MHz)
TEMPERATURE (°C)
3.00
2.50
2.00
1.50
1.00
0.50
0.00
–50 0 50 100 150
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MC68HSR705J1A
Package Types and Order Num bers
MC68HC705J1A —Rev. 4.0 Technical Data
MC68HSR705J1A
C.7 Package Types and Order Numbers
Table C-1. MC68HSR705J1A (High-Speed
RC Oscillator Option) Order Numbers(1)
1. Refer to Section 12. Ordering Information for standard part ordering info rmation.
Package
Type Case
Outline Pin
Count Operating
Temperature Order Number
PDIP 738-03 20 0 to 70°C
–40 to +85°CMC68HSR705J1AP(2)
MC68HSR705J1AC(3)P
2. P = plastic dual in-li ne package (PDIP)
3. C = extended temperature range
SOIC 751D-04 20 0 to 70°C
–40 to +85°CMC68HSR705J1ADW(4)
MC68HSR705J1ACDW
4. DW = small out li ne integrated ci rcuit (SOIC)
Cerdip 732-03 20 0 to 70°C
–40 to +85°C MC68HSR705J1AS(5)
MC68HSR705J1ACS
5. S = ceramic dual in- li ne package (cerd ip)
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Technical Data MC68HC705J1A —Rev. 4.0
MC68HSR705J1A
MC68HSR705J1A
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MC68HC705J1A —Rev. 4.0 Tec hnical Data
Index
Technical Data — MC68HC705J1A
Index
A
accumulator register (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
addressing modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
B
block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
brownout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
C
C bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
central processor unit (CPU ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
computer operating properly (COP) module . . . . . . . . . . . . . . . . . . . 97
condition code register (CCR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
COP watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
COP in stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
COP in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
COP register (COPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
COP reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
programmable option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
COPEN bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
instruction set. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
instruction set summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
instruction types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
programming model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
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Technical Data MC68HC705J1A —Rev. 4.0
Index
Index
CPU registers
accumulator register (A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
index register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
program counter register (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
stack pointer register (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
D
data direction registers
data direction register A (DDRA) . . . . . . . . . . . . . . . . . . . . . . . . . 90
data direction register B (DDRB) . . . . . . . . . . . . . . . . . . . . . . . . . 93
data-retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
E
ELAT bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126, 127
DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . 121, 122
driver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
MC68HSC705J1A (high-speed option) . . . . . . . . . . . . . . . . . . . 142
MC68HSR705J1A (high-speed RC oscillator option) . . . . . . . . 145
operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
power considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
typical supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
electrostatic damage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
EPGM bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
EPMSEC bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
EPROM
EPROM security programmable option . . . . . . . . . . . . . . . . . . . . 25
EPROM/OTPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
erasing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38, 40
programming characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
programming register (EPROG). . . . . . . . . . . . . . . . . . . . . . . . . . 39
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Index
MC68HC705J1A —Rev. 4.0 Technical Data
Index
external interrupt module (IRQ). . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
external interrupt pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
external reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
G
general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
H
H bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
I
I bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
index register (X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
addressing modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
instruction set summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
instruction types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
instruction types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
interrupts
external interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73, 74
external interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
external interrupt module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
external interrupt timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75, 107
external interrupt vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
interrupt flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78, 103
interrupt processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
interrupt sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
interrupt stacking order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
IRQ module block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
IRQ status and control register (ISCR) . . . . . . . . . . . . . . . . . . . 106
IRQ/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101, 104
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
optional external interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
pin sensitivity selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
pin triggering option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
port A external interrupts programmable option. . . . . . . . . . . . . . 25
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Technical Data MC68HC705J1A —Rev. 4.0
Index
Index
real-time interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
reset/interrupt vector addresses. . . . . . . . . . . . . . . . . . . . . . . . . . 77
software interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
software interrupt vector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
timer interrupt vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
timer interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76, 112
timer overflow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
IRQ latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
IRQ/VPP pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31, 98, 104
IRQE bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
IRQF bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
IRQR bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
J
junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
L
LEVEL bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
COP timeout period . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
data-retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80, 84
effects on clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
effects on COP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
effects on CPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
effects on EPROM/OTPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
effects on timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
exiting stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
exiting wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
flowchart (STOP/HALT/WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
halt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
STOP instruction flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79, 82
stop recovery timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
timing of stop mode recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
wait mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
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Index
MC68HC705J1A —Rev. 4.0 Technical Data
Index
M
mask option register (M OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
MC68HC705J1A
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
MC68HRC705J1A (RC oscillator option) . . . . . . . . . . . . . . . . . . . . 137
operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
RC oscillator connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
MC68HSC705J1A (high-speed option). . . . . . . . . . . . . . . . . . . . . . 141
DC electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
typical operating current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
typical wait mode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
MC68HSR705J1A (high-speed RC oscillator option) . . . . . . . . . . . 145
operating frequencies (with OSCRES bit set) . . . . . . . . . . . . . . 148
operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
RC oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
RC oscillator connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
EPROM/OTPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
EPROM/OTPROM programming. . . . . . . . . . . . . . . . . . . . . . . . . 38
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
mask option register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
MPGM bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
multifunction timer modu le. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
N
N bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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Technical Data MC68HC705J1A —Rev. 4.0
Index
Index
O
opcode map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
options (mask). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
options (programmable) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
ordering information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
MC68HRC705J1A (RC oscillator option). . . . . . . . . . . . . . . . . . 140
MC68HSC705J1A (high-speed option) . . . . . . . . . . . . . . . . . . . 144
MC68HSR705J1A (high-speed RC oscillator option) . . . . . . . . 149
order numbers . . . . . . . . . . . . . . . . . . . . . . . . . . 135, 140, 144, 149
OSC1 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
OSC2 pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
oscillator
crystal oscillator interna l resistor option. . . . . . . . . . . . . . . . . . . . 25
delay counter programmable option. . . . . . . . . . . . . . . . . . . . . . . 25
on-chip oscillator stabilization delay. . . . . . . . . . . . . . . . . . . . . . . 71
pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
OSCRES bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
P
PA0–PA3 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
package types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
parallel input/output (I/O) ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
pin assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
PIRQ bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
port A
data direction register (DDRA). . . . . . . . . . . . . . . . . . . . . . . . . . . 90
data register (PORTA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
I/O circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
I/O pin interrupts (PA0–PA3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
LED drive capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
pin operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
pulldown register (PDRA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
port B
data direction register (DDRB). . . . . . . . . . . . . . . . . . . . . . . . . . . 93
electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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Index
MC68HC705J1A —Rev. 4.0 Technical Data
Index
I/O circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
pin operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
port B data register (PORTB). . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
pulldown register (PDRB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
power-on reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
program counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
programmable options. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
programming model (CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
pulldown register A (PDRA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
pulldown register B (PDRB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
pulldown resistors
programmable option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
R
RAM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
stack RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
registers
CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
I/O register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
parallel I/O port register summary . . . . . . . . . . . . . . . . . . . . . . . . 88
RESET pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30, 72
resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
COP register (COPR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
COP watchdog reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
external reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
illegal address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
power-on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
power-on reset timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
reset/interrupt vector addresses. . . . . . . . . . . . . . . . . . . . . . . . . . 77
resistors (pulldown)
programmable option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
RT1, RT0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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Technical Data MC68HC705J1A —Rev. 4.0
Index
Index
RTIE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
RTIF bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
RTIFR bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
S
Schmitt trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31, 104, 105
SOSCD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
stack pointer register (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
STOP instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81, 100, 106
stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82, 100
effect on COP watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
effects on timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
STOP instruction flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
stop recovery timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
stop/halt mode programmable option . . . . . . . . . . . . . . . . . . . . . . . . 25
SWAIT bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
SWPDI bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
T
thermal resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
timer
block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
I/O registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76, 112
low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
timer counter register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
timer interrupt vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
timer status and contro l register (TSCR) . . . . . . . . . . . . . . . . . . 112
TOF bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
TOFR bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
TOIE bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
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Index
MC68HC705J1A —Rev. 4.0 Technical Data
Index
V
VDD pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
VSS pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
W
WAIT instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81, 100, 106
wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
effects on timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Z
Z bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
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Technical Data MC68HC705J1A —Rev. 4.0
Index
Index
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MC68HC705J1A/D
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