For application flexibility, burst length, burst type, CAS latency, DLL reset function, write recovery time (tWR) are user

defined variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable

function, additive CAS latency, driver impedance, ODT (On Die Termination), single-ended strobe and OCD (off chip

The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS latency,

burst length, burst sequence, test mode, DLL reset, tWR and various vendor specific options to make DDR2 SDRAM

useful for various applications. The default value of the mode register is not defined, therefore the mode register must be

written after power-up for proper operation. The mode register is written by asserting low on CS, RAS, CAS, E, BA0 and

BA1, while controlling the state of address pins A0 ~ A13. The DDR2 SDRAM should be in all banks precharged (idle)

mode with CKE already high prior to writing into the mode register. The mode register set command cycle time (tMRD) is

required to complete the write operation to the mode register. The mode register contents can be changed using the

same command and clock cycle requirements during normal operation as long as all banks are in the precharged state.

The mode register is divided into various fields depending on functionality. Burst length is defined by A0 ~ A2 with options

of 4 and 8 bit burst length. Burst address sequence type is defined by A3 and CAS latency is defined by A4 ~ A6. A7 is

used for test mode and must be set to low for normal MRS operation. A8 is used for DLL reset. A9 ~ A11 are used for