A6285
Description
The A6285 is designed for LED display applications. This
BiCMOS device includes an On/Off shift register, a Dot
Correction (DC) shift register, accompanying data latches, and
16 MOS constant-current sink drivers with active pull-ups that
can be enabled or disabled as required by the application.
The CMOS shift registers and latches allow direct interfacing
with microprocessor-based systems. With a 3.3 or 5 V logic
supply, typical serial data input rates can reach up to 30 MHz.
The LED drive current level can be set by a single external
resistor, selected by the application designer. A CMOS serial
data output permits cascading of multiple devices in applications
requiring additional drive lines.
Individual LED light intensity can be adjusted to correct for light
intensity variations by using the Dot Correction feature.
Open LED connections can be detected, and then signaled back
to the host microprocessor through the serial data output (SDO
pin). The FAULT output flags an LED open circuit (LOD)
condition or a thermal shutdown (TSD) condition. A staggering
delay on the load outputs during ON/OFF transitions helps to
reduce ground bounce.
6285-DS, Rev. 1
Features and Benefits
▪ 3.0 to 5.5 V logic supply range
▪ Schmitt trigger inputs for improved noise immunity
▪ Power-On Reset (POR)
▪ Up to 80 mA constant-current sinking outputs
▪ LED open circuit detection (LOD)
▪ Dot correction (DC) for adjusting LED light intensity on
each channel with 7-bit resolution
▪ Low-power CMOS logic and latches
▪ High data input rate up to 30 MHz
▪ Active output pull-ups with enable/disable
▪ 20 ns typical staggering delay between outputs
▪ Internal UVLO and thermal shutdown (TSD) circuitry
▪ Fault output flags for an LED open circuit (LOD) or a
thermal shutdown (TSD) condition
Package: 32 Contact QFN (suffix ET)
16-Channel Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
Continued on the next page…
Typical Application
Controller
FAULT
CLK
LE
MODE
SDO
SDO
REXT
A6285
OE
SDI SDI PE
100 KΩ
10 μF
100 nF
OUT0 OUT15
VLED VLED
VDD
VDD
FAULT
CLK
LE
MODE
OE
5 mm × 5 mm
0.90 mm nominal overall height
Not to scale
16-Channel Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6285
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Absolute Maximum Ratings
Characteristic Symbol Notes Min. Max. Unit
Supply Voltage* VDD –0.3 5.5 V
OUTx Current (any single output) IO–90mA
Input Voltage Range* VI VOE, VLE, VCLK, VSDI, VMODE –0.3 VDD + 0.3 V
LED Load Supply Range* VLED –0.3 13.2 V
ESD Rating HBM (JEDEC JESD22-A114, Human Body Model) – 1.5 kV
CDM (JEDEC JESD22-C101, Charged Device Model) – 1.0 kV
Operating Temperature Range (E) TA–40 85 °C
Junction Temperature TJ(max) – 150 °C
Storage Temperature Range Tstg –55 150 °C
*With respect to ground (GND, PGND).
Selection Guide
Part Number Package Packing (estimated)
A6285EET-T 5×5 mm QFN, 32 pin, exposed thermal pad 73 pieces per tube
A6285EETTR-T 5×5 mm QFN, 32 pin, exposed thermal pad 1500 pieces per 7-in reel
The device is available in a 32-lead QFN (package ET), with an
exposed thermal pad. It is lead (Pb) free with 100% matte tin
leadframe plating.
Applications include the following:
▪ Display backlighting
▪ Monocolor, multicolor, or full-color LED display
▪ Monocolor, multicolor, LED Signboard
▪ Multicolor LED lighting
Description (continued)
16-Channel Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6285
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Functional Block Diagram
Status Info:
LOD
015
ON/OFF Shift Register
015
DC Shift Register
0 111 SDO
FAULT
MODE
1
0
CLK
SDI
LE
MODE
1
0
ON/OFF
Register
0
DC Register
06
ON/OFF
Register
1
DC Register
713
ON/OFF
Register
15
DC Register
105 111
Io
Regulator
REXT
OUT0 OUT1 OUT15
GND
PAD
UVLO
POR VDD
VLED
LOD
15
LOD
1
LOD
0
7-Bit
DC
7-Bit
DC
7-Bit
DC
OE
LE
MODE
1
0
TSD
LOD
MODE
TSD
UVLO
VDD
PE
1
0
MODE
01 15
MODE
1
0
Active Pull-up Cell
(1 of 16 Outputs)
ON
5 mA
OUTx
PE
V
LED
Inputs and Outputs Equivalent Circuits
(Note: Resistor values are equivalent resistance and not tested.)
VDD
CLK, SDI, LE,
MODE,
O
¯ ¯ E¯500 Ω
SDO
VDD
FAULT
10 Ω
10 Ω
16-Channel Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6285
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
CLK
LE
OE
GND
VDD
REXT
MODE
FAULT
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
OUT5
PGND
OUT6
OUT7
OUT8
OUT9
PGND
OUT10
SDO
PE
OUT15
OUT14
PGND
OUT13
OUT12
OUT11
PAD
SDI
NC
OUT0
OUT1
PGND
OUT2
OUT3
OUT4
Terminal List Table
Name Number Description
O¯ ¯E¯ 30
Output Enable input. Active low. When O¯ ¯E¯ = High, all OUTx outputs are forced OFF. When O¯ ¯E¯ = Low,
ON/OFF of OUTx outputs are controlled by input data.
GND 29 Logic supply ground.
PE 23 Active Pull-up Enable. When connected to LED Load Supply (VLED) = enabled, when connected to PGND
= disabled.
REXT 27 Reference current input/output terminal.
MODE 26
Logic input, Mode select. When MODE = Low, then SDI, SDO, CLK, LE are connected to ON/OFF control
logic. When MODE = High, SDI, SDO, CLK, LE are connected to dot-correction logic.
NC 2 No connection. Not internally connected.
OUT0 3
Constant current outputs.
OUT1 4
OUT2 6
OUT3 7
OUT4 8
OUT5 9
OUT6 11
OUT7 12
OUT8 13
OUT9 14
OUT10 16
OUT11 17
OUT12 18
OUT13 19
OUT14 21
OUT15 22
PGND 5, 10, 15, 20 Power ground.
CLK 32
Data shift clock input. Note that the internal connections are switched by input at MODE pin. At CLK, the
shift-registers selected by MODE shift the data.
SDI 1 Serial Data In. Data input of serial data interface.
SDO 24 Serial Data Out. Data output of serial data interface.
VDD 28 Logic Supply.
FAULT 25 Error output. FAULT is open drain terminal. FAULT goes low when LOD or TSD detected.
LE 31
Latch Enable input. Note that the internal connections are switched by input at the MODE pin. At LE, the
latches selected by MODE get new data.
PAD – Exposed pad for enhanced thermal dissipation; not connected internally, connect to power ground plane.
Pin-out Diagram
16-Channel Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6285
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS at TA1 = 25°C, VDD = 3.0 to 5.5 V, unless otherwise noted
Characteristic Symbol Test Conditions Min. Typ.2Max. Unit
Logic Supply Voltage Range VDD Operating 3.0 5.0 5.5 V
LED Load Supply Output Voltage VLED Operating – – 12.0 V
Undervoltage Lockout VDD(UV)
VDD 0 5.0 V 2.5 2.7 2.95 V
VDD 5 0.0 V 2.3 2.5 2.75 V
Output Current IO
VDS = 1 V, REXT = 600 Ω70 80 90 mA
VDS = 1 V, REXT = 1.2 kΩ35 40 45 mA
Output to Output Matching Error4Err
1 V = VDS(x), REXT = 600 Ω;
All outputs on – +1.0 +4.4 %
1 V = VDS(x), REXT = 1.2 kΩ;
All outputs on – +1.0 +4.4 %
Load Regulation IOreg
VDS(X) = 1 to 3 V, REXT = 600 ;
All outputs on – – +6.0 %
Output Leakage Current IDSS VOH = 12 V – – 0.5 A
Logic Input Voltage VIH 0.8×VDD –V
DD V
VIL GND – 0.2×VDD V
Logic Input Voltage Hysteresis VIhys All digital inputs 250 – 900 mV
Logic Input Current IIAll digital inputs –1 – 1 A
SDO Voltage VOL IOL = 1 mA – – 0.5 V
VOH IOH = –1 mA VDD
– 0.5 – – V
Supply Current3
IDD(OFF)
REXT = 9.6 kΩ, VOE = 5 V – – 6 mA
REXT = 1.2 kΩ, VOE = 5 V – – 17 mA
IDD(ON)
All outputs on, REXT = 1.2 kΩ, VO = 1 V,
data transfer 30 MHz – – 25 mA
All outputs on, REXT = 600 Ω, VO = 1 V,
data transfer 30 MHz –2640mA
FAULT Output VOUT(0) IOUT = 5 mA; faults asserted – – 0.4 V
IOUT(1) VOUT = 5.5 V, open drain; faults negated – – 1 A
Active Pull-up IOUT(0) VLED = 1 V, all outputs off – 2.8 – mA
Thermal Shutdown Temperature TJTSD Temperature increasing – 165 – °C
Thermal Shutdown Hysteresis TJTSDhys –15–°C
Open LED Detection Threshold VLOD – 0.30 0.40 V
Reference Voltage at REXT VEXT REXT = 600 Ω1.19 1.23 1.28 V
1Tested at 25°C. Specifications are assured by design and characterization over the operating temperature range of –40°C to 85°C.
2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
3Recommended operating range: VO = 1.0 to 3.0 V.
4Err = (IO(min or max) – IO(av)) / IO(av).
Operating Characteristics
16-Channel Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6285
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
SWITCHING CHARACTERISTICS at TA1 = 25°C, VDD = VIH = 3.0 to 5.5 V, VDS = 1 V, VIL = 0 V, REXT = 1.2 k, IO = 40 mA,
VL = 3 V, RL = 51 , CL = 15 pF (see table 9)
Characteristic Symbol Test Conditions Min. Typ.2Max. Unit
Clock Frequency fCLK CLK – – 30 MHz
Clock Pulse Duration twh0/twl0 CLK = High/Low 16 – – ns
Clock Frequency (cascaded) fCLKC CLK – – 25 MHz
LE Pulse Duration twh1 LE = High 20 – – ns
Setup Time
tsu0 SDI to CLK10 – – ns
tsu1 CLK to LE 10 – – ns
tsu2 MODE to CLK 10 – – ns
tsu3 MODE to LE 10 – – ns
Hold Time
th0 CLK to SDI 10 – – ns
th1 LE to CLK 10 – – ns
th2 CLK to MODE 10 – – ns
th3 LE to MODE 10 – – ns
Rise Time
tr0 SDO, 10/90% points (see figure 1) – – 16 ns
tr1
OUTx, VDD = 5 V, DC = 127, 10/90% points
(see figure 2) –1030ns
Fall Time
tf0 SDO, 10/90% points (see figure 1) – – 16 ns
tf1
OUTx, VDD = 5 V, DC = 127, 10/90% points
(see figure 2) –1030ns
Propagation Delay Time
tpd0 CLK to SDO (see figure 1) – – 30 ns
tpd1 MODE to SDO (see figure 1) – – 30 ns
tpd2 O¯ ¯E¯ to OUT0 (see figure 2) – – 60 ns
tpd3 LE to OUT0 (see figure 2) – – 60 ns
tpd4 OUTx to FAULT (see figures 2 and 3) – – 1000 ns
tpd5 LE to IOUT (DC) (see figure 2) – – 200 ns
LOD Sample and Read Time tLOD LE1 to LE21660 – – ns
Output Delay Time td OUTx to OUT(x+1) (see figure 2) 10 20 40 ns
1Tested at 25°C. Specifications are assured by design and characterization over the operating temperature range of –40°C to 85°C.
2Typical data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits d maximum and minimum limits.
SDO
15 pF
OUTx
A6285 51 7
15 pF
A6285
FAULT
A6285 1.2 k7
Parameter Measurement Information
Figure 1. Test circuit for tr0, tf0, td0,
and td1
Figure 2. Test circuit for tr1, tf1, tpd2,
tpd3, tpd5, and tpd6
Figure 3. Test circuit for tpd4
16-Channel Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6285
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Operating Characteristics
IOLC (mA)
VO(V)
0
10
20
30
40
50
60
70
80
90
0 0.30.60.91.21.51.82.12.42.7 3
IO (mA)
VDS = 1 V
DC= 127
REXT = 600 Ω
REXT = 800 Ω
REXT = 1.2 kΩ
REXT = 2.4 kΩ
0
90
80
70
60
50
40
30
20
10
0
100
10
1
0.1
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.00 1020304050607080
VO (V)
IO(max) (mA)
REXT (kΩ)
Figure 4. Value of external reference resistor, REXT, versus
channel Constant Output Current
Figure 5. Output Voltage versus Output Current at various
levels of REXT
Thermal Characteristics
Characteristic Symbol Test Conditions1Value2Units
Package Power Dissipation PDContinuous, TA = 25°C 3.9 W
Package Thermal Resistance RJA 4-layer PCB based on JEDEC standard 32 °C/W
1Additional thermal information available on Allegro website.
2Actual performance significantly affected by application.
50 75 100 125 15025
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
AMBIENT TEMPERATURE IN °C
5.0
0
1.0
2.0
3.0
4.0
Package ET, R
QJA
= 32°C/W
Figure 6. Power Dissipation versus temperature
16-Channel Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6285
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Setting Maximum Channel Current The maximum output
current per channel is set by a single external resistor, REXT,
which is placed between the REXT pin and PGND. The voltage
on REXT, VEXT , is set by an internal band gap. The maximum
channel current is equivalent to the current flowing through
REXT multiplied by 38.4. The maximum channel output current
can be calculated as:
EXT
EXT
IO(max) = R
V38.4 ,
×
(1)
where:
VEXT is 1.25 V typical, and
REXT is the value of the user-selected external resistor, which
should not be less than 600 Ω, corresponding to 80 mA.
Figure 4 shows the maximum per channel constant output cur-
rent, IO(max), of OUT0 to OUT15, versus REXT , , the value of the
resistor between REXT terminal and ground.
Dot Correction The A6285 can independently fine-adjust
the current of each output channel, a feature referred to as dot
correction. This feature is used to compensate for the brightness
deviations of the LEDs connected to the output channels, OUT0
through OUT15.
Each of the 16 channels can be programmed with a 7-bit word.
The channel output can be adjusted in 128 steps from 0% to
100% of the maximum programmable per channel output cur-
rent, IO(max). Equation 2 determines the output current for each
OUTx:
IOx = IO(max) × DCx ,
127
(2)
where DCx is the programmed dot-correction value (0, 1, …127)
for each output channel.
Dot correction data is entered for all channels at the same time.
The complete dot correction data format consists of sixteen 7-bit
words, which form a 112-bit (16 × 7) wide serial data packet. The
data for each channel is sent in a continuous sequence, and all
data is clocked in with the MSB first, as shown in figure 7.
To input data into the Dot Correction register, LE should be set
low, and MODE must be set high. MODE sets the input shift reg-
ister to 112-bit width. After all serial data is clocked in, a rising
edge on the LE terminal latches the data into the Dot Correction
register. The timing sequence is shown in figure 9.
All Channel Output Enable-Disable All OUTx channels
of the A6285 can switched off using the O¯ ¯E¯ pin. When O¯ ¯E¯ is
set high, all OUTx outputs are disabled, regardless of the on/off
status of any OUTx. When O¯ ¯E¯ is set to low, the on/off status of
each OUTx is determined by the state of the latches in the On/Off
register. O¯ ¯E¯ can be PWMed to control the average current, which
controls the LED brightness of all outputs, in addition to the DC
function.
Individual Channel Output Enable-Disable Each OUTx
channel can be switched on or off independently. Each of the
channels can be programmed with a 1-bit word.
On/off data is entered for all channels at the same time. The
complete on/off data format consists of sixteen 1-bit words, which
form a 16-bit wide serial data packet. The data for each channel is
sent in a continuous sequence, and all data is clocked in with the
MSB first, as shown in figure 8.
To input data into the On/Off register, LE must be set low, and
MODE must be set low. LE allows on/off data to enter the input
shift register, and MODE sets the input shift register to 16-bit
width. After all serial data is clocked in, a rising edge on the LE
terminal latches the data into the On/Off register and moves the
LOD data at the Open Circuit Detector into the input shift regis-
ter. The timing sequence is shown in figure 9.
Functional Description
DC 15.6
111
DC 14.6
104
DC 0.6
6
DC 0.0
0
DC 15.0
105
DC 1.0
7
LSB MSB
DCOUT0 DCOUT15
DCOUT2 through DCOUT14
… … …
Figure 7. Dot Correction (DC) data format
1
On/Off On/Off
14 15
On/Off On/Off
0
LSB MSB
OUT0OUT1through OUT14 OUT15
…
Figure 8. Individual output on-off data format
16-Channel Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6285
9
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Delay Between Outputs The A6285 has graduated delay
circuits between outputs. The fixed delay time is 20 ns (typical).
OUT0 has no delay, OUT1 has a 20 ns delay, OUT2 has a 40 ns
delay, and so forth. This delay prevents large in-rush currents
that create ground bounce, which reduces power supply bypass
capacitor requirements when the outputs turn on. The delays
work during switch on and switch off of each output channel.
Serial Interface Data Transfer Rate The A6285
includes a flexible serial data interface, which can be connected
to a microcontroller or a digital signal processor. Only 3 pins are
required to input data into the device. The rising edge of a CLK
signal shifts the data from SDI pin to the input shift register. After
all data is clocked in, a rising edge of LE latches the serial data
to the On/Off register. All data is clocked in with the MSB first,
while LE is set low.
Multiple A6285 devices can be cascaded by connecting the SDO-
pin of one device with the SDI pin of the following device. The
SDO pin can also be connected to the microcontroller or micro-
processor in order to transmit LOD information from the A6285.
Figure 9. Output on-off and Dot Correction timing
16-Channel Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6285
10
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Figure 10 shows an example application with n cascaded A6285
devices connected to a controller. The maximum number of
cascaded devices depends on the application system and the data
transfer rate. The minimum data input transfer rate is calculated
as follows:
f
CLK = 112 × fUPDATE × n ,
(3)
where:
fCLK is the minimum data input frequency for CLK and SDI,
fUPDATE is the update rate of the entire cascaded system, and
n is the number of cascaded A6285 devices.
Operating Modes The A6285 has two operating modes, deter-
mined by the MODE signal:
• On-Off mode (MODE = low)
• Dot Correction mode (MODE = high)
Fault Output, FAULT The open-drain output FAULT is used
to report both of the fault flags, LOD and TSD. During normal
operating conditions, the internal transistor connected to the
FAULT pin is turned off. The voltage on FAULT is pulled up to
VDD through a external pull-up resistor.
If an LOD or TSD condition is detected, the internal transistor is
turned on, and FAULT is pulled to PGND. Because FAULT is an
open-drain output, multiple ICs can be ORed together and pulled-
up to VDD with a single pull-up resistor, as shown in figure 10.
This reduces the number of signals needed to report faults.
To determine whether the fault is a TSD or an LOD, LOD can be
masked by setting O¯ ¯E¯ = high. However, it cannot be determined
if both a TSD and an LOD condition are present. The FAULT
Truth Table is shown on page 11.
Active Pull-up Enable, PE The A6285 provides active
pull-ups on each output determined by the PE pin. When the
LED supply, VLED , is tied to the PE pin, the active pull-ups are
enabled. When the PE pin is tied to ground, the active pull-ups
are disabled. The Active Pull-up Enable is also current-limited to
2.8 mA typical, preventing possible damage to the device in the
event of a short-to-ground. This feature can eliminate ghosting in
multiplexing applications.
Undervoltage Lockout (UVLO) and Power-On Reset
(POR) The A6285 includes an internal undervoltage lockout
circuit that disables the outputs in the event that the logic supply
voltage drops below a minimum acceptable level. This feature
prevents the display of erroneous information, a function neces-
sary for some critical applications. A Power-On Reset (POR)
is performed upon recovery of the logic supply voltage after a
UVLO event and at power-up. During POR, all internal shift
registers and latches are set to 0.
Thermal Shutdown Protection and Fault Flag (TSD) The
A6285 provides thermal protection when the device is over-
heated, typically a result of excessive power being dissipated in
the outputs. If the junction temperature exceeds the threshold
A6285
SDI SDO
OUT15
CLK
MODE
LE
REXT
FAULT
A6285
SDI SDO
CLK
MODE
LE
REXT
FAULT
IC nIC 1
5
SDI
PE
CLK
MODE
LE
FAULT
Controller
SDO
100 k
100 nF
VLED
VLED
VDD
100 nF
VDD VDD
……
OE OE OE
OUT0 OUT15PE OUT0
VLED VLED
Figure 10. Schematic of cascaded A6285 devices
16-Channel Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6285
11
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
temperature, TTSDF
, of 165°C (typical), all driver outputs will
be turned off and a TSD fault will be flagged. The TSD flag will
pull the FAULT output pin to PGND (low). After a 15°C (typi-
cal) drop in junction temperature, the outputs will turn back on
and the FAULT pin will be pulled back to VDD (high). The input
shift register and the latch register will remain active during a
TSD event. Therefore, there is no need to reset the data in the
output latches. However, the TSD cycle will continue until the
thermal problem is corrected.
LED Open Detection (LOD) The A6285 provides LED open
circuit detection. This circuit flags a fault and pulls the FAULT
pin to PGND (low) if any of the 16 OUTx LEDs are open or
disconnected from the circuit.
The LOD circuit flags a fault when all of the following conditions
are met:
• O¯ ¯E¯ is set low
• The voltage at each OUTx pin is sampled after being turned on
• VOUTx < VLOD (0.3 V typical)
MODE may be set either high or low. However, to perform a
complete LOD cycle, which includes reading the LOD status of
each OUTx, MODE must be set low.
A complete LOD cycle is described as follows:
1. On/Off data is clocked into the input shift register.
2. LE is pulsed to move the On/Off data into the On/Off Reg-
ister. The data is moved on the rising edge of LE. If an LOD
condition is present, the FAULT output is immediately pulled
to PGND (low).
3. Data present at the Open Circuit Detector (sampled when data
was moved into the On/Off Register on the previous transition
of LE) is immediately moved into the input shift register on
the same rising edge of LE.
If no LOD condition was previously detected, all 0s are pres-
ent at the Open Circuit Detector. Thus, all 0s are moved into
the input shift register. This gives the appearance of “clearing”
the input shift register every time On/Off data is moved into
the On/Off Register, although in reality, the previous LOD
status is being moved into the input shift register.
If an LOD condition was previously detected, a 1 for each
open LED will be moved from the Open Circuit Detector into
the input shift register, where it can be read on the SDO pin.
4. The existing LOD condition is sampled within 2 μs of the out-
puts turning on and the resulting status data waits at the Open
Circuit Detector until moved into the input shift register on the
rising edge of the next LE pulse.
5. The cycle is repeated when new On/Off data is clocked into
the input shift register. As new data is being clocked in, LOD
status data is being clocked out of the SDO pin, where it can
be read by a microprocessor.
Note: It is not necessary to load new On/Off data in order to view
the LOD status waiting at the Open Circuit Detector. A second
LE pulse will put the LOD data into the input shift register. How-
ever, LOD data that is presently in the input shift register will be
moved into the On/Off Register, generating a “blank” display.
Such a blank display may be undesirable; therefore, a second
LE pulse should not be applied without first clocking in useful
On/Off data for updating the display.
The update interval between LE pulses ( LE1 to LE2 ), referred
to as the LOD Sample and Read Time, tLOD
, must be at least
1660 ns to allow for settling and staggered delays. Figure 11
shows the LOD serial data format. The FAULT truth table is
shown below.
1
LOD LOD
14 15
LOD LOD SDO
0
LSB MSB
OUT0OUT1through OUT14 OUT15
…
Figure 11. Individual output LOD data format
FAULT Truth Table Conditions Fault Output
Junction Temperature Outx Voltage Output Enable, O¯ ¯E¯
TJ < TTSD Outx > VLOD HH
TJ < TTSD Outx < VLOD HH
TJ < TTSD Outx > VLOD LH
TJ < TTSD Outx < VLOD LL
TJ > TTSD Outx > VLOD HL
TJ > TTSD Outx < VLOD HL
TJ > TTSD Outx > VLOD LL
TJ > TTSD Outx < VLOD LL
16-Channel Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6285
12
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Load Supply Voltage (VLED)
These devices are designed to operate with driver voltage drops
(VDS) of 1.0 to 3.0V, with one or more LED forward voltages,
VF , of 1.2 to 4.0 V. If higher voltages are dropped across the
driver, package power dissipation will increase significantly. To
minimize package power dissipation, it is recommended to use
the lowest possible load supply voltage, VLED, or to set any series
voltage dropping, VDROP , according to the following formula:
VDROP = VLED – VF – VDS ,
with VDROP = IO× RDROP for a single driver or for a Zener diode
(VZ), or for a series string of silicon diodes (approximately 0.7 V
per diode) for a group of drivers (see figure 3). If the available
voltage source will cause unacceptable power dissipation and
series resistors or diodes are undesirable, a voltage regulator can
be used to provide VLED.
For reference, typical LED forward voltages are:
LED Type VF (V)
White 3.5 to 4.0
Blue 3.0 to 4.0
Green 1.8 to 2.2
Yellow 2.0 to 2.1
Amber 1.9 to 2.65
Red 1.6 to 2.25
Infrared 1.2 to 1.5
Pattern Layout
The logic and power grounds should be kept separate, terminated
at one location. The exposed metal pad must be connected to a
large power ground plane, allowing the copper to dissipate heat.
Where multiple devices are cascaded, multilayer boards are
recommended.
REXT should be placed as close as possible to the device, keep-
ing a short distance between the REXT pin and ground.
Decoupling capacitors should be used liberally. 0.1 μF should
be placed on the logic supply pin, and 10 μF placed between
the common VLED line and the device ground at least at every
second device.
Package Power Dissipation (PD)
The maximum allowable package power dissipation based on
package type is determined by:
PD(max) = (150 – TA) / RθJA
,
where RθJA is the thermal resistance of the package mounted on
the circuit board, determined experimentally. Power dissipation
levels based on the package are shown in the Package Thermal
Characteristics section (see page 7).
The actual package power dissipation is determined by:
PD(act) = DC × (VDS × IO× 16) + (VDD× IDD) ,
where DC is the duty cycle. The value 16 represents the maxi-
mum number of available device outputs.
When the load supply voltage, VLED, is greater than 3 to 5 V, and
PD(act) > PD(max), an external voltage reducer (VDROP) must be
used (see figure 12).
Reducing the percent duty cycle, DC, will also reduce power dis-
sipation.
Application Information
Figure 12. Typical application voltage drops
16-Channel Constant-Current Latched LED Driver
with Open LED Detection and Dot Correction
A6285
13
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package ET, 5 mm x 5 mm, 32-pin QFN with Exposed Thermal Pad
For the latest version of this document, visit our website:
www.allegromicro.com
Copyright ©2007-2008, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per-
mit improvements in the per for mance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The in for ma tion in clud ed herein is believed to be ac cu rate and reliable. How ev er, Allegro MicroSystems, Inc. assumes no re spon si bil i ty for its use;
nor for any in fringe ment of patents or other rights of third parties which may result from its use.
32
32
2
1
2
1
A
ATerminal #1 mark area
BExposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
All dimensions nominal, not for tooling use
(reference JEDEC MO-220VHHD-6)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
CReference land pattern layout (reference
IPC7351 QFN50P500X500X100-33V6M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
B
32
2
1
PCB Layout Reference View
3.40
3.40
0.50
5.00 ±0.15
5.00 ±0.15
0.90 ±0.10
0.25 +0.05
–0.07
0.40 +0.15
–0.10
3.40
3.40
0.30
1
0.50
1.00
5.00
5.00
C
C0.08
33X SEATING
PLANE
C
D
DCoplanarity includes exposed thermal pad and terminals
