GA03JT12-247
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S
D
G
Normally – OFF Silicon Carbide
Junction Transistor
Features Package
175 °C Maximum Operating Temperature
Gate Oxide Free SiC Switch
Exceptional Safe Operating Area
Excellent Gain Linearity
Temperature Independent Switching Performance
Low Output Capacitance
Positive Temperature Coefficient of RDS,ON
Suitable for Connecting an Anti-parallel Diode
RoHS Compliant
TO-247AB
Advantages Applications
Compatible with Si MOSFET/IGBT Gate Drive ICs
> 20 µs Short-Circuit Withstand Capability
Lowest-in-class Conduction Losses
High Circuit Efficiency
Minimal Input Signal Distortion
High Amplifier Bandwidth
Down Hole Oil Drilling, Geothermal Instrumentation
Hybrid Electric Vehicles (HEV)
Solar Inverters
Switched-Mode Power Supply (SMPS)
Power Factor Correction (PFC)
Induction Heating
Uninterruptible Power Supply (UPS)
Motor Drives
Absolute Maximum Ratings
Parameter Symbol Conditions Value Unit Notes
Drain – Source Voltage VDS VGS = 0 V 1200 V Fig. 6
Continuous Drain Current ID TC = 150 °C 3 A Fig. 19
Continuous Gate Current IGM 1 A
Turn-Off Safe Operating Area RBSOA TVJ = 175 oC, IG = 1 A,
Clamped Inductive Load
ID,max = 3
@ VDS VDSmax A Fig. 16
Short Circuit Safe Operating Area SCSOA TVJ = 175 oC, IG = 1 A, VDS = 800 V,
Non Repetitive 20 µs
Reverse Gate – Source Voltage VSG 30 V
Reverse Drain – Source Voltage VSD 25 V
Power Dissipation Ptot TC = 150 °C 15 W Fig. 14
Storage Temperature Tstg -55 to 175 °C
Electrical Characteristics
On State Characteristics
Off State Characteristics
S
G
D
D
VDS = 1200 V
RDS(ON) =
470 mΩ
ID @ Tc=150°C = 3 A
hFE Tc=25°C = 54
Parameter Symbol Conditions
Value
Unit Notes
Min. Typical Max.
Drain – Source On Resistance RDS(ON)
ID = 3 A, Tj = 25 °C
ID = 3 A, Tj = 125 °C
ID = 3 A, Tj = 175 °C
470
530
730
m Fig. 5
Gate Forward Voltage VGS(FWD) IG = 500 mA, Tj = 25 °C
IG = 500 mA, Tj = 175 °C 3.3
3.1 V Fig. 4
DC Current Gain hFE VDS = 5 V, ID = 3 A, Tj = 25 °C
VDS = 5 V, ID = 3 A, Tj = 175 °C 54
32 – Fig. 5
Drain Leakage Current IDSS
VR = 1200 V, VGS = 0 V, Tj = 25 °C
VR = 1200 V, VGS = 0 V, Tj = 125 °C
VR = 1200 V, VGS = 0 V, Tj = 175 °C
0.1
0.2
0.5
10
50
100
A Fig. 6
Gate Leakage Current ISG VSG = 20 V, Tj = 25 °C 20 nA
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Electrical Characteristics
Capacitance Characteristics
Switching Characteristics1
1 – All times are relative to the Drain-Source Voltage VDS
Thermal Characteristics
Figures
Figure 1: Typical Output Characteristics at 25 °C Figure 2: Typical Output Characteristics at 125 °C
Parameter Symbol Conditions
Value
Unit Notes
Min. Typical Max.
Input Capacitance Ciss VGS = 0 V, VD = 800 V, f = 1 MHz 315 pF Fig. 7
Reverse Transfer/Output Capacitance Crss/Coss VD = 800 V, f = 1 MHz 15 pF Fig. 7
Output Capacitance Stored Energy EOSS VGS = 0 V, VD = 1000 V, f = 1 MHz 6.1 µJ Fig. 8
Internal Gate Resistance, Zero Bias RG
(
INT-ZERO
)
f = 1 MHz, VAC = 25 mV, Tj = 175 ºC 18.0
Internal Gate Resistance, On RG
(
INT-ON
)
VGS > 2.5 V 0.9
Turn On Delay Time td
(
on
)
Tj = 25 ºC, VDS = 800 V, ID = 3 A,
RG(EXT) = 40 , CG = 9 nF,
VG = 25/-5 V, Load = 267
Refer to Fig. 20 for IG Waveform
17 ns
Fall Time, VDS t
f
20 ns Fig. 9, 11
Turn Off Delay Time td
(
off
)
29 ns
Rise Time, VDS t
r
30 ns Fig. 10, 12
Turn On Delay Time td
(
on
)
Tj = 175 ºC, VDS = 800 V, ID = 3 A,
RG(EXT) = 40 , CG = 9 nF,
VG = 25/-5 V, Load = 267
Refer to Fig. 20 for IG Waveform
14 ns
Fall Time, VDS t
f
19 ns Fig. 9
Turn Off Delay Time td
(
off
)
23 ns
Rise Time, VDS t
r
33 ns Fig. 10
Turn-On Energy Per Pulse Eon Tj = 25 ºC, VDS = 800 V, ID = 3 A,
RG(EXT) = 40 , CG = 9 nF,
VG = 25/-5 V, Load = 1.05 mH
84 µJ Fig. 9, 11
Turn-Off Energy Per Pulse Eoff
9 µJ Fig. 10, 12
Total Switching Energy Etot
93 µJ
Turn-On Energy Per Pulse Eon Tj = 175 ºC, VDS = 800 V, ID = 3 A,
RG(EXT) = 40 , CG = 9 nF,
VG = 25/-5 V, Load = 1.05 mH
79 µJ Fig. 9
Turn-Off Energy Per Pulse Eoff
10 µJ Fig. 10
Total Switching Energy Etot
89 µJ
Thermal resistance, junction - case RthJC 1.64 °C/W Fig. 17
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Figure 3: Typical Output Characteristics at 175 °C Figure 4: Typical Gate Source I-V Characteristics vs.
Temperature
Figure 5: Normalized On-Resistance and Current Gain vs.
Temperature Figure 6: Typical Blocking Characteristics
Figure 7: Input, Output, and Reverse Transfer Capacitance Figure 8: Output Capacitance Stored Energy
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Figure 9: Typical Turn On Energy Losses and Switching
Times vs. Temperature Figure 10: Typical Turn Off Energy Losses and Switching
Times vs. Temperature
Figure 11: Typical Turn On Energy Losses and Switching
Times vs. Drain Current Figure 12: Typical Turn Off Energy Losses and Switching
Times vs. Drain Current
Figure 13: Typical Hard Switched Device Power Loss vs.
Switching Frequency 2 Figure 14: Power Derating Curve
2 – Representative values based on device switching energy loss. Actual losses will depend on gate drive conditions, device load, and circuit topology.
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Figure 15: Forward Bias Safe Operating Area at Tc = 25 °C Figure 16: Turn-Off Safe Operating Area
Figure 17: Transient Thermal Impedance Figure 18: Drain Current Derating vs. Pulse Width
Figure 19: Drain Current Derating vs. Temperature Figure 20: Typical Gate Current Waveform
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Driving the GA03JT12-247
A: Gate Drive Theory of Operation
The SJT is a current controlled transistor which requires a positive gate current for turn-on as well as to remain in on-state. An ideal gate
current waveform for ultra-fast switching of the SJT, while maintaining low gate drive losses, is shown in Figure 21.
Figure21:IdealizedGateCurrentWaveform
A:1: Gate Currents, IG,pk/-IG,pk and Voltages during Turn-On and Turn-Off
An SJT is rapidly switched from its blocking state to on-state, when the necessary gate charge, QG, for turn-on is supplied by a burst of high
gate current, IG,on, until the gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged.
,
The IG,pon pulse should ideally terminate, when the drain voltage falls to its on-state value, in order to avoid unnecessary drive losses during
the steady on-state. In practice, the rise time of the IG,on pulse is affected by the parasitic inductances, Lpar in the TO-247 package and drive
circuit. A voltage developed across the parasitic inductance in the source path, Ls, can de-bias the gate-source junction, when high drain
currents begin to flow through the device. The applied gate voltage should be maintained high enough, above the VGS,ON level to counter
these effects.
A high negative peak current, -IG,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from
the gate, and achieve rapid turn-off. While satisfactory turn off can be achieved with VGS = 0 V, a negative gate voltage VGS may be used in
order to speed up the turn-off transition.
A:2: Steady On-State
After the device is turned on, IG may be advantageously lowered to IG,steady for reducing unnecessary gate drive losses. The IG,steady is
determined by noting the DC current gain, hFE, of the device.
The desired IG,steady is determined by the peak device junction temperature TJ during operation, drain current ID, DC current gain hFE, and a
50 % safety margin to ensure operating the device in the saturation region with low on-state voltage drop by the equation:
,
, 1.5
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B: Gate Drive Implementation Examples
B:1: Using the IXYS IX2204 Gate Driver
The IXYS IX2204 is a dual output gate drive integrated circuit which can be used to drive an SJT by supplying the required gate drive current
IG in a low-power gate drive solution. This configuration features an external gate capacitor, CG, which creates the brief current peak IG,on
during device turn-on and IG,off during turn-off for fast switching and an external gate resistor RG(EXT) to set the continuous gate current IG,steady
required for the device to remain on. This configuration is shown in Figure 1 with further details provided below.
Figure 1: Gate drive configuration using an IXYS IX2204 gate drive IC.
Table 1: Recommended Component List for implementing the IX2204 based Gate Drive for the GA03JT12-247
Reference Component Description Suggested Part
RG
(
EXT
)
Gate Resistance, External 2.0 , 2 W CRM2512-JW-2R2ELF
CG Gate Capacitance 10 nF C1812C103J1GACTU
RCG Damping Resistor 1.0 , 0.5 W ERJ-1TYJ1R0U
DRG Silicon Schottky Diode 40 V, 2 A SS24T3G
Rb BJT Base Resistor 1.0 , 0.5 W ERJ-1TYJ1R0U
QHA, QHB Current Boost NPN 40 V, 8 A, Silicon NPN BJT MJD44H11
QL
A
, QLB Current Boost PNP 40 V, 8 A, Silicon PNP BJT MJD45H11
U1 Signal Isolator Opto-Isolator –or– Transformer Isolator
A
CPL-4800 / ADUM3210
X1 DC/DC Converter, VGH Supply VOUT = +20 V, VIN = +12 V, 2 W, VISO = 5.2
kV MGJ2D122005SC
X2 DC/DC Converter, VGL Supply VOUT = +5 V, VIN = +12 V, 3 W, VISO = 3.0 kV MEV3S1205SC
X3 DC/DC Converter, VEE Supply VOUT = -5 V, VIN = +12 V, 2 W, VISO = 5.2 kV MGJ2D122005SC
B:2: Voltage Supply Selection
The IX2204 gate drive design requires three supply voltages VGH, VGL, and VEE (listed in Table 2) optionally supplied through DC/DC
converters. During device turn-on, VGH charges the external capacitor CG thereby delivering the narrow width, high current pulse IG,on to the
SJT gate and charges the SJT’s internal terminal capacitances CGD and CGS. For a given level of parasitic inductance in the gate circuit and
SJT package, the rise time of IG,on is controlled by the choice of VGH and CG. During the steady on-state, VGL in combination with the internal
and external gate resistances provides a continuous gate current for the GA03JT12-247 to remain on. The VEE supply sets the gate negative
during turn-off and steady off-state for faster switching and to avoid spurious turn-on which may be caused by external circuit noise. The
power rating of the voltage supplies should be adequate to meet the gate drive power requirements as determined by
, 1
2
, 1
2
,
,
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Table 2: IX2204 Gate Drive Example Component List
Symbol Parameter
Values
Range Typical
VGH Supply Voltage, Driver Output A 15 – 20 + 20.0
VGL Supply Voltage, Driver Output B 5.0 – 7.0 + 5.0
VEE Negative Supply Voltage -10 – GND - 5.0
B:3: Gate Capacitor CG Selection
Figure 23: Primary gate drive circuit passive components with series gate resistance Schottky rectifier.
An external gate capacitor CG connected directly to the device gate pin delivers the positive current peak IG,on during device turn-on and the
negative current peak IG,off during turn-off. A low value resistor RCG is connected in series with CG to damp potential high-frequency oscillation.
A high value resistor Rch in parallel with CG sets the SJT gate to a defined potential (-VEE) during steady off-state.
At device turn-on, CG is pulled to VGH which produces a transient peak of gate voltage and current. This current peak rapidly charges the
internal SJT CGS and CGD capacitances. A Schottky diode, DRG, in series with RG(EXT) blocks any CG induced current from draining out through
RG(EXT) and ensures that all of the charge within CG flows only into the device gate, allowing for an ultra-fast device turn-on. During steady on-
state, a potential of VGH - VGS = VGH – 3 V is across CG. When the device is turned off, CG is pulled to negative VEE and VGS is pulled to a
transient peak of VGS,turn-off = VEE – (VGH – 3 V), this induces the negative current peak IG,off out of the gate which discharges the SJT internal
capacitances.
B:4: External Gate Resistor RG(EXT) Selection
An external gate resistor RG(EXT) connected directly to the SJT gate pin acts to deliver a continuous current IG,steady during steady on-state. The
gate current is determined by:
,
The on-state gate-source voltage VGS(FWD) can be approximated to 3 V and the Schottky on-state voltage VSch can be approximated to 0.3 V
which simplifies the equation to:
,
3.3
The desired IG,steady is determined by the peak device junction temperature TJ during operation, drain current ID, DC current gain hFE, and a 50
% safety margin to avoid operating the device in saturation. IG,steady may also be approximated from the temperature dependent on-state curves
of the device in Figures Error! Reference source not found. – Error! Reference source not found., provided that a 50 % increase is given.
Table 3: Passive Output Component List
Symbol Parameter Values
Range Typical
Units
CG Gate Capacitor, External 5 – 20 10 nF
RCG Damping Resistor of Gate Capacitor 0.5 – 2.0 1.0
Rch Charging Resistor 500 – 10k 1k
RG
(
EXT
)
Gate Resistor, External 0.4 – 5 2.0
RG
(
INT-ON
)
Gate Resistance, Internal, On-State 0.8 – 1.5 0.9
DRG Schottky Diode of Gate Resistor -- --
IG
CG
RG(EXT)
D
S
DRG
RG(INT)
RCG
VGL / VEE
VGH / VEE
Rch G
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B:5: Optional Gate Current Boost Network
An optional output totem-pole network may be attached to the IX2204 output pins as shown in Figure 22 using either silicon BJTs (shown) or
MOSFETs. This configuration allows the IX2204 to directly drive the BJT bases or MOSFET gates and not supply the full peak and steady
state gate current entering the SJT gate. The primary gate current delivery device is transferred to the discrete components which have higher
power dissipation ratings than the IX2204.
B:6: Voltage Supply Isolation
The DC/DC supply voltage converters are suggested to provide isolation at a minimum of twice the working VDS on the SJT transistor during
off-state to provide adequate protection to circuitry external to the gate drive circuit. Suggested DC/DC converters have an isolation of 3.0 kV
or greater. Alternatively, DC/DC converter galvanic isolation may be bypassed and direct connection of variable voltage supplies may be done,
this may be convenient during testing and prototyping but carries risk and is not suggested for extended usage.
Figure 24: Typical DC/DC converter configuration
B:7: Signal Isolation
The gate supply signal is suggested to be isolated to twice the working VDS on the SJT during off-state to provide adequate protection to
circuitry external to the gate drive circuit. This may be done using opto or galvanic isolation techniques.
B:8: Additional Features
The IX2204 has additional functionality available which is unused in the given configuration. Desaturation detection and fault status monitoring
may be implemented by un-grounding the DESAT, BLANK, and TRISTATE pins and configuring them as recommended in the IX2204
datasheet, available from IXYS. Active miller clamping is also available on other gate drive ICs which may also be desired in some SJT
switching applications but is not required, refer to specific gate drive IC datasheets for more information.
C: Alternative Gate Drive ICs
dividual product manufacturers.
Table4 features a partial list of alternative gate drive ICs which may be used for driving the GA03JT12-247; specific product information
should be obtained from the individual product manufacturers.
Table 4: Additional Commercial Gate Drivers Compatible with GA06JT12-247
Features
Manufacturer Part Number
Optical Signal
Isolation
Desaturation
Detection
Active Miller
Gate Clamping3
High Side
Capability
Number of
Outputs
A
vago Tech. HCPL-316J – 1
A
vago Tech. HCPL-322J 1
IXYS IXD_604 – – – 2
IXYS IXD_614 – – – 1
Micrel MIC4452YN – – – 1
Microsemi LX4510 – – – 1
Texas Instruments UCC27322 – – – 1
3 – Active Miller Gate Clamping recommended for VEE = GND switching applications as SJT and/or output BJT secondary gate discharge path.
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Package Dimensions
TO-247AB PACKAGE OUTLINE
NOTE
1. CONTROLLED DIMENSION IS INCH. DIMENSION IN BRACKET IS MILLIMETER.
2. DIMENSIONS DO NOT INCLUDE END FLASH, MOLD FLASH, MATERIAL PROTRUSIONS
Revision History
Date Revision Comments Supersedes
2014/08/26 7 Updated Electrical Characteristics
2014/02/05 6 Updated Electrical Characteristics
2013/12/18 5 Updated Gate Drive Section
2013/11/12 4 Updated Electrical Characteristics
2013/08/30 3 Updated Switching Characteristics
Published by
GeneSiC Semiconductor, Inc.
43670 Trade Center Place Suite 155
Dulles, VA 20166
GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice.
GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any
intellectual property rights is granted by this document.
GeneSiC is not responsible for third-party component performance and does not guarantee similar results.
Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft
navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal
injury and/or property damage.
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SPICE Model Parameters
This is a secure document. Please copy this code from the SPICE model PDF file on our website
(http://www.genesicsemi.com/images/products_sic/sjt/GA03JT12-247_SPICE.pdf) into LTSPICE
(version 4) software for simulation of the GA03JT12-247.
* MODEL OF GeneSiC Semiconductor Inc.
*
* $Revision: 1.2 $
* $Date: 26-AUG-2014 $
*
* GeneSiC Semiconductor Inc.
* 43670 Trade Center Place Ste. 155
* Dulles, VA 20166
*
* COPYRIGHT (C) 2014 GeneSiC Semiconductor Inc.
* ALL RIGHTS RESERVED
*
* These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY
* OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED
* TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
* PARTICULAR PURPOSE."
* Models accurate up to 2 times rated drain current.
*
.model GA03JT12 NPN
+ IS 3.01E-49
+ ISE 1.00E-27
+ EG 3.2
+ BF 58.5
+ BR 0.55
+ IKF 200
+ NF 1
+ NE 2
+ RB 18.0
+ RBM 0.9
+ IRB 1e-4
+ RE 0.184170194
+ RC 0.342829806
+ CJC 1.37E-10
+ VJC 3.150960833
+ MJC 0.43821105
+ CJE 2.97E-10
+ VJE 2.901930244
+ MJE 0.475141754
+ XTI 3
+ XTB -1.24
+ TRC1 5.00E-3
+ VCEO 1200
+ ICRATING 3
+ MFG GeneSiC_Semiconductor
*End of GA03JT12 SPICE Model
