1
Power Factor Correction Controllers
ISL6730A, ISL6730B, ISL6730C, ISL6730D
The ISL6730A, ISL6730B, ISL6730C, ISL6730D are active
Power Factor Correction (PFC) controller ICs that use a boost
topology. The controllers are suitable for AC/DC power
systems, up to 2kW and over the universal line input.
The ISL6730A, ISL6730B, ISL6730C, ISL6730D operate in
Continuous Conduction Mode (CCM). Accurate input current
shaping is achieved with a current error amplifier. A patent
pending breakthrough negative capacitance technology
minimizes zero crossing distortion and reduces the magnetic
components size. The small external components result in a
low cost design without sacrificing performance.
The internally clamped 12.5V gate driver delivers 1.5A peak
current to the external power MOSFET. The ISL6730A,
ISL6730B, ISL6730C, ISL6730D provide a highly reliable
system that is fully protected. Protection features include
cycle-by-cycle overcurrent, over power limit, over-temperature,
input brownout, output overvoltage and undervoltage
protection.
The ISL6730A, ISL6730B provide excellent power efficiency
and transitions into a power saving skip mode during light load
conditions, thus improving efficiency automatically. The
ISL6730A, ISL6730B, ISL6730C, ISL6730D can be shut down
by pulling the FB pin below 0.5V or grounding the BO pin. The
ISL6730C, ISL6730D have no skip mode.
Two switching frequency options are provided. The ISL6730B,
ISL6730D switch at 62kHz, and the ISL6730A, ISL6730C
switch at 124kHz.
Features
• Reduce component size requirements
- Enables smaller, thinner AC/DC adapters
- Choke and cap size can be reduced
- Lower cost of materials
• Excellent power factor over line and load regulation
- Internal current compensation
- CCM Mode with Patent pending IP for smaller EMI filter
•Better light load efficiency
- Automatic pulse skipping
- Programmable or automatic shutdown
• High reliable design
- Cycle-by-cycle current limit
- Input average power limit
- OVP and OTP protection
- Input brownout protection
• Small 10 Ld MSOP package
Applications
• Desktop computer AC/DC adaptor
• Laptop computer AC/DC adaptor
•TV AC/DC power supply
•AC/DC brick converters
FIGURE 1. TYPICAL APPLICATION FIGURE 2. PFC EFFICIENCY
+
ISL6730
VCC
ISEN
ICOMP
VIN
GATE
GND
FB
BO VREG
COMP
VLINE VOUT
VI
OUTPUT POWER (W)
EFFICIENCY (%)
ISL6730C
ISL6730A, SKIP
100
95
60
65
70
90
85
80
75
0 20 40 60 80 100
TABLE 1. KEY DIFFERENCES IN FAMILY OF ISL6730
VERSION ISL6730A ISL6730B ISL6730C ISL6730D
Switching Frequency 124kHz 62kHz 124kHz 62kHz
Skip Mode Yes-Fixed Yes-Fixed No No
August 8, 2013
FN8258.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas LLC 2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL6730A, ISL6730B, ISL6730C, ISL6730D
2FN8258.1
August 8, 2013
Pin Configuration
ISL6730A, ISL6730B, ISL6730C, ISL6730D
(10 LD MSOP)
TOP VIEW
7
8
10
9
4
3
2
1
GND
ISEN
ICOMP
VIN
GATE
VREG
FB
VCC
65
BO COMP
Pin Descriptions
PIN # I/O SYMBOL DESCRIPTION
1 - GND Ground pin. All voltage levels refer to this pin.
2 I ISEN Current sense pin. The current through this pin is proportional to the inductor current.
3 I/O ICOMP Current error amplifier output pin.
4 I VIN Input voltage sense. This pin provides the reference voltage to shape inductor current. Connect this pin to a resistor divider from
the rectified input voltage. The resistor divider ratio is used to adjust the phase lag between input voltage and the input current.
The phase lag is required to compensate the phase lead generated by the EMI filter.
5 I/O BO This pin should be decoupled to GND with a minimum 0.1µF ceramic capacitor. The BO pin is a voltage follower, which will follow
the DC voltage of the VIN pin. The BO pin is internally tied to GND through a resistor RIS. The decoupling capacitor provides ripple
filtering. When the voltage at the BO pin (VBO) drops below brownout voltage threshold, the controller enters shutdown mode
and the gate drive is disabled. The BO pin will be disabled when the FB pin drops below the enabling threshold.
6 I/O COMP Output of the error amplifier. The voltage of the COMP pin sets the input power. During start-up, a small charge current will slowly
ramp up the voltage of the COMP pin.
7 I FB Voltage feed back pin. Connect this pin to a resistor divider from the output. The resistor divider sets the output voltage. When
the FB pin voltage exceeds 104% of the reference voltage, overvoltage-protection is triggered and gate drive is disabled. When
the FB pin is below 10%, the device is put into shutdown mode. There is an internal pull-down current source for open loop
protection.
8 - VREG Output of internal regulator. The voltage having a ±2% tolerance over line, load and operating temperature. Bypass to GND with
a 47nF low ESR capacitor. VREG can source up to 10mA. This pin is not recommended for usage other than bypass.
9 I VCC Power supply pin. The VCC pin should be decoupled to GND with a minimum 0.1µF ceramic capacitor.
10 O GATE Push-pull gate drive for the external MOSFET. Output voltage is clamped at 12.5V. This pin provides typically 2A sink and 1.5A
source capability.
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
TEMP.
RANGE (°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL6730AFUZ 6730A -40 to +125 10 Ld MSOP M10.118
ISL6730BFUZ 6730B -40 to +125 10 Ld MSOP M10.118
ISL6730CFUZ 6730C -40 to +125 10 Ld MSOP M10.118
ISL6730DFUZ 6730D -40 to +125 10 Ld MSOP M10.118
ISL6730AEVAL1Z Evaluation Board
ISL6730BEVAL1Z Evaluation Board
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page. For more information on MSL please see techbrief TB363.
ISL6730A, ISL6730B, ISL6730C, ISL6730D
3FN8258.1
August 8, 2013
Block Diagram
FB
COMP
GATE
PWM
VCC
CONTROL
LOGIC
VIN
ISEN
OSCILLATOR
COMP
GND
OTP
VCC
BO
IFB
RSEN
R
IS
ICOMP
I
REF
CEQ GEN.
CURRENT
MIRROR
OVER POWER
LIMIT
SOFT-START
ENABLE
2.5V
SKIP
20µA
SKIP
CLAMP
SKIP
2:1
0.25 VIN
×
BO2
----------------------------- C O M P B
Q1COUT
VOUT
L
COMP-1V
RCS
VCS RIS IISEN
×
2
-----------------------------------=
CF1
VLINE CF3
EMI CHOKE
UVLO
RFB1
RFB2
Lm
RIN2
CBO
RIN1
D
ICS IOC
2
-------------->
ICS
COMPB
DF1
DF2
CREG
LINEAR
REGULATOR
VREG
VI
Gmi
Gmv
CF2
ISL6730A, ISL6730B, ISL6730C, ISL6730D
4FN8258.1
August 8, 2013
Application Schematics
Typical 300W Application Schematic
0.22R28 0.22R27
R3
2M
R1
2M
D2
C3D04060
2 1
TP12
GATE1
1u
C9
-+
DB1
GBU808
L1
0u
R19
42.2k
C20
47n
C19 0.1
VCC
C17
1n
DNP
Q2
2N7002
DNP
1
32
10k
R20
DNP
C21 0.1
25k
R21
DNP
VCC
DC+
P6
P7
GND
VCC
C12
DNP
C26
DNP
F2 8A
C15
150n
3.3M
R6
S1M
D7
C2
100n
3.3M
R10
S1M
D8 3.3V
DZ1
Q1
SPP20N60C3
1
3 2
C5
2.2n
470k
R11
C14
470n
R17
0
C4
DNP
7.15k
R13
C3
470n
C6
2.2n
C16
1n
51k
R4
R2
2.2
L3
5mH
4 3
1 2
270u
C1
450V
12
62k
R18
C18
2.2u
0.22R5
3k
R9
C8
220n
C13
220p
470k
R8
VREG
TP7
DNP
VOUT
GND
FB
BO COMP
GATE
ICOMP
ISEN
VIN
C22
680n
PE
AC2
AC1
L2
1.5mH
D1
1N5406
TP2
TP1
TP3
TP4
TP5
390VUNIVERSAL INPUT
85~265Vac
TP9
U1
ISL6730B/D
FB 7
GATE 10
GND 1
ISEN
2ICOMP
3
VIN
4
BO
5
6COMP
REG 8
VCC 9
TP10
P1
P4
P5
DNP
1u
C7
P2
P3
P8DNP
P9
DNP
C11
330p C10
1nF
TP8
R14
8.2k
TP6
R26
49.9
ISL6730A, ISL6730B, ISL6730C, ISL6730D
5FN8258.1
August 8, 2013
Typical 85W Application Schematic
Application Schematics (Continued)
ISL6730A, ISL6730B, ISL6730C, ISL6730D
6FN8258.1
August 8, 2013
Absolute Maximum Ratings Thermal Information
VCC to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +28V
GATE to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +18V
VIN, BO, ISEN, FB and COMP to GND. . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6.3V
ESD Rating
Human Body Model (Tested per JESD22-A114) . . . . . . . . . . . . . . .2.5kV
Machine Model (Tested per JESD22-A115). . . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per JESD-C101E. . . . . . . . . . . . . . . . . 1kV
Latch Up (Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . . . . . 100mA
Recommended Operating Conditions
VCC to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V to + 20V
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)
MSOP Package (Notes 4, 5) . . . . . . . . . . . . 136.9 39.4
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
5. For θJC, the "case temp" location is taken at the package top center.
Electrical Specifications Operating Conditions: VCC = 15V, TA = +25°C. Boldface limits apply over the operating temperature range,
-40°C to +125°C.
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8) UNITS
VCC SUPPLY CURRENT
Start Up Current ISTART VFB = 1V, VCC < VCC(ON) 73 106 139 µA
Standby Current ISTDN VFB = GND, VCC > VCC(ON) 179 237 295 µA
Skip Mode Current ICCSKIP VFB = 2.5V, COMP = SKIP*0.25 +1V 580 690 800 µA
Operating Current (Note 6) ICC GATE is floating 3.0 3.7 4.2 mA
VCC UVLO
UVLO Rising Threshold VCC(ON) 91011V
UVLO Falling Threshold VCC(OFF) 6.7 7.5 8.3 V
UVLO Threshold Hysteresis VCC(HYS) -2.5- V
REGULATOR VOLTAGE VREG
Overall Accuracy VREG IREG = 0 to -10mA, VCC = 15V, Load Capacitor = 47nF 5.1 5.4 5.6 V
Current Limit 30 50 70 mA
PWM CONVERTERS
Maximum Duty Cycle fSW = 124kHz for ISL6730A/C and
fSW = 62kHz for ISL6730B/D
94.8 96.5 - %
OSCILLATOR
Free Running Frequency, ISL6730A/C TA = -40°C to +125°C, VIN = 0.6V 98 107 116 kHz
Free Running Frequency, ISL6730A/C TA = -40°C to +125°C, VIN = 2.5V 114 125 136 kHz
Free Running Frequency, ISL6730B/D TA = -40°C to +125°C, VIN = 0.6V 47 54 61 kHz
Free Running Frequency, ISL6730B/D TA = -40°C to +125°C, VIN = 2.5V 57 64 71 kHz
PWM Ramp Amplitude Vm1.33 1.46 1.59 V
GATE DRIVER
Gate Drive Pull-Down Resistance VCC = 15V, IGATE = 15mA - 2.33 4.46 Ω
Gate Drive Pull-Up Voltage Drop VCC = 9V, IGATE = 15mA 0.15 0.3 0.45 V
ISL6730A, ISL6730B, ISL6730C, ISL6730D
7FN8258.1
August 8, 2013
Gate Drive Max. Sourcing/Sinking
Current
-1.5- A
Rise Time CO = 2.2nF, VCC = 15V, Gate Voltage Rise Time from 10%
to 90% of VGC
-3462ns
Fall Time CO = 2.2nF, VCC = 15V, Gate Voltage Fall Time from 10%
to 90% of VGC
-3457ns
Gate Clamp Voltage VGC 10.5 12 13.5 V
VOLTAGE REFERENCE
Reference Voltage VREF 2.48 2.5 2.52 V
Feedback Pin Pull-Down Current IFB -65-nA
Rising Threshold to Enable Converter FB_EN 280 300 320 mV
Falling Threshold to Disable Converter FB_DIS 190 202 214 mV
Enable Hysteresis FB_Hys - 100 - mV
VOLTAGE ERROR AMPLIFIER
Error Amp Transconductance Gmv 50 77 104 µA/V
ISource/Sink -13-µA
COMP Offset Voltage VCOMP_OFF 0.95 1.01 1.07 V
COMP Soft-Start Enable Voltage VCOMP_EN 0.58 0.64 0.75 V
INPUT VOLTAGE SENSING
VIN Leakage Current -9-nA
MULTIPLIER GAIN
GMUL COMP = 2.5V, VIN = 1.0V, BO = 1.0V, ISEN = 50µA 0.196 0.25 0.296 V/V
CURRENT ERROR AMPLIFIER
Current DC Gain AiDC ΔIICOMP/ΔIISEN 1.6 1.9 2.2 A/A
Error Amp Transconductance Gmi IICOMP = ±20µA 205 268 331 µA/V
ICOMP Source/Sink Current (Note 7) -60-µA
Current Sensing Input Offset -3 2 7 mV
LIGHT LOAD EFFICIENCY ENHANCEMENT AND OVERPOWER PROTECTION
Skip Mode COMP Threshold VSCMT Applied for ISL6730A/B 1.32 1.36 1.4 V
COMP Upper Limit VCUL 3.53 3.85 4.17 V
COMP Valid Range VCUL-1V 2.5 2.83 3.16 V
FB Exit Threshold Voltage VFB_EXIT Fraction of the set point (VREF), IISEN = 0µA, Applied for
ISL6730A/B
87 88 89 %
ISEN Exit Threshold Current ISEN_EXIT VFB = 2.5V, Applied for ISL6730A/B -38 -29 -20 µA
BROWNOUT DETECTION
Brownout Rising Threshold VBO_R 478 494 510 mV
Brownout Falling Threshold VBO_F 387 401 415 mV
OVERVOLTAGE PROTECTION
Overvoltage Protection VOVP Fraction of the set point (VREF); ~1µs noise filter 102.9 104.1 105.3 %
Electrical Specifications Operating Conditions: VCC = 15V, TA = +25°C. Boldface limits apply over the operating temperature range,
-40°C to +125°C. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8) UNITS
ISL6730A, ISL6730B, ISL6730C, ISL6730D
8FN8258.1
August 8, 2013
OVERCURRENT PROTECTION
Overcurrent Threshold IOC -197 -177 -159 µA
THERMAL SHUTDOWN
Shutdown Temperature (Note 7) - 160 - °C
Thermal Shutdown Hysteresis (Note 7) -25-°C
NOTES:
6. This is the VCC current consumed when the device is active but not switching. Does not include gate drive current.
7. Limits should be considered typical and are not production tested.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Electrical Specifications Operating Conditions: VCC = 15V, TA = +25°C. Boldface limits apply over the operating temperature range,
-40°C to +125°C. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8) UNITS
Typical Performance Curves
FIGURE 3. FEEDBACK ACCURACY FIGURE 4. FSW vs TEMPERATURE, VCC = 15V
FIGURE 5. AIDC vs TEMPERATURE FIGURE 6. FSW vs VIN, TA = +25°C
TEMPERATURE (°C)
VFB NORMALIZED (%)
99.50
99.75
100.00
100.25
100.50
-40 -20 0 20 40 60 80 100 120 140
FSW NORMALIZED (%)
99.0
99.5
100.0
101.0
VIN = 0.6V
VIN = 2.5V
TEMPERATURE (°C)
-40 -20 0 20 40 60 80 100 120 140
100.5
TEMPERATURE (°C)
97
98
99
100
101
-40 -20 0 20 40 60 80 100 120 140
AIDC NORMALIZED (%)
75
80
85
90
95
100
105
FSW NORMALIZED (%)
VIN (V)
0 0.51.01.52.02.53.0
ISL6730A, ISL6730B, ISL6730C, ISL6730D
9FN8258.1
August 8, 2013
FIGURE 7. UVLO THRESHOLDS vs TEMPERATURE FIGURE 8. VCC SUPPLY CURRENT vs TEMPERATURE
FIGURE 9. GATE DRIVER ABILITY vs TEMPERATURE (LOAD = 2.2nF)
Typical Performance Curves (Continued)
98
99
100
101
102
-40 -20 0 20 40 60 80 100 120 140
UP
DOWN
HYSTERSIS
TEMPERATURE (°C)
UVLO THRESHOLD NORMALIZED (%)
THRESHOLD
THRESHOLD
98
99
100
101
102
-40 -20 0 20 40 60 80 100 120 140
ICC
TEMPERATURE (°C)
VCC CURRENT NORMALIZED (%)
(GATE FLOATING)
ISTART
TEMPERATURE (°C)
DRIVER TIME NORMALIZED (%)
96
98
100
102
104
106
108
110
112
-40 -20 0 20 40 60 80 100 120 140
RISE TIME
FALL TI ME
ISL6730A, ISL6730B, ISL6730C, ISL6730D
10 FN8258.1
August 8, 2013
Functional Description
VCC Undervoltage Lockout (UVLO)
The ISL6730A, ISL6730B, ISL6730C, ISL6730D start
automatically once the voltage at VCC exceeds the UVLO
threshold.
Shutdown
When the VFB pin is below 0.2V, the controller is disabled and
the PWM output driver is tri-stated. When disabled, the IC power
will be reduced. During shutdown, the COMP pin is discharged to
GND and the controller is disabled. The Over-Temperature
Protection (OTP) is still alive to prevent the controller from
starting up in a high temperature ambient condition.
In the event that the FB pin is disconnected from the feedback
resistors, the FB pin is pulled to ground by an internal current
source IFB. When the FB pin voltage drops below 0.2V, the gate
driver is disabled. The ISL6730A, ISL6730B, ISL6730C,
ISL6730D enters shutdown mode.
Soft-Start
The COMP pin is released once the soft-start operation begins. A
13µA current sources out to the RC network connected from the
COMP pin until the FB pin voltage reaches 90% of the reference
voltage.
Switching is inhibited when the COMP pin voltage is below 1V.
When the COMP pin reaches 1V, the current error amplifier and
the gate driver are activated and the converter starts switching.
During UVLO, Brownout and Shutdown, the COMP is pulled to the
ground.
Input Voltage Sensing
The VIN pin is needed to sense the rectified input voltage. The
sensed semi-sinusoidal waveform is needed to shape inductor
current, which helps achieves unity power factor. At the same
time, the voltage on the VIN pin is used to generate the negative
capacitive element at the input. This will cancel the input filter
capacitor, CF. Canceling the effect of CF will increase the
displacement power factor and alleviate the zero crossing
distortion, which is related to the distortion power factor.
The BO pin also utilizes the VIN resistor divider for voltage
sensing. Set the resistor divider ratio to satisfy the brownout
requirement.
First, calculate the resistor divider ratio, KBO.
Where VF is the forward voltage drop of the bridge rectifier and
the voltage drop of DF1; DF2.
Then, select the RIN2 based on the highest reasonable resistance
value. Then select the RIN1 based upon the desirable minimum
RMS value of the line voltage for the PFC operation.
Inductor Current Sensing
The current sensing of the converter has two purposes. One is to
force the inductor current to track the input semi-sinusoidal
waveform. The other purpose is for overcurrent protection. Refer to
Figure 11 for the current sensing scheme. The sensed current ICS
is in proportion to the inductor current, IL as described in
Equation 3.
where:
RCS is the current sensing resistor with low value in the return
path to the bridge rectifier.
RSEN is the current scaling resistor connected between ISEN to
the RCS.
FIGURE 10. INPUT VOLTAGE SENSING SCHEMATIC
BO
RIN1 CBO
VIN
CF2
VLINE CF3
EMI CHOKE
Lm
DF1
DF2
RIN2
KBO VBORMAX
VRMSmin 2VF
–
-------------------------------------------
=(EQ. 1)
RIN1 KBO
1K–BO
--------------------- RIN2
⋅=(EQ. 2)
ICS 1
2
---RCS
RSEN
----------------IL
⋅⋅=(EQ. 3)
ISL6730A, ISL6730B, ISL6730C, ISL6730D
11 FN8258.1
August 8, 2013
A high value RCS renders more accurate current sensing. It is
recommended to use the RCS to render 120mV peak voltage at
the maximum line voltage during full load condition.
Where η is the efficiency of the converter at the maximum line
input with full load.
Since the RCS sees the average input current, high value RCS
generates high power dissipation on the RCS. Use a reasonable
RCS according to the resistor power rating. The worst-case power
dissipation occurs at the input low line when input current is at
its maximum. Power dissipation by the resistor is:
where:
IRMSMAX is the maximum input RMS current at the minimum
input line voltage, VRMSmin.
Select the RSEN according to the peak current limit requirement.
The resistor is sized for an overload current 25% more than the
peak inductor peak current.
Negative Input Capacitor Generation (Patent
Pending)
The patent pending negative capacitor generation capability of
the ISL6730A, ISL6730B, ISL6730C, ISL6730D allows the
capacitor CF2 to be moved from before the bridge rectifier
(Figure 12) to after the bridge rectifier (Figure 13). Thus, a
smaller lower cost CF2 can be used. The change in topology
reduces the size of the EMI filter. Furthermore, CF1 can be
increased thus decreasing the size of LF (Figure 13).
For applications where the output power is above 500W, the
negative capacitance helps to improve the power factor
dramatically. Please refer to Table 2 for the recommended
filtering capacitor to be placed after the bridge rectifier, CF1.
Additional CF1 may be used to accommodate the use of small
boost inductor or to eliminate the differential mode filter inductor
as long as the equipment meets the power factor or goal.
The equivalent negative capacitor is a function of the input
voltage divider ratio, KBO, the current sensing gain and current
compensation error integration gain.
Adjusting the negative Ceq can be achieved by adjusting the
current compensation network.
Frequency Modulation
The ISL6730A, ISL6730B, ISL6730C, ISL6730D can further
reduce EMI filter size by lowering the differential noise power
density. The reduction is achieved by switching frequency
modulation.
The frequency varies with the VIN pin. The switching frequency
reaches the peak value when the VIN pin voltage is 2V as shown
in Figure 6. The peak value of ISL6730A/C is 124kHz, and the
ISL6730B/D is 62kHz.
Output Voltage Regulation
The output voltage is sensed through a resistor divider. The
middle point of the resistor divider is fed to the FB pin. The
resistor divider ratio sets the output voltage. The
transconductance error amplifier generates a current in
proportion to the difference between the FB pin and the 2.5V
internal reference. The PFC is stabilized by the compensation
network that is connected from the COMP pin to the ground.
The voltage of the COMP sets the input average power by
determining the amplitude of the current reference. To keep the
FIGURE 11. INDUCTOR CURRENT SENSING SCHEME
Q1 COUT
VOUT
L
CF1
VI
RCS
ISEN
RSEN
CURRENT
MIRROR
2:1
ICS 0.5 IOC
>
ICS
RCS 120mV VRMSMAX η⋅⋅
2P
Omax
⋅
-------------------------------------------------------------
>(EQ. 4)
PRCS IRMSMAX
()
2RCS
⋅=(EQ. 5)
FIGURE 12. TYPICAL PFC INPUT FILTER CIRCUIT
FIGURE 13. LOW COST PFC INPUT FILTER CIRCUIT
TABLE 2.
CF1 Po < 100W 100W < Po < 500W Po > 500W
Typical
C(µF)/100W
0.68 0.33 0.22
CF1
CF2
VLINE CF3
EMI CHOKE
Lm
BRIDGE RECTIFIER
LF
CF1
CF2
VLINE CF3
EMI CHOKE
Lm
BRIDGE RECTIFIER LF
ISL6730A, ISL6730B, ISL6730C, ISL6730D
12 FN8258.1
August 8, 2013
harmonic distortion minimum, it is desirable to set the control
bandwidth much lower than twice of the line frequency. The
recommended voltage loop bandwidth is 10Hz.
During start-up, the compensation capacitors and the charging
current from the error amplifier sets the input power increase
rate. Thus, soft-start is achieved.
The COMP is discharged during shutdown and fault conditions.
Light Load Efficiency Enhancement
For PC, adaptor and TV applications, it is desirable to achieve
high efficiency at light load conditions and low standby current.
The ISL6730A, ISL6730B can enter light load efficiency mode
automatically.
The voltage error amplifier output, COMP, is an indicator of the
average input power level. The controller compares the V(COMP)
and V(SKIP). If V(COMP)-1V is less than V(SKIP)*0.25, the PFC
controller stops gate switching and the COMP pin voltage is
clamped to V(SKIP)+0.6V. ISL6730A/B use a fixed V(SKIP), which
is 1.4V; for ISL6730C/D, the SKIP function are disabled.
The controller exits skip mode when VFB drops to 88% (typical) of
the reference voltage or when the sensed returned current
exceeds 29µA.
Protection Circuits
Input Brownout, BO Protection
Brownout occurs when there is a drop in the line voltage. The BO
pin is a dual function pin. The BO pin detects the brownout
condition and shuts down the gate driver and controller. During
normal operation, the BO pin is used to compensate the effect of
the input line voltage change on the voltage loop. To keep the
harmonic distortion low, the corner frequency formed by the RBO
and CBO should be lower than 6Hz.
The BO pin is the output of the average voltage of the rectified
voltage. The PFC controller is turned off when the BO pin drops
below 0.4V. This protects the PFC power stage to enable
operation at or below brownout condition for long periods of
time. The controller resumes operation when the BO pin returns
to 0.5V.
The BO pin is usually connected to GND through a capacitor, CBO.
To avoid distortion on the VIN pin, select CBO so that:
Overcurrent Protection
The peak current limiting function prevents the inductor from
saturation. The gate driver turns off when the current goes above
the current limit.
Overpower Protection
The overpower protection is implemented by limiting the COMP
pin voltage higher than 3.85V (typical).
Overvoltage Protection
If the voltage on the FB pin exceeds the reference voltage by about
4%, the gate driver is turned off. The controller resumes normal
operation after the FB pin drops below reference voltage.
Over-Temperature Protection
The ISL6730A, ISL6730B, ISL6730C, ISL6730D is protected
against over-temperature conditions. When the junction
temperature exceeds +160°C, the PWM shuts down. Normal
operation is resumed when the junction temperature decreases
below +135°C.
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using wide,
short printed circuit traces. The critical components should be
located as close together as possible using ground plane
construction or single point grounding.
Figure 14 shows the critical power components; Q1, D and COUT.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of the ground or the
power plane in a printed circuit board. The components shown in
Figure 14 should be located as close together as possible. Please
note that the capacitors CVCC and CO each represent numerous
physical capacitors. Locate the ISL6730A, ISL6730B, ISL6730C,
ISL6730D within 2 inches of the MOSFET, Q1. The circuit traces
for the MOSFETs’ gate and source connections from the
ISL6730A, ISL6730B, ISL6730C, ISL6730D must be sized to
handle up to 1.5A peak current.
Component Selection Guidelines
A 300W, universal input, PFC converter design is provided for
demonstration. The design method is for a continuous current
mode power factor correction boost converter with the
ISL6730B/D. The switching frequency is 62kHz.
CBO 0.22μF»(EQ. 6)
FIGURE 14. CRITICAL CURRENT POWER COMPONENTS
Q1COUT
L
D
GATE
VCC
CVCC
ISL6730A, ISL6730B, ISL6730C, ISL6730D
13 FN8258.1
August 8, 2013
Table 3 shows the design parameters.
BOOST INDUCTOR SELECTION
First, calculate the maximum input RMS current, IINMAX.
Where η is the converter efficiency at VRMSmin. PF is the power
factor at VRMSmin.
Assuming the current is sinusoidal and the peak to peak ripple at
line is 40%.
The boost inductor, LBST, is given by the following equation:
The peak current of the inductor is the sum of the average peak
inductor current and half of the peak to peak ripple current.
Select and design the boost inductor as given by Equation 11.
The ISL6730A, ISL6730B, ISL6730C, ISL6730D provides peak
current limit function that can prevent the boost inductor
saturation. Assuming 25% margin is given to the OCP threshold,
select and design the boost inductor with saturation current
given by Equation 11 with 25% more.
INPUT RECTIFIER
The maximum average input current is calculated:
Select the bridge diode using Equation 15 and sufficient reverse
breakdown voltage. Assuming the forward voltage, VF,BR, is 1V
across each rectifier diode. The power loss of the rectifier bridge
can be calculated:
INPUT CAPACITOR SELECTION
Refer to Table 2 for the recommended input filter capacitor value.
This is the recommended capacitor used after the diode bridge.
For better power factor, less capacitance can be used. To lower
the input filter inductor size, more capacitance can be used.
Two 0.47µF capacitors in parallel are used for CF1.
BOOST DIODE SELECTION
The boost diode loss is determined by the diode forward voltage
drop, VF and the output average current. The maximum output
current is:
The forward power loss on the diode is:
The IDD03E60 part is selected.
The reverse recovery loss on the diode can be calculated. The
QRR is found from the diode datasheet. QRR = 220nC when
IF=3.5A.
The reverse recover loss on the diode can be estimated:
The total power loss on the diode is:
MOSFET POWER DISSIPATION
The power dissipation on the MOSFET is from two different types
of losses; the condition loss and the switching loss.
For the MOSFET, the worst case is at minimum line input voltage.
First, the drain to source RMS current is calculated:
TABLE 3. CONVERTER DESIGN PARAMETERS
PARAMETER CONDITIONS MIN TYP MAX UNIT
VLINE 85 115 265 VAC
FLINE 47 63 Hz
POMAX Maximum Output Power 300 W
THOLD Hold Up Time 20 ms
Efficiency VLINE = 115VAC 92 %
IINMAX POMAX
ηV•RMSmin
-----------------------------------
=(EQ. 7
IINMAX 300W
0.92 85V•
---------------------------- 3.84A== (EQ. 8)
LBST 2VRMSmin
0.4 Fsw 2•• IINMAX
•
----------------------------------------------------------------12V
RMSmin
•
VOUT
---------------------------------------
–
⎝⎠
⎜⎟
⎛⎞
•≥ (EQ. 9)
LBST 85V
0.4 62kHz 3.84•A•
------------------------------------------------------1285V•
390V
------------------------
–
⎝⎠
⎛⎞
•≥ 617μH=(EQ. 10)
ILPeak 2I•INMAX 10.4
2
--------
+
⎝⎠
⎛⎞
•=(EQ. 11)
ILPeak 23.88A•10.4
2
--------
+
⎝⎠
⎛⎞
•6.5A== (EQ. 12)
IINAVE max()
22•IINMAX
•
π
------------------------------------------
=(EQ. 13)
IINAVE max()
22•3.88A•
π
-------------------------------------- 3.5A== (EQ. 14)
PBR 2V
FBR,
•IINAVE MAX()
•=(EQ. 15)
PBR 21V•3.5A•7W== (EQ. 16)
CF1 300W 0.33
100
-----------
•0.99μF== (EQ. 17)
IOUT max()
POMAX
VOUT
--------------------
=(EQ. 18)
IOUT max()
300W
390V
----------------0.77A== (EQ. 19)
PFD IOUT max()
VF
•=(EQ. 20)
PFD 0.77A 1.85V•1.42W== (EQ. 21)
PRRD 1
4
---Q•RR VOUT
•F•sw
=(EQ. 22)
PRRD 1
4
---220nC•390V•62kHz•1.33W==
(EQ. 23)
PDPFD PRRD
+1.42 1.35+()W2.75W== = (EQ. 24)
IDS max()
IINMAX 182
3π
-----------VRMSmin
VOUT
--------------------------
•–= (EQ. 25)
IDS max()
3.88A 1 82
3π
-----------85V
390V
--------------
•–3.3A==
(EQ. 26)
ISL6730A, ISL6730B, ISL6730C, ISL6730D
14 FN8258.1
August 8, 2013
The MOSFET, SPP20N60C3 is selected.
The switching loss of the MOSFET consists of three parts: the
turn-on loss, the turn-off loss and the diode reverse recovery loss.
From the MOSFET datasheet, the typical switching losses curves
are provided.
When RG = 3.6Ω, ID = 6A, EON = 0.015mJ, EOFF = 0.007mJ.
The switching loss due to transition is calculated:
The diode reverse recovery incurs additional power loss on the
MOSFET. This loss can be estimated as:
This loss is also related the di/dt during the MOSFET turn-on. The
di/dt can be found out from the MOSFET datasheet. At
RG = 3.6Ω, the turn-on di/dt is 4000A/µs. From the Typical
Reverse Recovery Charge curve at TJ = +125°C, the
QRR = 220nC when IF = 3.5A.
THE TOTAL LOSS ON THE MOSFET
OUTPUT CAPACITOR SELECTION
The output capacitor, COUT, is required to hold the output above
300V during one line cycle. For capacitors with 20% tolerance,
the tolerance should be taken into consideration. Thus, the
output capacitance should be greater than:
Calculate the ripple RMS current through the capacitor:
Select the proper capacitor according to the hold time and ripple
RMS current requirement. The actual capacitance is 270µF.
It is important to make sure the output peak-to-peak ripple is
less than the minimum OVP threshold as specified in the
“Electrical Specifications” table on page 6. The ESR at 2 times of
the line frequency of the capacitor is found in the capacitor
datasheet. The ESR of the output capacitor is 770mΩ at 100Hz.
The minimum OVP threshold is 103% of the nominal output
value. The maximum output peak to peak ripple should be less
than 6% of the nominal value, which is 23.4VP-P.
CURRENT SENSING RESISTORS
Please refer to Equation 4 for calculation of the current sensing
resistor RCS.
While a large RCS renders better current sensing accuracy, larger
RCS also incurs higher power dissipation. Select RCS from
available standard value resistors to determine the sense
resistor.
The maximum power dissipation on the RCS occurs at low line
and full load condition. The maximum power dissipation is
calculated:
The resistor, RSEN sets the overcurrent protection limit. From
Equation 3, RSEN should be greater than:
Where |x| stands for the ABS(x) function.
Select RSEN from available standard value resistors, the selected
RSEN is 3.16kΩ.
CURRENT LOOP COMPENSATION
The input current shaping is achieved by comparing the sensed
current signal to the sensed input voltage signal. The current
error amplifier (Gmi), together with the current compensation
network, adjusts the duty cycle so that the inductor current
traces the sensed rectified voltage. Thus, unity power factor is
achieved.
The compensation network consists of the Trans-Conductance
error amplifier (Gmi) and the impedance network (ZICOMP). The
goal of the compensation network is to provide a closed loop
transfer function with the sufficient 0dB crossing frequency
(f0dB) and adequate phase margin. Phase margin is the
difference between the open loop phase at f0dB and 180°. The
following equations relate the compensation network’s poles,
zeros and gain to the components (Ric, Cic and Cip) in Figure 15.
PCOND IDS max()
2RDS on()
•=(EQ. 27)
PCOND 3.3A20.3Ω• 3.27W== (EQ. 28)
PSW EON EOFF
+()F•sw
=(EQ. 29)
PSW 0.015mJ 0.007mJ+()62kHz•1.36W==
(EQ. 30)
PRR QRR VOUT
•F•sw
=(EQ. 31)
PRR 220nC 390V 62•kHz•5.32W== (EQ. 32)
PCOND PSW P+RR
+3.27W 1.36W 5.32W++ 9.95W==
(EQ. 33)
COUT 2T
HOLD P⋅⋅
OMAX
VOUT
2VHOLD
2
–
---------------------------------------------------- 1
10.2–
-----------------
⋅≥ (EQ. 34)
COUT 2 20ms 300W⋅⋅
390()
2300V()
2
–
---------------------------------------------- 1.25 242μF=⋅≥ (EQ. 35)
ICORMS max()
IOUT max()
82
3π
-----------VOUT
VRMSmin
--------------------------
•1–= (EQ. 36)
ICORMS max()
0.77A 82
3π
-----------390V
85V
--------------
•1–1.635A==
(EQ. 37)
VOpp IOUT max()
4πfline COUT ESR⋅⋅()
21+
4πfline
()COUT 0.8⋅⋅
-------------------------------------------------------------------------------
⋅=(EQ. 38)
VOpp 0.77A 4π50Hz 270μF0.77Ω⋅⋅ ⋅()
21+
4π50Hz⋅()270μF0.8⋅⋅
--------------------------------------------------------------------------------------------
⋅6.6V==
(EQ. 39)
RCS 120mV 265V 0.92⋅⋅
2300W⋅
-------------------------------------------------------
≥0.069Ω=(EQ. 40)
RCS 0.068Ω=(EQ. 41)
PRCSMAX IINMAX2R•CS
=(EQ. 42)
PRCSMAX 3.88A20.068Ω• 1.023W== (EQ. 43)
RSEN RCS ILPeak 10.25+()••
20.5I
OC
•
--------------------------------------------------------------------
≥(EQ. 44)
RSEN 0.068Ω6.6A 1.25••
290μA•
--------------------------------------------------------
≥3.117kΩ=(EQ. 45)
ISL6730A, ISL6730B, ISL6730C, ISL6730D
15 FN8258.1
August 8, 2013
Use the following guidelines for locating the poles and zeros of
the compensation network.
The cross over frequency of the current loop should be set
between 2kHz to 100kHz. At cross over frequency, the transfer
function from duty cycle to inductor current is well approximated
by Equation 48:
It is recommended to set the cross over frequency from 1/10 to
1/6 of the switching frequency with phase margin of 60°. A high
frequency pole is set at 1/2 of the switching frequency for ripple
filtering. In this example, we set the cross over, FC at 1/6 of the
switching frequency.
Where FC = FS/6 = 10.3kHz, ΦM is the phase margin, which is
60°. FP = FS/2 = 31kHz.
Thus, the current loop compensation zero is:
The total compensation capacitance is calculated:
The value of the noise filtering capacitor is:
The value of Cic is:
The value of Ric is:
Select the RC value from the standard value, we have:
Ric = 4.02kΩ, Cic = 18nF, Cip = 1.2nF. Figure 17 shows the actual
bode plot of current loop gain.
FIGURE 15. INDUCTOR CURRENT SENSING SCHEME
Q1COUT
VOUT
L
CF1
RCS
ISEN
RSEN
CURRENT
MIRROR
2:1 ICS
ICOMP
IREF
Gmi
Ric
Cic
RIS
Cip
VI
80
40
20
0
-20
-40
-60
-80
-100
FP
100k10k1k100
FROM DUTY TO
FZ
COMPENSATION
GAIN (dB)
FREQUENCY (Hz)
GAIN
MODULATOR GAIN
CURRENT GAIN
OPEN LOOP
GAIN
FIGURE 16. ASYMPTOTIC BODE PLOT OF CURRENT LOOP GAIN
INDUCTOR CURRENT
FZ1
2πRic C•ic
•
------------------------------------
=(EQ. 46)
FP1
2πRic Cip C•ic
Cip Cic
+
------------------------
••
---------------------------------------------------
=(EQ. 47)
Gid s() VOUT
LBST s⋅
----------------------
=(EQ. 48)
FZFC
FC
FP
-------
⎝⎠
⎜⎟
⎛⎞
atan ΦM
+
⎝⎠
⎜⎟
⎛⎞
tan
--------------------------------------------------------
=(EQ. 49)
FZ62KHz()6⁄
2
6
---
⎝⎠
⎛⎞
atan 60deg+
⎝⎠
⎛⎞
tan
-------------------------------------------------------------
=2.12kHz=(EQ. 50)
Cip Cic VOUT
LBST 2πfc
()
2
⋅
---------------------------------------AiDC
Vm
------------- RCS
RSEN
----------------
⋅⋅
⎝⎠
⎜⎟
⎛⎞
1f
cfz
⁄()
2
+
1f
cfp
⁄()
2
+
-------------------------------⋅
⎝⎠
⎜⎟
⎜⎟
⎛⎞
=+ (EQ. 51)
Cip Cic 19.8()nF=+ (EQ. 52)
Cip Cip CiC
+()
fz
fp
----
=(EQ. 53)
Cip 14.9nF 2.12kHz
31kHz
-----------------------
⋅1.35nF== (EQ. 54)
Cic 19.8nF 1.35nF–18.4nF== (EQ. 55)
Ric 1
2π2.12kHz 18.4nF⋅⋅
-----------------------------------------------------------4.11kΩ== (EQ. 56)
ISL6730A, ISL6730B, ISL6730C, ISL6730D
16 FN8258.1
August 8, 2013
INPUT VOLTAGE SETTING
First, set the BO resistor divider gain, KBO according to
Equations 1 and 2.
Assuming the converter starts at VLINE = 80VRMS, then the BO
resistor divider gain, KBO should be:
In this design, two 3.3MΩ resistors in series are used for RIN2.
So, RIN1 is calculated:
Using resistor from the standard value, RIN1 = 43kΩ, the actual
KBO is calculated:
NEGATIVE INPUT CAPACITOR GENERATION
The ISL6730A, ISL6730B, ISL6730C, ISL6730D generates an
equivalent negative capacitance at the input to cancel the input
filter capacitance. Thus, more input capacitors can be used
without reducing the power factor.
The input equivalent negative capacitance is a function of the
current sensing gain, BO resistor divider gain and the
compensation components.
This equivalent negative capacitor cancels the input filter
capacitor required for EMI filtering. Therefore, the displacement
power factor significantly improves.
For example, CF2 = 0.68µF, CF1 = 0.94µF, using the low cost EMI
filter shown in Figure 13. When VLINE = 230VAC, fLINE = 50Hz,
PO= 60W.
Assuming 95% efficiency under the above test condition, the
resistive component, which is in phase to voltage:
The reactive current through the input capacitors:
Thus, the displacement power factor is:
The reactive current generated by the equivalent negative
capacitor is:
With the equivalent negative capacitor, the total reactive current
reduces to:
The displacement power factor increases to:
VOLTAGE LOOP COMPENSATION
The average diode forward current can be approximated by:
Assuming the input current traces the input voltage perfectly. The
input power is in proportion to (VCOMP - 1V).
Where ΔCOMP is the VCOMP - 1V. 1V is the offset voltage.
RIS is the internal current scaling resistor. RIS = 14.2kΩ.
FIGURE 17. BODE PLOT OF THE ACTUAL CURRENT LOOP GAIN
-20
0
20
40
60
80
GAIN (dB)
10 100 1x103
0
45
90
135
180
FREQUENCY (Hz)
PHASE (°)
45
60
10.5kHz
1x1031x103
10.5kHz
KBO 0.5V
80V 2V–
------------------------ 0.00641== (EQ. 57)
RIN1 0.00641
1 0.00641–
-------------------------------6.6MΩ()⋅42.6kΩ== (EQ. 58)
KBO RIN1
RIN1 RIN2
+
---------------------------------0.00647== (EQ. 59)
CNEG KBO 0.8 Vm
VOUT
----------------
–⋅
⎝⎠
⎜⎟
⎛⎞
RSEN
RCSAiDC
--------------------------Cic Cip
+()=(EQ. 60)
CNEG 0.00647 0.8 1.5
390
----------
–⋅
⎝⎠
⎛⎞
3.16k
0.068 1.9⋅
--------------------------- 18nF 1.2nF+()=0.62μF=
(EQ. 61)
IaPo
VLINE 0.95⋅
---------------------------------
=0.275A=(EQ. 62)
IcVLINE 2πfLINE
⋅()•CF1 CF2
+()•=0.117A=(EQ. 63)
PFDIS Ia
Ia
()
2Ic
()
2
+
-----------------------------------
=0.92=(EQ. 64)
Icneg VLINE 2πfLINE
⋅()•CNEG
()•=0.045A=(EQ. 65)
IcIcneg
–0.072A=(EQ. 66)
PFDIS Ia
Ia
()
2IcIcneg
–()
2
+
--------------------------------------------------------
=0.967=(EQ. 67)
IDave()
Pin
VOUT
----------------
=(EQ. 68)
IDave()
RSEN
RCS 0.5 R⋅IS
⋅
--------------------------------------- 1
VOUT
----------------
•0.25
22()π⁄()
2KBO
⋅
------------------------------------------------
⎝⎠
⎜⎟
⎜⎟
⎛⎞
ΔCOMP
••=
(EQ. 69)
IDave()
0.598A
V
----ΔCOMP
•=(EQ. 70)
ISL6730A, ISL6730B, ISL6730C, ISL6730D
17 FN8258.1
August 8, 2013
Thus, the transfer function from VCOMP to VOUT is:
As shown in Figure 18, the voltage loop gain is:
The output feedback resistor divider gain, GDIV is:
The compensation gain uses external impedance networks as
shown in Figure 18, ZCOMP(s) is given by:
The targeted cross over frequency, FCV is 8Hz. The high frequency
pole, FPv is required in order to reject the 2 time line frequency
component. FPv = 20Hz. The targeted phase margin is 60°.
The zero, FZv is calculated:
Then the total capacitance used for compensation is calculated:
Thus, the total compensation capacitance is:
Choose components from the standard values. We have
CVP = 100nF, CVC = 1500nF, RVC = 82.5kΩ. The actual bode plot
is shown in Figure 20.
FB
COMP
Gmv
IFB
2.5V
RFB1
RFB2
VOUT
FIGURE 18. OUTPUT VOLTAGE SENSING AND COMPENSATION
Rvc
Cvc Cvp
GPS s() VOUT s()
ΔCOMP
------------------------
=1
COs⋅
----------------IDave()
ΔCOMP
--------------------
⋅=(EQ. 71)
GPS s() IDave()
COs⋅
------------------- 1
ΔCOMP
--------------------
⋅
⎝⎠
⎜⎟
⎛⎞
=0.598
COs⋅
----------------
=(EQ. 72)
GVLOOP s() GPS s() GDIV gmv ZCOMP
••• s()=(EQ. 73)
GDIV VREF
VOUT
----------------
=(EQ. 74)
ZCOMP s() 1
Cvc Cvp
+()s⋅
---------------------------------------Rvc Cvc s1+••
Rvc Cvc
•Cvp
•
Cvc Cvp
+
------------------------------------------s•1+
-------------------------------------------------------------
•=(EQ. 75)
100
80
60
40
20
0
-20
-40
-60
FPv
1k100101
FZv
GAIN (dB)
FREQUENCY (Hz)
FIGURE 19. ASYMPTOTIC BODE PLOT OF CURRENT LOOP GAIN
FCV
GPS(s)
Gmv*ZCOMP(s)
GVLOOP(s)
GDIV
FZv FCV
ΦmFCV FPv
()⁄()atan+()tan
------------------------------------------------------------------------------
=(EQ. 76)
FZv 8Hz
60deg 8Hz()20Hz()⁄()atan+()tan
------------------------------------------------------------------------------------------------ 1.15Hz==
(EQ. 77)
Cvc Cvp
+GPS i2πFCV
()•()GDIV Gmv••
2πFCV
()
-------------------------------------------------------------------------------------------FCV FZV
⁄()
21+
FCV FPV
⁄()
21+
--------------------------------------------•=
(EQ. 78)
Cvc Cvp
+1829nF=(EQ. 79)
Cvp 1829nF FZV
FPV
-----------
•105nF== (EQ. 80)
Cvc 1829nF 105nF–1724nF== (EQ. 81)
Rvc 1
2πFZV CVC
⋅⋅ ⋅
-------------------------------------------81.2kΩ== (EQ. 82)
FIGURE 20. BODE PLOT OF THE ACTUAL VOLTAGE LOOP GAIN
-40
-20
0
20
40
60
GAIN (dB)
0
110 100 1x103
0
15
30
45
60
75
90
FREQUENCY (Hz)
PHASE (deg)
ISL6730A, ISL6730B, ISL6730C, ISL6730D
18
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8258.1
August 8, 2013
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE REVISION CHANGE
August 8, 2013 FN8258.1 Added electronic specifications to parts ISL6730B/D and made necessary changes throughout document.
February 26, 2013 FN8258.0 Initial Release.
ISL6730A, ISL6730B, ISL6730C, ISL6730D
19 FN8258.1
August 8, 2013
Package Outline Drawing
M10.118
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 4/12
DETAIL "X"
SIDE VIEW 2
TYPICAL RECOMMENDED LAND PATTERN
TOP VIEW
PIN# 1 ID
0.18 - 0.27
DETAIL "X"
0.10 ± 0.05
(4.40)
(3.00)
(5.80)
H
C
1.10 MAX
0.09 - 0.20
3°±3°
GAUGE
PLANE 0.25
0.95 REF
0.55 ± 0.15
B
0.08 C A-B D
3.0±0.05
12
10
0.85±010
SEATING PLANE
A
0.50 BSC
3.0±0.05 4.9±0.15
(0.29)
(1.40)
(0.50)
D
5
5
SIDE VIEW 1
Dimensioning and tolerancing conform to JEDEC MO-187-BA
Plastic interlead protrusions of 0.15mm max per side are not
Dimensions in ( ) are for reference only.
Dimensions are measured at Datum Plane "H".
Plastic or metal protrusions of 0.15mm max per side are not
Dimensions are in millimeters.
3.
4.
5.
6.
NOTES:
1.
2. and AMSEY14.5m-1994.
included.
included.
0.10C
M
Mouser Electronics
Authorized Distributor
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