INTEGRATED CIRCUITS 74ABT16821A 74ABTH16821A 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) Product data Supersedes data of 1998 Feb 27 2002 Dec 13 Philips Semiconductors Product data 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ABT16821A 74ABTH16821A FEATURES DESCRIPTION * 20-bit positive-edge triggered register * Multiple VCC and GND pins minimize switching noise * Live insertion/extraction permitted * Power-up reset * Power-up 3-State * 74ABTH16821A incorporates bus-hold data inputs which The 74ABT16821A high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive. The 74ABT16821A has two 10-bit, edge triggered registers, with each register coupled to a 3-State output buffer. The two sections of each register are controlled independently by the clock (nCP) and Output Enable (nOE) control gates. Each register is fully edge triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop's Q output. eliminate the need for external pull-up resistors to hold unused inputs * Output capability: +64 mA / -32 mA * Latch-up protection exceeds 500mA per JEDEC Std 17 * ESD protection exceeds 2000V per MIL STD 883 Method 3015 The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-LOW Output Enable (nOE) controls all ten 3-State buffers independent of the register operation. When nOE is LOW, the data in the register appears at the outputs. When nOE is HIGH, the outputs are in high impedance "off" state, which means they will neither drive nor load the bus. and 200V per Machine Model Two options are available, 74ABT16821A which does not have the bus-hold feature and 74ABTH16821A which incorporates the bus-hold feature. QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS Tamb = 25 C; GND = 0 V TYPICAL UNIT tPLH tPHL Propagation delay nCP to nQx CL = 50 pF; VCC = 5 V 2.4 2.0 ns CIN Input capacitance VI = 0 V or VCC 3 pF VO = 0 V or VCC; 3-State 7 pF Outputs disabled; VCC = 5.5 V 500 A Outputs LOW; VCC = 5.5 V 10 mA COUT Output capacitance ICCZ Quiescent supply current ICCL ORDERING INFORMATION PACKAGES TEMPERATURE RANGE PART NUMBER DWG NUMBER 56-Pin Plastic SSOP Type III -40 C to +85 C 74ABT16821ADL SOT371-1 56-Pin Plastic TSSOP Type II -40 C to +85 C 74ABT16821ADGG SOT364-1 56-Pin Plastic TSSOP Type II -40 C to +85 C 74ABTH16821ADGG SOT364-1 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 55, 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31, 30 1D0 - 1D9 2D0 - 2D9 Data inputs 2, 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26, 27 1Q0 - 1Q9 2Q0 - 2Q9 Data outputs 1, 28 1OE, 2OE Output enable inputs (active-LOW) Clock pulse inputs (active rising edge) 56, 29 1CP, 2CP 4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0 V) 7, 22, 35, 50 VCC Positive supply voltage 2002 Dec 13 2 Philips Semiconductors Product data 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ABT16821A 74ABTH16821A PIN CONFIGURATION 1OE LOGIC SYMBOL (IEEE/IEC) 1 56 1CP 1OE 1 EN2 1Q0 2 55 1D0 1CP 56 1Q1 3 54 1D1 2OE 28 GND 4 53 GND 2CP 29 1Q2 5 52 1D2 1D0 55 2 1Q0 1Q3 6 51 1D3 1D1 54 3 1Q1 VCC 7 50 VCC 1D2 52 5 1Q2 1Q4 8 49 1D4 1D3 51 6 1Q3 1Q5 9 48 1D5 1D4 49 8 1Q4 1Q6 10 47 1D6 1D5 48 9 1Q5 GND 11 46 GND 1D6 47 10 1Q6 1Q7 12 45 1D7 1D7 45 12 1Q7 1Q8 13 44 1D8 1D8 44 13 1Q8 1Q9 14 43 1D9 1D9 43 14 1Q9 2Q0 15 42 2D0 2D0 42 15 2Q0 2Q1 16 41 2D1 2D1 41 16 2Q1 2Q2 17 40 2D2 2D2 40 17 2Q2 GND 18 39 GND 2D3 38 19 2Q3 2Q3 19 38 2D3 2D4 37 20 2Q4 2Q4 20 37 2D4 2D5 36 21 2Q5 2Q5 21 36 2D5 2D6 34 23 2Q6 VCC 22 35 VCC 2D7 33 24 2Q7 2Q6 23 34 2D6 2D8 31 26 2Q8 2Q7 24 33 2D7 2D9 30 27 2Q9 GND 25 32 GND 2Q8 26 31 2D8 2Q9 27 30 2D9 2OE 28 29 2CP C1 EN4 C3 1D 3D FUNCTION TABLE INPUTS LOGIC SYMBOL 54 52 51 49 48 47 1D0 1D1 1D2 1D3 1D4 1D5 1D6 56 1CP 1 1OE 45 44 43 1D7 1D8 1D9 2 3 5 6 8 9 10 12 13 14 42 41 40 38 37 36 34 33 31 30 29 2CP 28 2OE 2D7 2D8 2D9 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9 15 16 17 19 20 21 23 24 26 27 SH00002 2002 Dec 13 OUTPUTS nOE nCP nDx INTERNAL REGISTER nQ0 - nQ9 OPERATING MODE L L l h L H L H Load and read register L X NC NC Hold H X NC Z Disable H Dn Dn Z outputs H = High voltage level h = High voltage level one set-up time prior to the LOW-to-HIGH clock transition L = Low voltage level l = Low voltage level one set-up time prior to the LOW-to-HIGH clock transition NC= No change X = Don't care Z = High impedance "off" state = LOW-to-HIGH clock transition = Not a LOW-to-HIGH clock transition 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 2D0 2D1 2D2 2D3 2D4 2D5 2D6 4 SH00003 SH00001 55 2 3 Philips Semiconductors Product data 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ABT16821A 74ABTH16821A LOGIC DIAGRAM nD0 nD1 nD2 nD3 nD4 nD5 nD6 nD7 nD8 nD9 D D D D D D D D D D CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q CP Q nCP nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 nQ9 SH00004 ABSOLUTE MAXIMUM RATINGS1, 2 SYMBOL VCC PARAMETER IIK DC input diode current VI DC input voltage3 IOK DC output diode current VOUT CONDITIONS DC supply voltage VI < 0 V DC output voltage3 IOUT DC output out ut current Tstg Storage temperature range RATING UNIT -0.5 to +7.0 V -18 mA -1.2 to +7.0 V VO < 0 V -50 mA Output in Off or HIGH state -0.5 to +5.5 V Output in LOW state 128 Output in HIGH state -64 mA -65 to 150 C NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS MIN VCC DC supply voltage VI Input voltage VIH High-level input voltage UNIT MAX 4.5 5.5 V 0 VCC V 2.0 V VIL Low-level Input voltage 0.8 V IOH High-level output current -32 mA IOL Low-level output current 64 mA 0 10 ns/V -40 +85 C t/v Input transition rise or fall rate Tamb Operating free-air temperature range 2002 Dec 13 4 Philips Semiconductors Product data 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ABT16821A 74ABTH16821A DC ELECTRICAL CHARACTERISTICS LIMITS SYMBOL PARAMETER Min VIK Input clamp voltage VOH HIGH-level output voltage VOL LOW-level output voltage VCC = 4.5 V; IOL = 64 mA; VI = VIL or VIH VRST voltage3 Power-up output II Input leakage current II Input leakage current 74ABTH16821A Tamb = -40 C to +85 C Tamb = +25 C TEST CONDITIONS VCC = 4.5 V; IIK = -18 mA Typ Max -0.9 -1.2 Min UNIT Max -1.2 V VCC = 4.5 V; IOH = -3 mA; VI = VIL or VIH 2.5 2.9 2.5 V VCC = 5.0 V; IOH = -3 mA; VI = VIL or VIH 3.0 3.4 3.0 V VCC = 4.5 V; IOH = -32 mA; VI = VIL or VIH 2.0 2.4 2.0 V 0.36 0.55 0.55 VCC = 5.5 V; IO = 1 mA; VI = GND or VCC 0.13 0.55 0.55 V VCC = 5.5 V; VI = VCC or GND 0.01 1.0 1.0 A 0.01 1 1 A VCC = 5.5 V; VI = VCC or GND VCC = 5.5 V; VI = VCC Control pins Data pins VCC = 5.5 V; VI = 0 V 0.01 1 1 A -1 -3 -5 A VCC = 4.5 V; VI = 0.8 V 35 35 VCC = 4.5 V; VI = 2.0 V -75 -75 VCC = 5.5 V; VI = 0 to 5.5 V 800 IHOLD Bus Hold current inputs5 74ABTH16821A IOFF Power-off leakage current VCC = 0.0 V; VO or VI 4.5 V 5.0 100 100 A Power-up/down 3-State output current4 VCC = 2.1 V; VO = 0.5 V; VI = GND or VCC; VOE = Don't care 5.0 50 50 A IOZH 3-State output HIGH current VCC = 5.5 V; VO = 2.7 V; VI = VIL or VIH 1.0 10 10 A IOZL 3-State output LOW current VCC = 5.5 V; VO = 0.5 V; VI = VIL or VIH -1.0 -10 -10 A ICEX Output HIGH leakage current VCC = 5.5 V; VO = 5.5 V; VI = GND or VCC 5.0 50 50 A Output current1 VCC = 5.5 V; VO = 2.5 V -90 -180 -180 mA 0.5 1 1 mA VCC = 5.5 V; Outputs LOW, VI = GND or VCC 10 19 19 mA VCC = 5.5 V; Outputs 3-State; VI = GND or VCC 0.5 1 1 mA VCC = 5.5 V; one input at 3.4 V, other inputs at VCC or GND 0.25 1.5 1.5 mA IPU/PD IO ICCH ICCL Quiescent supply current ICCZ ICC -50 VCC = 5.5 V; Outputs HIGH, VI = GND or VCC Additional supply current per input pin2 -50 A NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4 V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0 V and 2.1 V with a transition time of up to 10 msec. From VCC = 2.1 V to VCC = 5 V a transition time of up to 100 sec is permitted. 5. This is the bus hold overdrive current required to force the input to the opposite logic state. 2002 Dec 13 5 Philips Semiconductors Product data 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ABT16821A 74ABTH16821A AC CHARACTERISTICS GND = 0 V, tR = tF = 2.5 ns, CL = 50 pF, RL = 500 LIMITS SYMBOL PARAMETER Tamb = +25 C VCC = +5.0 V WAVEFORM Tamb = -40 C to +85 C VCC = +5.0 V 0.5V MAX MIN UNIT MIN TYP fMAX Maximum clock frequency 1 160 250 MAX tPLH tPHL Propagation delay nCP to nQx 1 1.3 1.1 2.4 2.0 3.3 2.6 1.3 1.1 3.7 3.0 ns tPZH tPZL Output enable time to HIGH and LOW level 3 4 1.4 1.2 2.5 2.3 3.3 3.0 1.4 1.2 4.1 3.7 ns tPHZ tPLZ Output disable time from HIGH and LOW level 3 4 1.6 1.3 3.2 2.3 4.1 3.1 1.6 1.3 4.8 3.3 ns 160 MHz AC SETUP REQUIREMENTS GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER Tamb = +25 C VCC = +5.0 V WAVEFORM Tamb = -40 C to +85 C VCC = +5.0 V 0.5 V MIN TYP MIN UNIT MAX ts(H) ts(L) Set-up time, HIGH or LOW nDx to nCP 2 1.8 1.8 1.2 -0.9 1.8 1.8 ns th(H) th(L) Hold time, HIGH or LOW nDx to nCP 2 1.0 1.0 0.8 -1.0 1.0 1.0 ns tw(H) tw(L) nCP pulse width HIGH or LOW 1 2.5 2.5 0.8 1.0 2.5 2.5 ns AC WAVEFORMS nCP VM tw(H) VM tw(L) tPHL 3.0V or VCC whichever is less VM VM VM 0V tPZH 0V tPHZ VOH tPLH VM VY VM VOH nQx 3.0V or VCC whichever is less nOE 1/fMAX nQx VM 0V VOL SH00007 SH00005 Waveform 3. 3-State Output Enable Time to HIGH Level and Output Disable Time from HIGH Level Waveform 1. Propagation Delay, Clock Input to Output, Clock Pulse Width, and Maximum Clock frequency 3.0V or VCC whichever is less nOE nDx VM VM VM VM ts(H) th(H) ts(L) th(L) 3.0V or VCC whichever is less VM 0V tPZL 0V CP VM VM VM tPLZ 3.0V or VCC nQx 3.0V or VCC whichever is less VM VX VOL 0V 0V SH00008 Waveform 4. 3-State Output Enable Time to LOW Level and Output Disable Time from LOW Level SH00006 Waveform 2. Data Set-up and Hold Times 2002 Dec 13 6 Philips Semiconductors Product data 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ABT16821A 74ABTH16821A TEST CIRCUIT AND WAVEFORM VCC 7.0V PULSE GENERATOR VOUT VIN tW 90% VM NEGATIVE PULSE CL 10% 0V RL tTHL (tF) tTLH (tR) tTLH (tR) tTHL (tF) 90% POSITIVE PULSE Test Circuit for 3-State Outputs AMP (V) 90% VM VM 10% 10% tW SWITCH POSITION TEST SWITCH tPLZ closed tPZL closed All other open 0V VM = 1.5V Input Pulse Definition INPUT PULSE REQUIREMENTS DEFINITIONS RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. AMP (V) VM 10% RL D.U.T. RT 90% FAMILY 74ABT/H16 Amplitude Rep. Rate tW tR tF 3.0V 1MHz 500ns 2.5ns 2.5ns SA00018 2002 Dec 13 7 Philips Semiconductors Product data 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ABT16821A 74ABTH16821A SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm 2002 Dec 13 8 SOT371-1 Philips Semiconductors Product data 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ABT16821A 74ABTH16821A TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm 2002 Dec 13 9 SOT364-1 Philips Semiconductors Product data 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ABT16821A 74ABTH16821A REVISION HISTORY Rev Date Description _2 20021213 Product data (9397 750 10855); ECN 853-1796 29295 of 12 December 2002. Supersedes data of 27 February 1998 (9397 750 03501). Modifications: * Ordering information table: remove "North America" column; remove 74ABTH16821ADL package offering. _ 19980227 2002 Dec 13 Product specification (9397 750 03501). ECN 853-1796 19026 of 27 February 1998. 10 Philips Semiconductors Product data 20-bit bus-interface D-type flip-flop; positive-edge trigger (3-State) 74ABT16821A 74ABTH16821A Data sheet status Level Data sheet status [1] Product status [2] [3] Definitions I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. [3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products--including circuits, standard cells, and/or software--described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 Date of release: 12-02 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. Document order number: 2002 Dec 13 11 9397 750 10855