74ABT16821A
74ABTH16821A
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
Product data
Supersedes data of 1998 Feb 27 2002 Dec 13
INTEGRATED CIRCUITS
Philips Semiconductors Product data
74ABT16821A
74ABTH16821A
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
2
2002 Dec 13
FEATURES
•20-bit positive-edge triggered register
•Multiple VCC and GND pins minimize switching noise
•Live insertion/extraction permitted
•Power-up reset
•Power-up 3-State
•74ABTH16821A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused
inputs
•Output capability: +64 mA / –32 mA
•Latch-up protection exceeds 500mA per JEDEC Std 17
•ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
DESCRIPTION
The 74ABT16821A high-performance BiCMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ABT16821A has two 10-bit, edge triggered registers, with
each register coupled to a 3-State output buffer. The two sections of
each register are controlled independently by the clock (nCP) and
Output Enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one
set-up time before the LOW-to-HIGH clock transition, is transferred
to the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active-LOW Output Enable (nOE) controls all ten 3-State
buffers independent of the register operation. When nOE is LOW,
the data in the register appears at the outputs. When nOE is HIGH,
the outputs are in high impedance “off” state, which means they will
neither drive nor load the bus.
Two options are available, 74ABT16821A which does not have the
bus-hold feature and 74ABTH16821A which incorporates the
bus-hold feature.
QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS
Tamb = 25 °C; GND = 0 V TYPICAL UNIT
tPLH
tPHL Propagation delay
nCP to nQx CL = 50 pF; VCC = 5 V 2.4
2.0 ns
CIN Input capacitance VI = 0 V or VCC 3 pF
COUT Output capacitance VO = 0 V or VCC; 3-State 7 pF
ICCZ
Quiescent su
pp
ly current
Outputs disabled; VCC = 5.5 V 500 µA
ICCL
Q
u
iescent
s
u
ppl
y
c
u
rrent
Outputs LOW; VCC = 5.5 V 10 mA
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE PART NUMBER DWG NUMBER
56-Pin Plastic SSOP T ype III –40 °C to +85 °C 74ABT16821ADL SOT371-1
56-Pin Plastic TSSOP Type II –40 °C to +85 °C 74ABT16821ADGG SOT364-1
56-Pin Plastic TSSOP Type II –40 °C to +85 °C 74ABTH16821ADGG SOT364-1
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
55, 54, 52, 51, 49, 48, 47, 45, 44, 43,
42, 41, 40, 38, 37, 36, 34, 33, 31, 30 1D0 – 1D9
2D0 – 2D9 Data inputs
2, 3, 5, 6, 8, 9, 10, 12, 13, 14,
15, 16, 17, 19, 20, 21, 23, 24, 26, 27 1Q0 – 1Q9
2Q0 – 2Q9 Data outputs
1, 28 1OE, 2OE Output enable inputs (active-LOW)
56, 29 1CP, 2CP Clock pulse inputs (active rising edge)
4, 11, 18, 25, 32, 39, 46, 53 GND Ground (0 V)
7, 22, 35, 50 VCC Positive supply voltage
Philips Semiconductors Product data
74ABT16821A
74ABTH16821A
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
2002 Dec 13 3
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28 29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
561OE
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
GND
VCC
GND
1Q7
1Q8
1Q9
2Q0
2Q1
2Q2
GND
2Q3
2Q4
2Q5
VCC
2Q6
2Q7
GND
2Q8
2Q9
2OE
1CP
1D0
1D1
GND
1D2
1D3
VCC
1D4
1D5
1D6
GND
1D7
1D8
1D9
2D0
2D1
2D2
GND
2D3
2D4
2D5
VCC
2D6
2D7
GND
2D8
2D9
2CP
SH00001
LOGIC SYMBOL
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
1D8 1D9
1Q8 1Q9
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
2D8 2D9
2Q8 2Q9
55 54 52 51 49 48 47 45 44 43
56
1
29
28
2 3 5 6 8 9 10 12 13 14
42 41 40 38 37 36 34 33 31 30
15 16 17 19 20 21 23 24 26 27
SH00002
1CP
1OE
2CP
2OE
LOGIC SYMBOL (IEEE/IEC)
EN2
2 ∇
C1
EN4
C3
1D
4 ∇
3D
SH00003
1
56
28
29
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
27
1OE
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
1Q9
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
2OE
1CP
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
2CP
FUNCTION TABLE
INPUTS INTERNAL OUTPUTS OPERATING
nOE nCP nDx
INTERNAL
REGISTER nQ0 – nQ9
OPERATING
MODE
L
L↑
↑l
hL
HL
HLoad and read
register
L↑X NC NC Hold
H
H↑
↑X
Dn NC
Dn Z
ZDisable
outputs
H = High voltage level
h = High voltage level one set-up time prior to the LOW-to-HIGH
clock transition
L = Low voltage level
l = Low voltage level one set-up time prior to the LOW-to-HIGH
clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑= LOW-to-HIGH clock transition
↑= Not a LOW-to-HIGH clock transition
Philips Semiconductors Product data
74ABT16821A
74ABTH16821A
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
2002 Dec 13 4
LOGIC DIAGRAM
CP Q
D
nD0
nQ0
nCP
nOE
CP Q
D
nD1
nQ1
CP Q
D
nD2
nQ2
CPQ
D
nD3
nQ3
CP Q
D
nD4
nQ4
CPQ
D
nD5
nQ5
CP Q
D
nD6
nQ6
CPQ
D
nD7
nQ7
CPQ
D
nD8
nQ8
CPQ
D
nD9
nQ9
SH00004
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL PARAMETER CONDITIONS RATING UNIT
VCC DC supply voltage –0.5 to +7.0 V
IIK DC input diode current VI < 0 V –18 mA
VIDC input voltage3–1.2 to +7.0 V
IOK DC output diode current VO < 0 V –50 mA
VOUT DC output voltage3Output in Off or HIGH state –0.5 to +5.5 V
IOUT
DC out
p
ut current
Output in LOW state 128
mA
I
OUT
DC
out ut
current
Output in HIGH state –64
mA
Tstg Storage temperature range –65 to 150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS UNIT
MIN MAX
VCC DC supply voltage 4.5 5.5 V
VIInput voltage 0 VCC V
VIH High-level input voltage 2.0 V
VIL Low-level Input voltage 0.8 V
IOH High-level output current –32 mA
IOL Low-level output current 64 mA
∆t/∆vInput transition rise or fall rate 0 10 ns/V
Tamb Operating free-air temperature range –40 +85 °C
Philips Semiconductors Product data
74ABT16821A
74ABTH16821A
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
2002 Dec 13 5
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER TEST CONDITIONS Tamb = +25 °CTamb = –40 °C
to +85 °CUNIT
Min Typ Max Min Max
VIK Input clamp voltage VCC = 4.5 V; IIK = –18 mA –0.9 –1.2 –1.2 V
VCC = 4.5 V ; IOH = –3 mA; VI = VIL or VIH 2.5 2.9 2.5 V
VOH HIGH-level output voltage VCC = 5.0 V ; IOH = –3 mA; VI = VIL or VIH 3.0 3.4 3.0 V
VCC = 4.5 V ; IOH = –32 mA; VI = VIL or VIH 2.0 2.4 2.0 V
VOL LOW-level output voltage VCC = 4.5 V ; IOL = 64 mA; VI = VIL or VIH 0.36 0.55 0.55 V
VRST Power-up output voltage3VCC = 5.5 V ; IO = 1 mA; VI = GND or VCC 0.13 0.55 0.55 V
IIInput leakage current VCC = 5.5 V ; VI = VCC or GND ±0.01 ±1.0 ±1.0 µA
VCC = 5.5 V ; VI = VCC or GND Control pins ±0.01 ±1±1µA
IIInput leakage current
74ABTH16821A
VCC = 5.5 V ; VI = VCC
Data
p
ins
0.01 1 1 µA
74ABTH16821A
VCC = 5.5 V ; VI = 0
Data
pins
–1 –3 –5 µA
5
VCC = 4.5 V ; VI = 0.8 V 35 35
IHOLD Bus Hold current inputs
5
74ABTH16821A
VCC = 4.5 V ; VI = 2.0 V –75 –75 µA
74ABTH16821A
VCC = 5.5 V ; VI = 0 to 5.5 V ±800
IOFF Power-of f leakage current VCC = 0.0 V ; VO or VI ≤ 4.5 V ±5.0 ±100 ±100 µA
IPU/PD Power-up/down 3-State
output current4VCC = 2.1 V ; VO = 0.5 V; VI = GND or VCC;
VOE = Don’t care ±5.0 ±50 ±50 µA
IOZH 3-State output HIGH current VCC = 5.5 V ; VO = 2.7 V; VI = VIL or VIH 1.0 10 10 µA
IOZL 3-State output LOW current VCC = 5.5 V; VO = 0.5 V; VI = VIL or VIH –1.0 –10 –10 µA
ICEX Output HIGH leakage
current VCC = 5.5 V ; VO = 5.5 V; VI = GND or VCC 5.0 50 50 µA
IOOutput current1VCC = 5.5 V; VO = 2.5 V –50 –90 –180 –50 –180 mA
ICCH VCC = 5.5 V; Outputs HIGH, VI = GND or VCC 0.5 1 1 mA
ICCL Quiescent supply current VCC = 5.5 V; Outputs LOW, VI = GND or VCC 10 19 19 mA
ICCZ VCC = 5.5 V ; Outputs 3-State; VI = GND or VCC 0.5 1 1 mA
∆ICC Additional supply current
per input pin2VCC = 5.5 V ; one input at 3.4 V, other inputs at
VCC or GND 0.25 1.5 1.5 mA
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4 V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any VCC between 0 V and 2.1 V with a transition time of up to 10 msec. From VCC = 2.1 V to VCC = 5 V a
transition time of up to 100 µsec is permitted.
5. This is the bus hold overdrive current required to force the input to the opposite logic state.
Philips Semiconductors Product data
74ABT16821A
74ABTH16821A
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
2002 Dec 13 6
AC CHARACTERISTICS
GND = 0 V, tR = tF = 2.5 ns, CL = 50 pF, RL = 500 Ω
LIMITS
SYMBOL PARAMETER WAVEFORM Tamb = +25 °C
VCC = +5.0 V Tamb = –40 °C to +85 °C
VCC = +5.0 V ±0.5V UNIT
MIN TYP MAX MIN MAX
fMAX Maximum clock frequency 1 160 250 160 MHz
tPLH
tPHL Propagation delay
nCP to nQx 11.3
1.1 2.4
2.0 3.3
2.6 1.3
1.1 3.7
3.0 ns
tPZH
tPZL Output enable time
to HIGH and LOW level 3
41.4
1.2 2.5
2.3 3.3
3.0 1.4
1.2 4.1
3.7 ns
tPHZ
tPLZ Output disable time
from HIGH and LOW level 3
41.6
1.3 3.2
2.3 4.1
3.1 1.6
1.3 4.8
3.3 ns
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω
LIMITS
SYMBOL PARAMETER WAVEFORM Tamb = +25 °C
VCC = +5.0 V Tamb = –40 °C to +85 °C
VCC = +5.0 V ±0.5 V UNIT
MIN TYP MIN MAX
ts(H)
ts(L) Set-up time, HIGH or LOW
nDx to nCP 21.8
1.8 1.2
–0.9 1.8
1.8 ns
th(H)
th(L) Hold time, HIGH or LOW
nDx to nCP 21.0
1.0 0.8
–1.0 1.0
1.0 ns
tw(H)
tw(L) nCP pulse width
HIGH or LOW 12.5
2.5 0.8
1.0 2.5
2.5 ns
AC WAVEFORMS
VM
SH00005
nCP
nQx
VM
tw(H)
tPHL
VM
tPLH
1/fMAX
VM
VM
tw(L) 0V
VOH
VOL
3.0V or VCC
whichever
is less
W aveform 1. Propagation Delay, Clock Input to Output,
Clock Pulse Width, and Maximum Clock frequency
th(H)ts(H)
CP
SH00006
VMVM
VM
VM
VMVM
th(L)ts(L)
nDx 0V
0V
3.0V or VCC
whichever
is less
3.0V or VCC
whichever
is less
Waveform 2. Data Set-up and Hold Times
VY
VM
VM
VM
nQx
tPZH tPHZ
SH00007
nOE
0V
VOH
0V
3.0V or VCC
whichever
is less
W aveform 3. 3-State Output Enable Time to HIGH Level
and Output Disable Time from HIGH Level
VX
VM
VM
VM
nQx
tPZL tPLZ
SH00008
nOE
VOL
0V
0V
3.0V or VCC
3.0V or VCC
whichever
is less
W aveform 4. 3-State Output Enable Time to LOW Level
and Output Disable Time from LOW Level
Philips Semiconductors Product data
74ABT16821A
74ABTH16821A
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
2002 Dec 13 7
TEST CIRCUIT AND WAVEFORM
PULSE
GENERATOR
RT
VIN D.U.T. VOUT
RL
VCC
RL
7.0V
Test Circuit for 3-State Outputs
VMVM
tWAMP (V)
NEGATIVE
PULSE 10% 10%
90% 90%
0V
VMVM
tW
AMP (V)
POSITIVE
PULSE
90% 90%
10% 10% 0V
tTHL (tF)
tTLH (tR)t
THL (tF)
tTLH (tR)
VM = 1.5V
Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance;
see AC CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of
pulse generators.
INPUT PULSE REQUIREMENTS
FAMILY Amplitude Rep. Rate tWtRtF
74ABT/H16 3.0V 1MHz 500ns 2.5ns 2.5ns
SWITCH POSITION
TEST SWITCH
tPLZ closed
tPZL closed
All other open
SA00018
CL
Philips Semiconductors Product data
74ABT16821A
74ABTH16821A
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
2002 Dec 13 8
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm SOT371-1
Philips Semiconductors Product data
74ABT16821A
74ABTH16821A
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
2002 Dec 13 9
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1
Philips Semiconductors Product data
74ABT16821A
74ABTH16821A
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
2002 Dec 13 10
REVISION HISTORY
Rev Date Description
_2 20021213 Product data (9397 750 10855); ECN 853-1796 29295 of 12 December 2002.
Supersedes data of 27 February 1998 (9397 750 03501).
Modifications:
•Ordering information table: remove ”North America” column; remove 74ABTH16821ADL package offering.
_ 19980227 Product specification (9397 750 03501). ECN 853-1796 19026 of 27 February 1998.
Philips Semiconductors Product data
74ABT16821A
74ABTH16821A
20-bit bus-interface D-type flip-flop;
positive-edge trigger (3-State)
2002 Dec 13 11
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys
no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent,
copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit
http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Koninklijke Philips Electronics N.V. 2002
All rights reserved. Printed in U.S.A.
Date of release: 12-02
Document order number: 9397 750 10855
Data sheet status[1]
Objective data
Preliminary data
Product data
Product
status[2] [3]
Development
Qualification
Production
Definitions
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
Data sheet status
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Level
I
II
III
