HARRIS SENICOND SECTOR 3875081 GE SOLID STATE O18 13642 OD 37E D MM 4302271 0021456 T MBH it mang AS CD4049A, CD4050A Types CMOS Hex Buffer/Converters RECOMMENDED OPERATING CONDITIONS at Ta=25C, Except as Noted. For maximum reliability, nominal operating conditions should be selected so that CD4049AInverting Type CD4050ANon-Inverting Type The CD4049A and CD4050A are inverting and non-inverting hex buffers, respectively, and feature logic-level conversion using only one supply: voltage. (Vcc). The input-signal high level (VjH) can exceed the Voc supply voltage when these devices are used for logic- level conversions, These devices are intended for use as CMOS to OTL/TTL- converters and can. drive directly two DTL/TTL loads. (Vcc=5 V, VoL 20.4 V, and IpN 23.2 mA.) The CD4049A and CD4050A are. designated as replacements for CD4009A and CD4010A, respectively. Because the. CD4049A and CD4050A require only one power supply, they are preferred over the CD4009A and CD4010A and shoutd be used in place of the CD4009A and CD4010A in all inverter, cur- rent driver, or logic-level conversion appli- cations, In these applications. the CD4049A and CD4050A are pin compatible with the CD4009A and CD4010A respectively, and can be substituted for these devices in existing as well as in new designs. Terminal No. 16 is not connected internally on the GD4049A or CD4050A, therefore, connection to this terminal is of no consequence to cir- cult operation. For applications not re- quiring high sink-current or voltage conver- sion, the CD4069 Hex Inverter is recom- mended. These types are supplied in 16-lead hermetic dual-in-line ceramic pacKages (D and F suffixes), 16-lead dual-in-line plastic pack- age (E suffix), 16-lead ceramic flat packages (K suffix), and in chip form (H suffix). Features: & High sink current for driving 2 TTL loads @ High-to-low fevel logic conversion @ Quiescent current specified to 15 V @ Maximum input leakage of 1 uA at 15 V (full._package-temperature range) Applications: CMOS to DTL/TTL hex converter = CMOS current sink or source driver CMOS high-to-low fogic-level operation is always within the following ranges: TSZ-N-OO CHARACTERISTIC LIMITS UNITS Min. } Max. Supply-Voltage Range (Vcc) (For Ta=Full Package- 3 12 Temperature Range) Input. Voltage Range (V)) Veco" | 12 The CD4049 and CD4050 have high-to-low-level voltage conversion capability but not low-to-high-level; therefore it is recommended that Vj > Voc. STATIC ELECTRICAL CHARACTERISTICS converter A 22 GA A I> Ga a 2f>e4 ro) 8 >+ He i> Ise c + rec o 2 2 yd o 2 Jo et 2 ng et 2 oe 4 5 uF F 4. 15 ur Veo Veg L Vgg 2 Vg5 NG 13 ANC 213 . NG +16 RCS TTR NC #16 2203-21907 CD4049A cp40504 Fig.1 Functional diagrams. Limits at Indicated Temperatures (C) Characteristic Conditions D, F, K, H Packages ~_E Package Units Vo-| Yin | Voc) 55 +26 | +128 | 40 425 | 485 (vy ]} (vd (Vv) Typ.| Limit Typ.} Limit ulescent - | ~ | 5| 03 {oo1| 03 | 20 | 3 1o03} 3 | 42 Current - = 10| 0.65 {0.01] 0.5 30 5 0.05 5 70} pA - ~ 15 10 {0.02} 10 100 50 |0.05; 50 500 ty Max. . Output Voltage: Low-Level, |] | 0,54 5 0 Typ.;.0.05 Max. VoL = {0,10} 10 0 Typ.; 0.05 Max. Vv High-Level, | | 0,5] 5 4.95 Min.; 5 Typ. Vou 10, i0F 10 9.95 Min.; 10 Typ. Noise Immunity: Inputs Low, {3.6 - 5 1.5 Min.; 2.25 Typ. VN 72| - | 10 3 Min.; 4.5 Typ. CD4050A Inputs High, } 1.4 - 5 1.5 Min.; 2.25 Typ. VNH 2.8 ~ 10 3 Min.; 4.5 Typ. Vv All Types Inputs Low, | 3.6 = 5 1 Min.; 1.5 Typ. VNE 721 = | 10 2 Min.; 3 Typ. CD4049A Noise Margin: Inputs Low, | 4.5 - 5 1 Min. Vaya Min. [| O | | fof 7 Min. CD4050A Inputs High, | 0.5 - 6 1 Min. VNMH Min. | 1 - 10 1 Min. Vv CD4050A fo Output Drive Current: N-Channel {0.4 ~ 4.5] 3.3 [5.2 | 2.6 1.8 3.1 | 5.2 2.6 2.1 (Sink), 0.4 - 5 | 3.75] 6 3.4 2.1 3.6 6 3 2.5 IpN Min. 0.5 - 10 10 16 8 5.6 9.6 | 16 8 6.6 P-Channel [4.5 {| 5 [-062} 1 [-05 [-0.35[-0.6/i1 _|-05/-04 mA (Source), 2.5 _ 5 |-1.85}-2.5}-1.25/ -0.9 |1.5]2.5 |-1.25] -1 - IpP Min. 9.5 - 10 |1,85]~2.5 | 1.25} ~0.9. | 1.5]~-2.5 |-1.25 |] 1 Tnput Leakage Current, Any fnput | 15 +195 Typ., 1 Max. uA te Max. 590 3782 D-11J7E HARRIS SEMICOND SECTOR D Mm 430 3875081 G E SOLID STATE - MAXIMUM RATINGS, Absolute-Maximum Values: STORAGE-TEMPERATURE RANGE (Tyg) -- +--+ leet eee n erence beeen enone 65 to +150C OPERATING-TEMPERATURE RANGE (Ta): PACKAGE'TYPES D,F,K,H .... 0. ee eee eee peek e een eben ene eb ener enene -55:to +#125C PACKAGE TYPE Go. cece see eee eee Cet b eee e teens eee eee 40 to +85C DC SUPPLY-VOLTAGE RANGE,. (Veo) (Voltages referenced to Vss Terminalh. 6... pene eeeeee vee c cece ee ben eteeeee + 0.5 to+15 V POWER DISSIPATION PER PACKAGE (Pp): FOR T= 40 to #60C (PACKAGE TYPE E) 0... eee eee eee eee etree eet 500 mW FOR Ta= #60 to 485C (PACKAGE TYPE EE} = ..-.- Derate Linearly at 12 MW/C to 200 mW FOR Ta =-55 to #100C (PACKAGE TYPES D, F,K) 9 -- +0 --- eee eee eee eee 500 mw FOR Ta = +100 to +125C (PACKAGE TYPES D, F, K). OEVICE DISSIPATION PER OUTPUT TRANSISTOR FOR Ta = FULL PACKAGE-TEMPERATURE RANGE [ALL PACKAGE TYPES)......- 100 mW INPUT VOLTAGE RANGE, ALL INPUTS ....... 200-0 eee eee eee 05 t0 Vop 10.5 V- LEAD TEMPERATURE (DURING SOLDERING): Atdistance 1/16 1/32 inch (1.59 * 0.79 mm) from case for 10s max. -. wees +265C AMCIENT TEMPERATURE BIENT. TEMPERATURE (Tale 25C SUPPLY VOLTAGE OUTPUT VOLTAGE (Vo)V INFUT VOLTAGE (Vp) =v wWecs-20681 3064063CUGhUThUUU lh IN#@UT VOLTAGE (yI Fig..4Minimum and maximum voltage transfer characteristics for CD4049A. 9209-20400 Fig. 3-Minimum and maximum voltage transfer characteristics for CD4050A. 234 5 6 7 @ 8 IMPUT VOLTAGE Vy I e2e5-20484 Fig. 7Typical voltage transfer charac- teristics as a function of tempera- ture for CD4050A. a a ee ee ee IHPUT. VOLTAGE ivy Vv stca-20483 Fig: 6-Typical voltage transfer charac- teristics as a function of tempera- ture for CD40494. ORAN-TO-SOURCE VOLTASE (pg) wu 0x) 1NaWeND NINO i : 2 : 2 3 Z 4 : 5 NG--POWER conve PER nevice *H ASSIPATION $00 mit . i 40 60 ag 100 Fig. 9Typical and minimum p-channel drain LOAD CAPACITANCE {CLIoF characteristics as a function of gate-to- source voltage (Vag) for CD4049A, CD4050A. 9205-20829 time vs. Cy for CD4049A. 01 13643 Fig: 10Typical high-to-low level propagation delay 227) 0021457 1 MBHAS Bo T-52-1\- CO CD4049A, CD4050A Types. AMBIENT TEMPERATURE (Tg)925C VOLTAGE OUTPUT VOLTAGE (g}V ' INPUT tvyhv s2cs-20479 Fig. 2-Minimum and maximum voltage transter characteristics for CD4049A. AMBIENT TEMPERATURE (Tq # 25 SUPPLY: VOLTAGE (Yec]=i0 34S 8 tT 8 Oe INPUT VOLTAGE {VzIV 9209-20487 Fig. Minimum and maximum voltage transfer characteristics for CD4050A. AMBIENT TEMPERATURE iT, )*25C TYAICAL TEMPERATURE COEFFICIENT iC DRAIN CURRENT (Ip )mA 2 4 1 ORAIN-TO-SOURCE foursce Nos! $208-20465al. Fig. 8Typical and minimum n-channel drain characteristics as a function of gate-to-. souree voltage (V gg) for CD4049A, CD4050A. AMBIENT TEMPERATURE (Tg}#25C TYPICAL TEMPERATURE coer ricer FOR ALL VALUES OF LOW-LEVEL PROPAGATION DELAY TIME (pig os 00 pF 20 40 Cy a LOAD CAPACITANCE (,) $2cs-20607 Fig. 11-Typical high-to-low level propagatian delay time vs. C, for CD4050A. 3783 D-12_ 59T-HARRIS SEMICOND SECTOR CD4049A, CD4050A Types CL=15 pF, Ry=200 kQ 3875001 GG E SOLID STATE 27E D MM 4302272 goe4sa 3 MBHAS DYNAMIC ELECTRICAL CHARACTERISTICS at Tan26C Input t,,t#20 ns, LIMITS CHARACTERISTIC CONDITIONS ALL PKGS. UNITS Mi Veco Typ.}| Max. Propagation Delay Time: Low-to-High, tp_y . 5 50 80 CD40494 9140125168 a . 5 5 75 | 140 CO4050A T4910] 35 185 High-to-Low, tPHL : 5 5 15 55 a co4o4eA Tag | 10} 10 [30 ae 5 5 55 110 : : GD4060A 10 10 25 55 Transition Time: : . 5 5 50 | 100 Low-to-High, *TLH 10 10 30 | 60 as . 5 5 20 45 High-to-Low, tTHL 10 10 16 1 40 Input Capacitance, Cy CD4049A = - 15 - F CD4050A | = 5 | - P AMBIENT TEMPERATURE (Ta) 925C TYMICAL TEMPERATURE COEFFICIENT FOR ALL VALUES OF * Nee O.38/C LOW= LEVEL TRANSITION TIME.( ty, ) 20 40 0 LOAD CAPACITANCE {C,] 9268 = 20526 Fig. 14Typical high-to-low level transition time vs: Cy, for CD40494, CD4050A, ee 3 o Aa OM - POWER DISSIPANION PER INVERTER (Pp)) pW 10 of INPUT RISE ARO FALL TIME (tet)? RUBEN TEMPERATURE (Tg )25C. TYPICAL TEMPERATURE. COEF MICE FOR ALL VALUES OF Veg 0.5% 7" HGH-LEVEL TRANSITION TIME ity iy )ne 20. 40 0 0 100 ROAD CAPACITANCE (CLIoF Sits-z04te Fig. 18-Typical low-to-high level transition time vs. C, for CD4049A, CD4050A, POWER DISSIPATION. PER INVERTER (Pp lop Lo) WMPUT RISE AWD FALL TIME (1, ,.t) t Vss OTHER RWuTs aT 3269-27400 1 Yop oR Vsg- Fig. 19=Noise.is Immunity test circuit. Fig. 20Input leakage current test circuit, 9268-20490R 92C8- 20488 Fig. 17-Typleal power dissipation -vs, transition Fig. 18-Typical power dissipation vs. transition time per Inverter CD4049A. time per inverter CD4050A. r Y vj e Yoo 2 ineurs Wweuts_ [ QuTPuTs t __, NOTE: % Vane, (HPuts MEASURE INPUTS Do-YnH we Lie Yoo ~ SEQUENTIALLY, + Lm at, TO BOTH Vpp ANO Vg: wo RUF ees eae be 7 NOT Yoo on Yes 8i08- 27408 est ANY ONE INPUT, Ty Vgg S2s-2r408 OTE we JL 13644 dD CU T52-1 60 HIGH-LEVEL PROPAGATION DELAY TIME tip, ae 40 60 80 8 LOAD CAPACITANCE (C\I-0F ae Fig. 12Typical tow-tofiigh level propagation delay time vs. Cy for CD4049A. AMSIENT TEMPERATURE (Tgli2See TYPICAL TEMPERATURE COEFFICIENT FOR ALL VALUES OF Veg 20.3% C Lovo caPAciTaNCe ten) oF ftcs-29e Fig. 13Typical low-to-high lavel propagation delay time vs. C, for CD4050A. . .) wt ws INPUT FAEQUENCY (16) wacasnose? Fig. 16-Typical dissipation characteristics tor CD4049A, CD4050A. tN Vee Veo 4 P Ak our JL fu Ww 7 u : ouT N N 4se 4's (a) : tb) 92CS20UF Fig. 22 {a]Schematic diagram of CD4049A, af 6 identical units. (b} Schematic diagram of CD4050A, 1 of 6 identical units. Fig. 21 5 isscont device current test circuit. 592HARRIS SEMICOND SECTOR 37E D MM 430227) 0021568 T MBHAS 3875081 GE SOLID STATE O1E 13754 BD - CL EGO2Z0 Dimensional Outlines Dual-In- Line Welded-Seal Ceramic Packages a (D) SUFFIX (JEDEC MO-001-AD) (D) SUFFIX (JEDEC MO-001-AE} 7" } 14-Lead Dual-In-Line Welded-Seat 16-Lead Dual-In-Line Welded-Seal y Ceramic Package Ceramic Package myer ILLIMET! t sy MBOL INCHES Note [MILLIMETERS an | symeon INCHES | re |_MILLIMETERS MIN. | MAX. MIN. | MAX. MIN. | MAX. MIN. | MAX. A 0.120 | 0.160 3.05 4.06 ha A 0.120 | 0.160 3.05 4.06 Ay 0.020 | 0.065 Ost 1.65 = ears ag = B | 0014 | 0.020 0.356 | 0.508 ; 84 0.060 | 0.086 127 165 By 0.035 | 0.065 0.89 1.66 Se FA c 0.008 | 0.012 + | 0.200] 0.308 c 0.008 | 0.012 1 0.204 | 0.304 \ ' f f D 0.745 | 0.770 18.93 | 19.56 D_ | 0.746 | 0.785 18.93 | 19.93 eorrom view Gwe E 0.300 | 0.325 7.62 8.25 E 0.300 | 0.325 7.62 8.25 _ ote _ 4 1 __| a2e0 | 0.260 6.10 | 6.60 E, | 0.240 | 0.260 610 | 6.60 71 0.100 TP 2 2.64 TP 0.300 TP 23 7.62 TP ey 0.100 TP 2 2.54 TP NOTES: L 0.125 | 0.150 3.18 3.81 ee 0.300 TP 2,3 7.62 TP Refer to Rules for Dimensioning (JEDEC Publication No. 95} u 0.000 0.030 0.000 0.76 far Axial Lead Product Outlines. = oo Tige Tle Tie L | 0.125 | 0.150 318 | 3.81 1. When this device is supplied solder-dipped, the maxi lead n 4 5 Ly | 0.000 | 0.030 0.000 | 0.76 thickness (narrow portion) will not exceed 0.013" (0.33 mm). 1 4 a 9 75 4 ? 15 2. Leads within 0.005 (0.12 mm) radius of True Position (TP) at N41 9 6 o gauge piane with maximum material condition-and unit installed. ay 0.050 | 0.085 1.27 2.15 N 16 5 16 3. eg applies in zone Ly when unit installed. s 0.065 0.090 1.66 2.28 Ny 0 6 0 4. a applies to spread leads prior to installation. 5. Nis the maximum quantity of lead positions. * TIR2 a 0.050 | 0.085 1.27 2.15 6. Ny is the quantity of allowable missing leads. $s 0.015 | 0.060 0.39 1.62 928S-4286R5 (D) SUFFIX (JEDEC MO-015-AG) (D) SUFFIX (JEDEC MO-015-AH) 24-Lead Dual-In-Line Welded-Seal 28-Lead Dual-In-Line Welded-Seal Cc ic Package Ceramic Package INCHES MILLIMETERS SYMBOL WIND MAX NOTE iin. MAX SYMBOL A 0.090} 0.200 2.29 5.08 Aq 0.020{ 0.070 0.51 1.78 A 9 0.070 2 8 0.015} 0.020 0.381 0.508 0.015 | 0.055 . 1.39 a1 0.045] 0.055 1.143 1.397 c 0.008} 0.012 1 0.204 0.304 1.380 {1 36.06 o 1.15 } 1.22 29.21 30.98 E 0.6001 0.625 15.24 | 15.87 0.485 |0.515 12.32 | 13.08 Ey 0.480] 0.520 12.20 13.20 a1 0.100 TP 2 2.54 1P 0.600 TP 2,3 15.24 TP cA 0.600 TP 2,3 15.24 TP 0 10.030 0 0.76 Rater to Rules for Dimensioning {JEDEC Publication No. 95} . 0.100 | 0.180 2e8 | 487 1 ul HMensioning ication No, for Axial Lead Product Outlines. L2__{ 9.000 | 0.030 0.00 | 9.76 1. When this device is supplied solder-dipped, the maxi a oo j iso | 4 | a0 15 lead thickness (narrow portion} will not exceed 0.013" N 24 5 24 {0.33 mm). Ny Oo 6 0 2. Leads within 0.005 (0.12 mm} radius of True Position O 0.0201 0.080 O51 203 (TP) at gauga ptane with maximum material condition 1 . . . . and unit installed. . $s 0.020 | 0.060 0.51 1.52 92CM-20250R2 3. 8g applies in zone L2 when unit installed. 4. applies to spread leads prior to installation. 92CS-19948R4 5. Nis the maximum quantity of lead positions. 6. Ny is the quantity of allowable missing teads. TO-5 Style Package . SYMBOL INCHES NOTE MILLIMETERS (T) SUFFIX (JEDEC MO-006-AG) MIN. [ MAX, MIN. | MAX! 12-Lead Metal Package a 0.230 2 5.84 TP NOTES: r9o A o 9 0 | 4. Refer to Rutes for Dimensioning Axiat Lead Product Out- to 9D) ~*4 Ag 0.165 | 0.185 4.19 470 lines. $8 0.016 | 0.019 3 0.407 | 0.482 2. Leads at gauge plane within 0.007 (0.178 mm} radius of $B 0 0 0 0 True Position (TP) at maximum material condition. Bo 0.016 | 0.021 3 0.407 0.533 3. $8 applies between L1 and L2. B2 applies between L2 oD 0.335 | 0.370 BS1 9.39 and 0.500" (12.70 mm) from seating plane. Diameter is 40; 0305 | 0.335 775 850 uncontrolled in L1 and beyond 0.500" (12.70 mm). Fy | o020 | 0.080 05t | 1.01 4. Measure from Max. D. j 0.028 | 0.034 0.712 0.863 5. N7 is the quantity of allowable missing leads. k 0.029 | 0.045 4 0.74 1.14 6. N is the maximum quantity of lead positions. Ly 0.000 | 0.050 3 0.00 1.27 2 0.260 | 0.500 3 6.4 12.7 t3 0.500 | 0.562 3 12.7 14.27 a 30 TP 30 TP N 12 6 12 Ny 1 5 1 92Cs-19778 702 wate 2 . . 2 oo a . ~ oy Peet Es Sage NY -08 % ST pees ee geneHARRIS SEMICOND SECTOR 3875081 GE SOLID STATE DUAL-IN-LINE SIDE-BRAZED CERAMIC PACKAGES (D) SUFFIX 18-Lead Dual-In-Line Side-Brazed Ceramic Package 37E D MM 4302271 0021569 1 MBHAS a DIE 13755 on) a T-270-Ad Dimensional Outlines (Cont'd) (D) SUFFIX 22-Lead Oual-In-Line Side-Brazed Ceramic Package sure symeor |__INCHES | ygre| MILLIMETERS NOTE 1 MIN. | MAX. MIN, MAX. wave! A 0.890 | 0.915 22.606 | 23.241 - c -_| 0.200 - 5.080 i 1 T a D 0,015 | 0.021 0.381 | 0.533 : PTE be 4 F 0.054 REF. | 1 1.371 REF. wero ee ae] G | 0.100 asc 1 2.54 Bsc H 0.035 | 0.065 0.889 1.651 NOTES: J 0,008} 0.012| 3 | 0.203] 0.304 1. beads within 0.005" (0.13 mm) adi of True K 0.125 ; 0.150 3.175 3.810 ositian at maximum material condition. 2. Dimension L to center of leads when formed L 0.290 | 0.310 2 7.366 7874 92CS-25186R2 parallel. M ge 159 ge 150 3. When this device is supplied solder-dipped, the maximum lead thickness (narrow portion) will not Pp 0.025 | 0.045 0.635 | 1.143 exceed 0.013" (0.33 mm). N 18 18 92CS-27231R1 (D) SUFFIX (D) SUFFIX 24-Lead Dual-in-Line 40-Lead Dual-In-Line Side-Brezed Ceramic Package Side-Brazed Ceramic Package SYMBOL INCHES __1 wore MILLIMETERS symBot |__'NCHES | woTe MILLIMETERS ; a _ sae MIN. | MAX. MIN. | MAX. ~ : - 2.0: 10.30 . c 0.085 0.145 2.16 3.68 | A 1.980 0 20 51 = Oo 0.015 0.023 0.39 0.68 c 0.095 0.185 2.43 3.93 F 0.040 REF, 102 REF. D 0,017| 0.023 0.43 | 056 6 0.100 BSC 1 2.54 BSC F 0.050 REF, 1.27 REF. H 0.030 0.070 0.77 1.77 G 0.100 BSC 1 2.54 BSC J 0.008 0.012 3 0.21 0,30 H 0.030] 0.070 0.76 1.78 K 9.125 | 0.175 3.18 | 4.44 J 0.008} 0.012] 3 | 0.20 | 0.30 a 0.580 2 {N74 a K 0.126| 0.175 318 | 445 P 0.025 | 0.050 0.64 1.27 L 0.580 2820 2 #(14.74 Ba N 24 24 M = 7 = 7 92CS-30986A1 P 0.025] 0.050 0.64 1.27 N 40 40 92CM-27029R2 Duat-In-Line Plastic and Frit-Seal Ceramic Packages (E) SUFFIX (JEDEC MO-001-AN) INCHES MILLIMETERS 8-Lead Dual-in-Line Ptastic SYMBOL MIN. MAX. NOTE MIN. | MAX. (Mini-DIP} Package A 0.185 |0.200 394 | 5.08 AY 0.020 | 0.050 0.608 1.27 | ps 8 0.014 [0.020 0.356 | 0508 NOTES: . . . 1.65 Refer to Rules for Dimenstoning (JEDEC Publication No. 95) Sst Suse 81 0.035 10.065 9.889 for Axial Lead Product Outlines. SEATING Plant 0.008 40.012 ' 0.203 | 0.304 1, When this device is supplied salder-dipped, the maximum lead - . a TTS Gd PLANE, o 9.370 | 0.400 9.40 | 10.16 (narrow portion) will not exceed 0.013". 0.300 | 0.325 762 | 8.25 2. Leads within 0.005" (0.12 mm) radius of True Position (TP) at Ey 0.240 | 0.260 6.16 6.60 quage plane with maximum material condition and unit instatled, 4 0.100 TP 2 2.54 TP 3. @g applies in zone La when unit installed. c A 0.300 TP 23 7.62 1P 4. 4 applies to spread leads prior to installation. - 5. Nis the of lead = L 0.125 | 0.150 3.18 3.81 6. Nq 1s the quantity of allowable missing leads. lo 0.000 | 0.030 0.000 0.762 . a 0 15 4 0 15 4 N 8 5 8 Toe Ny 0 8 9 Qy 0.040 | 0.075 1.02 1.90 Ss 0.015 | 0.060 0.381 1.62 92CS-2402ERI 703 3895 E-12 -HARRIS SEMICOND SECTOR 37E D MM 4302271 0021570 8 MBHAS 3875081 G E& SOLID STATE | Dimensional Outlines (Cont'd) Dual-in-Line Plastic and Frit-Seal Ceramic Packages (Cont'd) O1E 13756 T-4O-AO_ (E) and (F) SUFFIXES (JEDEC MO-001-AC) > % (E) and (F) SUFFIXES (JEDEC MO-001-A8) rm 14-Lead Dual-In-Line Plastic or 16-Lead Dual-in-Line Plastic or bast ane T $ Frit-Seal Ceramic Package Frit-Seal Ceramic Package INCHES MILLIMETERS INCHES MILLIMETERS MBOL TE us \ | 7 SYMBOL Tain] max] NOTED wax. bY min. | max, | NOTE win, | MAX. eee L A | 0.166 | o.200 3.94] 6.08 A [0.166 | 0.200 304 | 5.08 " Ay__| 0.070 | 0.060 ost | 1.27 Ay | 0.020 | 0.050 ost | 1.27 3 0.014 | 0.020 0.356] 0.56068 2 y yo uu By 0.060 | 0.068 127 1.85 8 0.014 | 0.020 0.356 pred Aes ss aay c 0.008 | 0.012 1] 0.204] 0.308 By | 0.035 | 0.066 0.89 : ee { f o 0.745 | 0.770 19.93 | 19.55 c | o008 | 0012 1 | 0,204 | 0.304 a 1 as E 0.300 | 0.325 7.62 | 8.25 D | 0.745 | 0.785 18.93 | 19.93 ee) eee Lf Ey__{ 0.240 | 0.260 8.10 | 6.60 E | 0300 | 0.326 762 | 8.26 oe " 0.100 TP 2 2.547? E, | 0.240 | 0.260 6.10 | 6.60 NOTES: