PI74SSTV16857 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 14-Bit Registered Buffer Product Features Product Description * PI74 SSTV16857 is designed for low-voltage operation, VDD = VDDQ = 2.3V to 2.7V * Supports SSTL_2 Class I and II specifications * SSTL_2 Input and Output Levels * Designed for DDR Memory * Flow-Through Architecture * Packaging: - 48-pin, 240-mil wide plastic TSSOP (A) - 48-pin, 240-mil wide Lead-Free plastic TSSOP (AE) Pericom Semiconductor's PI74SSTV16857 series of logic circuits are produced using the Company's advanced 0.35 micron CMOS technology, achieving industry leading speed. The 14-bit PI74SSTV16857 universal bus driver is designed for 2.3V to 2.7V VDD operation and SSTL_2 I/O Levels except for the RESET input which is LVCMOS. Data flow from D to Q is controlled by the differential clock , CLK, CLK and RESET. Data is triggered on the positive edge of CLK. CLK must be used to maintain noise margins. RESET must be supported with LVCMOS levels as VREF may not be stable during power-up. RESET is asynchronous and is intended for power-up only and when low assures that all of the registers reset to the Low State, Q outputs are low, and all input receivers, data and clock, are switched off. Pericom's PI74SSTV16857 is characterized for operation from 0 to 70C. Product Pin Configuration Q1 1 48 D1 Q2 2 47 D2 GND 3 46 GND VDDQ 4 45 VDD Q3 5 44 D3 Q4 6 43 D4 Q5 7 42 D5 GND 8 41 D6 VDDQ 9 40 D7 Q6 10 39 CLK Q7 11 38 CLK VDDQ 12 37 GND 13 36 Q8 14 35 VREF Product Pin Description Pin Name Description RESET CLK Reset (Active Low) Clock Input CLK D Clock Input Data Input Q GND Data Output Ground VDD VDD VDDQ Core Supply Voltage Output Supply Voltage GND VREF Input Reference Voltage 15 34 RESET 16 33 D8 GND 17 32 D9 Q10 18 31 D10 Q11 19 30 D11 Q12 20 29 D12 VDDQ 21 28 VDD GND 22 27 GND Q13 23 26 D13 Q14 24 25 D14 Logic Block Diagram CLK CLK RESET D1 VREF 38 39 34 48 35 R V Q9 VDDQ CLK 1 Q1 D TO 13 OTHER CHANNELS 08-0291 1 PS8460H 11/10/08 PI74SSTV16857 14-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Truth Table(1) Inputs Outputs RESET CLK CLK D Q L X X X L H H H L L H L or H L or H X Q o(2 ) Notes: 1. H = High Signal Level 2. Output level before the L = Low Signal Level indicated steady state = Transition LOW-to-HIGH input conditions were = Transition HIGH-to-LOW established. X = Irrelevant Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Ite m Symbol/Conditions Ratings Units Tstg -65 to 150 C VDD or VDDQ -0.5 to 3.6 VI -0.5 to VDD +0.5 VO -0.5 to VDDQ +0.5 Input clamp current IIK, VI<0 -50 Output clamp current IOK, VO<0 50 IO, VO = 0 to VDDQ 50 IDD, IDDQ or IGND 100 JA 70 Storage temperature Supply voltage (1) Input voltage (1,2) Output voltage Continuous output current VDD, VDDQ or GND current/pin Package Thermal Impedance(3) V mA C/W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Notes: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This current will flow only when the output is in the high state level VO > VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51. 08-0291 2 PS8460H 11/10/08 PI74SSTV16857 14-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Recommended Operating Conditions Parame te rs M in. Nom. M ax. Supply Voltage 2. 3 2. 5 2. 7 VDDQ I/O Supply Voltage 2. 3 2.5 2.7 VREF Reference Voltage VREF = 0.5X VDDQ 1.15 1.25 1.35 VTT Termination Voltage VREF -0.04 VREF VREF +0.04 VIH DC Input High Voltage VIL DC Input Low Voltage VIH Input High Voltage VIL Input Low Voltage VIN Input Voltage Level VID Input Differential Voltage VIX Cross Point Voltage of Differential Clock Pair IO H High- Level Output Current -20 IO L Low- Level Output Current 20 TA Operating Free- Air Temperature VDD 08-0291 De s cription Data Inputs RESET CLK,CLK VREF +0.15 VDDQ +0.3 -0.3 VREF -0.15 1. 7 VDDQ +0.3 -0.3 0. 8 V -0.3 0.36 VDDQ +0.6 (VDDQ /2) -0.2 (VDDQ /2) +0.2 0 3 Units 70 PS8460H mA C 11/10/08 PI74SSTV16857 14-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics (Over the Operating Range, TA = 0C to +70C, VDD = 2.5V 200mV, VDDQ = 2.5V 200mV) Pa ra me te rs VCC M in. Typ. (1) M ax. II =-18 mA 2.3V IOH = -10 0 A 2 . 3 V- 2 . 7 V VDD-0 . 2 V IOH =-16 mA 2.3V 1.95 IOL = 10 0 A 2 . 3 V- 2 . 7 V 0.2 IOH =16 mA 2.3V 0.35 All Inp uts, VI = VDD o r GN D 2.7V 5 S tand b y (S tatic) RES ET = GN D 10 O p erating S tatic VI = VIH(AC ) o r VI (AC ), RES ET = VDD 56 Dynamic O p erating - C lo ck o nly RES ET = VDD VI = VIH (AC) o r VIL(AC), C K and C K switching 5 0 % d uty cycle Dynamic O p erating - p er each d ata inp ut RES ET = VDD VI = VIH (AC) o r VIL(AC), C K and C K switching 5 0 % d uty cycle. O ne d ata inp ut switching at half clo ck freq uency, 5 0 % d uty cycle VIK VO H VO L II IDD Te s t Co nditio ns IDDD IO = 0 -1.2 V 9 A/ clo ck MHz Data O utp ut High IOH = - 2 0 mA 2 . 3 V- 2 . 7 V 7 20 rOL O utp ut Lo w IOL = 2 0 mA 2 . 3 V- 2 . 7 V 7 20 rO( ) rOH- rOL IO = 2 0 mA, TA= 2 5 C Data inp uts VI = VREF 3 5 0 mV C K and C K VICR= 1. 2 5 V, VI(PP) = 3 6 0 mV 2.5V mA A/ clo ck MHz rOH CI A 52 2.7V 2.5V Units o hm 6 2.0 3.5 2.0 3.5 pF Notes: 4. Typical values are at VDD = Nominal VDD, TA = +25C. 08-0291 4 PS8460H 11/10/08 PI74SSTV16857 14-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) VDD =2.5V 0.2V Unit M in. fclock C lock F requency 200 tW P ulse Duration ta c t Differential inputs active time tinact O utput slew rate differential inputs inactive time(6) (5 ) S etup time, slow slew rate(8, 9) Hold time , fast slew rate(7, 9) th MHz 2.5 S etup time, fast slew rate(7, 9) tS U M ax. Hold time, slow slew rate(8, 9) 22 22 Data before C K , C K Data before C K , C K 0.75 ns 0.9 0.75 0.9 Notes: 5. Data inputs must be held low for a minimum time of tact min , after RESET is taken high 6. Data and clock inputs must be held at valid levels (not floating) for a minimum time of tinact min, after RESET is taken low. 7. Data signal input slew rate 1 V/ns 8. Data signal input slew rate 0.5V/ns and <1V/ns 9. CLK, CLK input slew rates are 1 V/ns. Switching characteristics (over recommended operating free-air temperature range, unless otherwise noted.) (See test circuits and switching waveforms). Parame te r From (Input) VDD= 2.5V 0.2V To (Output) M in. fmax Units M ax. 200 tpd CLK, CLK Q tphl RESET Q 08-0291 Typ. 1.1 MHz 2 .8 ns 5.0 5 PS8460H 11/10/08 PI74SSTV16857 14-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Test Circuit and Switching Waveforms VTT RL = 50 LVCMOS RESET Input VDD VDD/2 From Output Under Test Test Point 0V t inact CL = 30pF(8) tact IDD(9) 90% 10% IDDH Load Circuit IDDL Voltage and Current Waveforms Input Active and Inactive Times Timing Input VICR tw VIH Input VREF VREF Output VIL VICR tsu t PLH t PHL VTT VTT VREF VOH Voltage Waveforms - Propagation Delay Times LVCMOS RESET Input VI(PP) th VIH VDD/2 VIL t PHL VIH Input VI(PP) VOL Voltage Waveforms - Pulse Duration Timing Input VICR VREF Output VIL VOH VTT VOL Voltage Waveforms - Setup and Hold Times Voltage Waveforms - Propagation Delay Times Parameter Measurement Information (VDD = 2.5V 0.2V) Notes: 8. CL includes probe and jig capacitance. 9. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA. 10. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50. Input slew rate = 1V/ns 20% (unless otherwise specified). 11. The outputs are measured one at a time with one transition per measurement. 12. VTT = VREF = VDDQ/2 13. VIH = VREF + 350mV (ac voltage levels) for SSTL inputs. VIH = VDD for LVCMOS input. 14. VIL = VREF + 350mV (ac voltage levels) for SSTL inputs. VIL = GND for LVCMOS input. 15. tPLH and tPHL are the same as tpd. 08-0291 6 PS8460H 11/10/08 PI74SSTV16857 14-Bit Registered Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 48-Pin TSSOP Package (A) 48 .236 .244 1 6.0 6.2 .488 12.4 .496 12.6 .047 1.20 Max SEATING PLANE .004 0.09 .008 0.20 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS .0197 BSC 0.50 .002 .006 0.05 0.15 .007 .010 0.17 0.27 0.45 .018 0.75 .030 .319 BSC 8.1 Ordering Information Orde ring Code Package Type Ope rating Range PI74SSTV16857A 48- Pin, 240- mil TSSOP 0C to 70C PI74SSTV16857AE 48- Pin, 240- mil TSSOP (Pb- Free) 0C to 70C Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com 08-0291 7 PS8460H 11/10/08