HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Document Title 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Memory Revision History Revision No. 0.0 0.1 History Initial Draft. Draft Date Remark Sep. 2004 Preliminary 1) Correct part number ( change mode) - 2A -> 1A (sequential row read : disable -> enable) 2) Correct Table.5 & Table 12 - Correct Command Set - correct AC timing characteristics (tWP : 40 -> 25ns, tWH : 20 ->15ns) 3) Correct Summary description & page.7 - The cache feature is deleted in summary description. Oct. 22. 2004 - Note.3 is deleted. (page.7) 4) Add System interface using CE don't care (page. 38) 5) Change TSOP1, WSOP1,FBGA package dimension & figures. Preliminary - Change TSOP1, WSOP1, FBGA package mechanical data - Change TSOP1, WSOP package figures 6) Correct TSOP1, WSOP1 Pin configuration - 38th NC pin has been changed Lockpre (figure 2,3) 7) Add Bad block Management 1) LOCKPRE is changed to PRE - Texts, Table and figures are changed. 2) Change Command set - Read A,B are changed to Read1. - Read C is changed to Read2. 3) Change AC, DC characterics 0.2 - tRB, tCRY, tCEH and tOH are added. 4) Correct Program time (max) Mar. 08. 2005 Preliminary - before : 700us - after : 500us 5) Edit figures - Address names are changed. 6) Change FBGA Package Dimension - FD1 : 1.70(before) -> 0.90(after) Rev 1.3 / Jun. 2006 1 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Revision History - Continued Revision No. History Draft Date Remark Jul. 08. 2005 Preliminary Jul. 15. 2005 Preliminary 1) Change AC Characteristics (1.8V device) tRC tRP tREH tWC tWP tWH tREA before 50 25 15 50 25 15 30 after 60 40 20 60 40 20 40 2) Change AC Parameter 0.3 tCRY(3.3V) tCRY(1.8V) tOH Before 50+tr(R/B#) 50+tr(R/B#) 15 After 60+tr(R/B#) 80+tr(R/B#) 10 3) Change Figure 20,22 4) Add Read ID Table 5) Change PAD Configuration - GND is changed to VSS. 6) Add Marking Information 1) The test condition for ICC1 operating current is corrected. tCRY(3.3V) 0.4 Before tRC=50ns, CE#=VIL, IOUT=0mA tRC(1.8V=60ns, After Rev 1.3 / Jun. 2006 3.3V=50ns) CE#=VIL, IOUT=0mA 2 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Revision History - Continued Revision No. History Draft Date Remark Jul. 20. 2005 Preliminary Jul. 22. 2005 Preliminary Aug. 01. 2005 Preliminary Aug. 29. 2005 Preliminary Nov. 07. 2005 Preliminary 1) The test conditions is corrected. Test Conditions (ICC1) Test Conditions (ILI, ILO) tRC=50ns, CE#=VIL, IOUT=0mA VIN=VOUT=0 to 3.6V Before tRC(1.8V=60ns, 3.3V=50ns) CE#=VIL, IOUT=0mA After 0.5 VIN=VOUT=(1.8V, 0 to 1.95V) =(3.3V, 0 to 3.6V) 2) Change VIL parameter (max.) 1.8V 3.3V Before 0.2xVcc 0.2xVcc After 0.4 0.8 1) Correct the test Conditions (DC Characteristics table) Test Conditions (ILI, ILO) 0.6 Before VIN=VOUT=(1.8V, 0 to 1.95V) =(3.3V, 0 to 3.6V) After VIN=VOUT=0 to Vcc (max) 2) Change AC Conditions table 3) Add tWW parameter ( tWW = 100ns, min) - Texts & Figures are added. - tWW is added in AC timing characteristics table. 1) Edit Copy Back Program operation step 2) Edit System Interface Using CE don't care Figures. 3) Change AC Characteristics (3.3V device) tRP tREA before 30 35 after 25 30 0.7 4) Correct Address Cycle Map. 1) Correct PKG dimension (TSOP, USOP PKG) CP 0.8 0.9 Before 0.050 After 0.100 1) Correct USOP figure. Rev 1.3 / Jun. 2006 3 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Revision History - Continued Revision No. History Draft Date 1.0 1) Delet Preliminary. Nov. 08. 2005 1.1 1) Correct Figure 32. Feb. 06. 2006 1.2 1) Add ECC algorithm. (1bit/512bytes) 2) Correct Read ID naming 1) Change AC Parameter Remark May. 09. 2006 tWHR 1.3 Before 60 ns After 50 ns Rev 1.3 / Jun. 2006 Jun. 20. 2006 4 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash FEATURES SUMMARY HIGH DENSITY NAND Flash MEMORIES - Cost effective solutions for mass storage applications FAST BLOCK ERASE - Block erase time: 2ms (Typ.) STATUS REGISTER NAND INTERFACE - x8 or x16 bus width. - Multiplexed Address/ Data ELECTRONIC SIGNATURE - Pinout compatibility for all densities - 1st cycle : Manufacturer Code - 2nd cycle: Device Code SUPPLY VOLTAGE - 3.3V device: VCC = 2.7 to 3.6V : HY27USXX121A CHIP ENABLE DON'T CARE - Simple interface with microcontroller - 1.8V device: VCC = 1.7 to 1.95V : HY27SSXX121A Memory Cell Array AUTOMATIC PAGE 0 READ AT POWER-UP OPTION - Boot from NAND support - Automatic Memory Download = (512+16) Bytes x 32 Pages x 4,096 Blocks = (256+8) Words x 32 pages x 4,096 Blocks SERIAL NUMBER OPTION HARDWARE DATA PROTECTION PAGE SIZE - x8 device : (512 + 16 spare) Bytes : HY27(U/S)S08121A - x16 device: (256 + 8 spare) Words : HY27(U/S)S16121A BLOCK SIZE - x8 device: (16K + 512 spare) Bytes - x16 device: (8K + 256 spare) Words PAGE READ / PROGRAM - Random access: 3.3V: 12us (max.) 1.8V: 15us (max.) - Sequential access: 3.3V device: 50ns (min.) 1.8V device: 60ns (min.) - Page program time: 200us (typ.) COPY BACK PROGRAM MODE - Fast page copy without external buffering Rev 1.3 / Jun. 2006 - Program/Erase locked during Power transitions DATA INTEGRITY - 100,000 Program/Erase cycles (with 1bit/512byte ECC) - 10 years Data Retention PACKAGE - HY27(U/S)S(08/16)121A-T(P) : 48-Pin TSOP1 (12 x 20 x 1.2 mm) - HY27(U/S)S(08/16)121A-T (Lead) - HY27(U/S)S(08/16)121A-TP (Lead Free) - HY27(U/S)S(08/16)121A-S(P) : 48-Pin USOP1 (12 x 17 x 0.65 mm) - HY27(U/S)S(08/16)121A-S (Lead) - HY27(U/S)S(08/16)121A-SP (Lead Free) - HY27(U/S)S(08/16)121A-F(P) : 63-Ball FBGA (9 x 11 x 1.0 mm) - HY27(U/S)S(08/16)121A-F (Lead) - HY27(U/S)S(08/16)121A-FP (Lead Free) 5 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 1. SUMMARY DESCRIPTION The HYNIX HY27(U/S)S(08/16)121A series is a 64Mx8bit with spare 2Mx8 bit capacity. The device is offered in 1.8V Vcc Power Supply and in 3.3V Vcc Power Supply. Its NAND cell provides the most cost-effective solution for the solid state mass storage market. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. The device contains 4096 blocks, composed by 32 pages consisting in two NAND structures of 16 series connected Flash cells. A program operation allows to write the 512-byte page in typical 200us and an erase operation can be performed in typical 2ms on a 16Kbyte(X8 device) block. Data in the page mode can be read out at 50ns cycle time(3.3V device) per byte. The I/O pins serve as the ports for address and data input/output as well as command input. This interface allows a reduced pin count and easy migration towards different densities, without any rearrangement of footprint. Commands, Data and Addresses are synchronously introduced using CE, WE, ALE and CLE input pin. The on-chip Program/Erase Controller automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. The modifying can be lockde using the WP input pin. The output pin R/B (open drain buffer) signals the status of the device during each operation. In a system with multiple memories the R/B pins can be connected all together to provide a global status signal. Even the write-intensive systems can take advantage of the HY27(U/S)S(08/16)121A extended reliability of 100K program/erase cycles by providing ECC (Error Correcting Code) with real time mapping-out algorithm. The chip could be offered with the CE don't care function. This function allows the direct download of the code from the NAND Flash memory device by a microcontroller, since the CE transitions do not stop the read operation. The copy back function allows the optimization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section without the time consuming serial data insertion phase. This device includes also extra features like OTP/Unique ID area, Block Lock mechanism, Automatic Read at Power Up, Read ID2 extension. The HYNIX HY27(U/S)S(08/16)121A series is available in 48 - TSOP1 12 x 20 mm , 48 - USOP1 12 x 17 mm, FBGA 9 x 11 mm. 1.1 Product List PART NUMBER ORIZATION HY27SS08121A x8 HY27SS16121A x16 HY27US08121A x8 HY27US16121A x16 Rev 1.3 / Jun. 2006 VCC RANGE PACKAGE 1.70 - 1.95 Volt 63FBGA / 48TSOP1 / 48USOP1 2.7V - 3.6 Volt 6 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 9&& &( ,2a,2 ,2a,2 [2QO\ :( 5% 5( $/( &/( :3 35( 966 Figure1: Logic Diagram IO15 - IO8 Data Input / Outputs (x16 Only) IO7 - IO0 Data Input / Outputs CLE Command latch enable ALE Address latch enable CE Chip Enable RE Read Enable WE Write Enable WP Write Protect R/B Ready / Busy Vcc Power Supply Vss Ground NC No Connection PRE Power-On Read Enable, Lock Unlock Table 1: Signal Names Rev 1.3 / Jun. 2006 7 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9FF 9VV 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1$1')ODVK 7623 [ 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 35( 9FF 9VV 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9FF 9VV 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1$1')ODVK 7623 [ 9VV ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 1& 35( 9FF 1& 1& 1& ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 9VV Figure 2. 48TSOP1 Contactions, x8 and x16 Device 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9FF 9VV 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1$1')ODVK 8623 [ 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 35( 9FF 9VV 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9FF 9VV 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1$1')ODVK 8623 [ 9VV ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 1& 35( 9FF 1& 1& 1& ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 9VV Figure 3. 48USOP1 Contactions, x8 and x16 Device Rev 1.3 / Jun. 2006 8 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash $ 1& % 1& 1& & :3 $/( 9VV &( :( 5% ' 1& 5( &/( 1& 1& 1& ( 1& 1& 1& 1& 1& 1& ) 1& 1& 1& 1& 1& 1& * 1& 1& 1& 1& 1& 35( + 1& ,2 1& 1& 1& 9FF - 1& ,2 1& 9FF ,2 ,2 . 9VV ,2 ,2 ,2 ,2 9VV 1& 1& 1& 1& / 1& 1& 1& 1& 0 1& 1& 1& 1& Figure 4. 63FBGA Contactions, x8 Device (Top view through package) $ 1& % 1& 1& & :3 $/( 9VV &( :( 5% ' 1& 5( &/( 1& 1& 1& ( 1& 1& 1& 1& 1& 1& ) 1& 1& 1& 1& 1& 1& * 1& 1& 1& ,2 ,2 35( + ,2 ,2 ,2 ,2 ,2 9FF - ,2 ,2 ,2 9FF ,2 ,2 . 9VV ,2 ,2 ,2 ,2 9VV 1& 1& 1& 1& / 1& 1& 1& 1& 0 1& 1& 1& 1& Figure 5. 63FBGA Contactions, x16 Device (Top view through package) Rev 1.3 / Jun. 2006 9 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 1.2 PIN DESCRIPTION Pin Name IO0-IO7 IO8-IO15(1) CLE ALE CE WE RE WP R/B VCC VSS NC PRE Description DATA INPUTS/OUTPUTS The IO pins allow to input command, address and data and to output data during read / program operations. The inputs are latched on the rising edge of Write Enable (WE). The I/O buffer float to High-Z when the device is deselected or the outputs are disabled. COMMAND LATCH ENABLE This input activates the latching of the IO inputs inside the Command Register on the Rising edge of Write Enable (WE). ADDRESS LATCH ENABLE This input activates the latching of the IO inputs inside the Address Register on the Rising edge of Write Enable (WE). CHIP ENABLE This input controls the selection of the device. When the device is busy CE low does not deselect the memory. WRITE ENABLE This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise edge of WE. READ ENABLE The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE which also increments the internal column address counter by one. WRITE PROTECT The WP pin, when Low, provides an Hardware protection against undesired modify (program / erase) operations. READY BUSY The Ready/Busy output is an Open Drain pin that signals the state of the memory. SUPPLY VOLTAGE The VCC supplies the power for all the operations (Read, Write, Erase). GROUND NO CONNECTION To Enable and disable the Lock mechanism and Power On Auto Read. When PRE is a logic high, Block Lock mode and Power-On Auto-Read mode are enabled, and when PRE is a logic low, Block Lock mode and Power-On Auto-Read mode are disabled. Power-On Auto-Read mode is available only on 3.3V device. Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect it Vss or leave it NC. Table 2: Pin Description NOTE: 1. For x16 version only 2. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations. Rev 1.3 / Jun. 2006 10 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16 3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24 4th Cycle A25 (1) (1) (1) (1) (1) (1) L(1) L L L L L L Table 3: Address Cycle Map(x8) NOTE: 1. L must be set to Low. 2. A8 is set to LOW or High by the 00h or 01h Command. IO0 IO1 IO2 IO3 IO4 IO5 IO6 IO7 IO8-IO15 1st Cycle A0 A1 A2 A3 A4 A5 A6 A7 L(1) 2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16 L(1) 3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24 L(1) 4th Cycle A25 L(1) L(1) L(1) L(1) L(1) L(1) L(1) L(1) Table 4: Address Cycle Map(x16) NOTE: 1. L must be set to Low. FUNCTION 1st CYCLE 2nd CYCLE 3rd CYCLE READ 1 00h/01h - - READ 2 50h - - READ ID 90h - - RESET FFh - - PAGE PROGRAM 80h 10h - COPY BACK PGM 00h 8Ah (10h) BLOCK ERASE 60h D0h - READ STATUS REGISTER 70h - - LOCK BLOCK 2Ah LOCK TIGHT 2Ch UNLOCK (start area) 23h UNLOCK (end area) 24h READ LOCK STATUS 7Ah 4th CYCLE Acceptable command during busy Yes Yes Table 5: Command Set Rev 1.3 / Jun. 2006 11 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash CLE ALE CE WE RE WP MODE H L L Rising H X L H L Rising H X H L L Rising H H L H L Rising H H L L L Rising H H Data Input L L L(1) H Falling X Sequential Read and Data Output L L L H H X During Read (Busy) X X X X X H During Program (Busy) X X X X X H During Erase (Busy) X X X X X L Write Protect X X H X X 0V/Vcc Read Mode Write Mode Command Input Address Input(4 cycles) Command Input Address Input(4 cycles) Stand By Table 6: Mode Selection NOTE: 1. With the CE high during latency time does not stop the read operation Rev 1.3 / Jun. 2006 12 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 2. BUS OPERATION There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than 5 ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not affect bus operations. 2.1 Command Input. Command Input bus operation is used to give a command to the memory device. Command are accepted with Chip Enable low, Command Latch Enable High, Address Latch Enable low and Read Enable High and latched on the rising edge of Write Enable. Moreover for commands that starts a modifying operation (write/erase) the Write Protect pin must be high. See figure 7 and table 12 for details of the timings requirements. Command codes are always applied on IO7:0, disregarding the bus configuration (X8/X16). 2.2 Address Input. Address Input bus operation allows the insertion of the memory address. Four cycles are required to input the addresses for the 512Mbit devices. Addresses are accepted with Chip Enable low, Address Latch Enable High, Command Latch Enable low and Read Enable high and latched on the rising edge of Write Enable. Moreover for commands that starts a modify operation (write/erase) the Write Protect pin must be high. See figure 8 and table 12 for details of the timings requirements. Addresses are always applied on IO7:0, disregarding the bus configuration (X8/X16). In addition, addresses over the addressable space are disregarded even if the user sets them during command insertion. 2.3 Data Input. Data Input bus operation allows to feed to the device the data to be programmed. The data insertion is serially and timed by the Write Enable cycles. Data are accepted only with Chip Enable low, Address Latch Enable low, Command Latch Enable low, Read Enable High, and Write Protect High and latched on the rising edge of Write Enable. See figure 9 and table 12 for details of the timings requirements. 2.4 Data Output. Data Output bus operation allows to read data from the memory array and to check the status register content, the lock status and the ID data. Data can be serially shifted out toggling the Read Enable pin with Chip Enable low, Write Enable High, Address Latch Enable low, and Command Latch Enable low. See figures 10 to 14 and table 12 for details of the timings requirements. 2.5 Write Protect. Hardware Write Protection is activated when the Write Protect pin is low. In this condition modify operation do not start and the content of the memory is not altered. Write Protect pin is not latched by Write Enable to ensure the protection even during the power up. 2.6 Standby. In Standby mode the device is deselected, outputs are disabled and Power Consumption is reduced. Rev 1.3 / Jun. 2006 13 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 3. DEVICE OPERATION 3.1 Page Read. Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with followed by the four address input cycles. Once the command is latched, it does not need to be written for the following page read operation. Three types of operations are available: random read, serial page read and sequential row read. The random read mode is enabled when the page address is changed. The 528 bytes (x8 device) or 264 word (x16 device) of data within the selected page are transferred to the data registers in less than access random read time tR (12us, 3.3V device). The system controller can detect the completion of this data transfer tR (12us, 3.3V device) by analyzing the output of R/B pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing RE. High to low transitions of the RE clock output the data stating from the selected column address up to the last column address. After the data of last column address is clocked out, the next page is automatically selected for sequential row read. Waiting tR again allows reading the selected page. The sequential row read operation is terminated by bringing CE high. The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. Writing the Read2 command user may selectively access the spare area of bytes 512 to 527. Addresses A0 to A3 set the starting address of the spare area while addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential row Read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command (00h/01h) is needed to move the pointer back to the main area. Figure_11 to 13 show typical sequence and timings for each read operation. Devices with automatic read of page0 at power up can be provided on request. 3.2 Page Program. The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528 (x8 device), in a single page program cycle. The number of consecutive partial page programming operations within the same page without an intervening erase operation must not exceed 1 for main array and 2 for spare array. The addressing may be done in any random order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes (x8 device) or 264 word (x16 device) of data may be loaded into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to Figure_29. The data-loading sequence begins by inputting the Serial Data Input command (80h), followed by the four address input cycles and then serial data loading. The Page Program confirm command (10h) starts the programming process. Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal P/ E/R Controller automatically executes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle by monitoring the R/B output, or the Status bit (I/O 6) of the Status Register. Only the Read Status command and Reset command are valid while programming is in progress. When the Page Program is complete, the Write Status Bit (I/O 0) may be checked Figure_17 The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status command mode until another valid command is written to the command register. Rev 1.3 / Jun. 2006 14 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 3.3 Block Erase. The Erase operation is done on a block (16K Byte) basis. It consists of an Erase Setup command (60h), a Block address loading and an Erase Confirm Command (D0h). The Erase Confirm command (D0h) following the block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command ensures that memory contents are not accidentally erased due to external noise conditions. The block address loading is accomplished in two to four cycles depending on the device density. Only block addresses (A14 to A26) are needed while A9 to A13 is ignored. At the rising edge of WE after the erase confirm command input, the internal P/E/R Controller handles erase and erase-verify. When the erase operation is completed, the Write Status Bit (I/O 0) may be checked. Figure_18 details the sequence. 3.4 Copy-Back Program. The copy-back program is provided to quickly and efficiently rewrite data stored in one page within the plane to another page within the same plane without using an external memory. Since the time-consuming sequential-reading and its reloading cycles are removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned free block. The operation for performing a copy-back program is a sequential execution of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation with "00h" command and the address of the source page moves the whole 528byte data into the internal buffer. As soon as the device returns to Ready state, Page-Copy Data-input command (8Ah) with the address cycles of destination page followed may be written. The Program Confirm command (10h) is not needed to actually begin the programming operation. For backward-compatibility, issuing Program Confirm command during copy-back does not affect correct device operation. Copy-Back Program operation is allowed only within the same memory plane. Once the Copy-Back Program is finished, any additional partial page programming into the copied pages is prohibited before erase. Plane address must be the same between source and target page "When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if Copy-Back operations are accumulated over time, bit error due to charge loss is not checked by external error detection/correction scheme. For this reason, two bit error correction is recommended for the use of Copy-Back operation." Figure 17 shows the command sequence for the copy-back operation. The Copy Back Program operation requires three steps: - 1. The source page must be read using the Read A command (one bus write cycle to setup the command and then 4 cycle bus to input the source page address.) This operation copies all 264 Words/ 528 Bytes from the page into the page Buffer. - 2. When the device returns to the ready state (Ready/Busy High), the second bus write cycle of the command is given with the 4cycles to input the target page address. A14 & A25 must be the same for the Source and Target Pages. - 3. Then the confirm command is issued to start the P/E/R Controller. Rev 1.3 / Jun. 2006 15 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 3.5 Read Status Register. The device contains a Status Register which may be read to find out whether read, program or erase operation is com pleted, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does not need to be toggled for updated status. Refer to table 13 for specific Status Register definitions. The command register remains in Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read command (00h or 50h) should be given before sequential page read cycle. 3.6 Read ID. The device contains a product identification mode, initiated by writing 90h to the command register, followed by an address input of 00h. Two read cycles sequentially output the manufacturer code (ADh), the device code. The command register remains in Read ID mode until further commands are issued to it. Figure 19 shows the operation sequence, while tables 16 explain the byte meaning. 3.7 Reset. The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is cleared to wait for the next command, and the Status Register is cleared to value E0h when WP is high. Refer to table 12 for device status after reset operation. If the device is already in reset state a new reset command will not be accepted by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Refer to figure 25. Rev 1.3 / Jun. 2006 16 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 4. OTHER FEATURES 4.1 Data Protection & Power on/off Sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V (1.8V device), 2.0V (3.3V device). WP pin provides hardware protection and is recommended to be kept at VIL during power-up and power-down. A recovery time of minimum 10us is required before internal circuit gets ready for any command sequences as shown in Figure 26. The two-step command sequence for program/erase provides additional software protection. If the power is dropped during the ready read/write/erase operation, Power protection function may not guaranteed the data. Power protection function is only available during the power on/off sequence. 4.2 Ready/Busy. The device has a Ready/Busy output that provides method of indicating the completion of a page program, erase, copy-back and random read completion. The R/B pin is normally high and goes to low when the device is busy (after a reset, read, program, erase operation). It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy (Ibusy), an appropriate value can be obtained with the following reference chart (Fig 27). Its value can be determined by the following guidance. 4.3 Lock Block Feature In high state of PRE pin, Block lock mode and Power on Auto read are enabled, otherwise it is regarded as NAND Flash without PRE pin. Block Lock mode is enabled while PRE pin state is high, which is to offer protection features for NAND Flash data. The Block Lock mode is divided into Unlock, Lock, Lock-tight operation. Consecutive blocks protects data allows those blocks to be locked or lock-tighten with no latency. This block lock scheme offers two levels of protection. The first allows software control (command input method) of block locking that is useful for frequently changed data blocks, while the second requires hardware control (WP low pulse input method) before locking can be changed that is useful for protecting infrequently changed code blocks. The followings summarized the locking functionality. - All blocks are in a locked state on power-up. Unlock sequence can unlock the locked blocks. - The Lock-tight command locks blocks and prevents from being unlocked. Lock-tight state can be returned to lock state only by Hardware control(WP low pulse input). 1. Block lock operation 1) Lock - Command Sequence: Lock block Command (2Ah). See Fig. 20. - All blocks default to locked by power-up and Hardware control (WP low pulse input) - Partial block lock is not available; Lock block operation is based on all block unit - Unlocked blocks can be locked by using the Lock block command, and a lock block's status can be changed to unlock or lock-tight using the appropriate commands - On the program or erase operation in Locked or Lock-tighten block, Busy state holds 1~10us(tLBSY) Rev 1.3 / Jun. 2006 17 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 2) Unlock - Command Sequence: Unlock block Command (23h) + Start block address + Command (24h) + End block address. See Fig. 21. - Unlocked blocks can be programmed or erased. - An unlocked block's status can be changed to the locked or lock-tighten state using the appropriate sequence of commands. - Only one consecutive area can be released to unlock state from lock state; Unlocking multi area is not available. - Start block address must be nearer to the logical LSB (Least Significant Bit) than End block address. - One block is selected for unlocking block when Start block address is same as End block address. 3) Lock-tight - Command Sequence: Lock-tight block Command (2Ch). See Fig. 22. - Lock-tighten blocks offer the user an additional level of write protection beyond that of a regular lock block. A block that is lock-tighten can't have its state changed by software control, only by hardware control (WP low pulse input); Unlocking multi area is not available - Only locked blocks can be lock-tighten by lock-tight command. - On the program or erase operation in Locked or Lock-tighten block, Busy state holds 1~10us(tLBSY) 4) Lock Block Boundaries after Unlock Command issuing - If Start Block address = 0000h and End Block Address = FFFFh , the device is all unlocked - If Start Block address = End Block Address = FFFFh , the device is all locked except for the last Block - If Start Block address = End Block Address = 0000h , the device is all locked except for the first Block 2. Block lock Status Read Block Lock Status can be read on a block basis to find out whether designated block is available to be programmed or erased. After writing 7Ah command to the command register and block address to be checked, a read cycle outputs the content of the Block Lock Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. RE or CE does not need to be toggled for updated status. Block Lock Status Read is prohibited while the device is busy state. Refer to table 15 for specific Status Register definitions. The command register remains in Block Lock Status Read mode until further commands are issued to it. In high state of PRE pin, write protection status can be checked by Block Lock Status Read (7Ah) while in low state by Status Read (70h). 4.4 Power-On Auto-Read The device is designed to offer automatic reading of the first page without command and address input sequence during power-on. An internal voltage detector enables auto-page read functions when Vcc reaches about 1.8V. PRE pin controls activation of auto- page read function. Auto-page read function is enabled only when PRE pin is logic high state. Serial access may be done after power-on without latency. Power-On Auto Read mode is available only on 3.3V device. Rev 1.3 / Jun. 2006 18 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Parameter Symbol Min Valid Block Number NVB 4016 Typ Max Unit 4096 Blocks Table 6: Valid Blocks Number NOTE: 1. The 1st block is guaranteed to be a valid block up to 1K cycles without ECC. (1bit/512bytes) Symbol Parameter Value Unit 1.8V 3.3V 0 to 70 0 to 70 Ambient Operating Temperature (Extended Temperature Range) -25 to 85 -25 to 85 Ambient Operating Temperature (Industrial Temperature Range) -40 to 85 -40 to 85 TBIAS Temperature Under Bias -50 to 125 -50 to 125 TSTG Storage Temperature -65 to 150 -65 to 150 VIO(2) Input or Output Voltage -0.6 to 2.7 -0.6 to 4.6 V Supply Voltage -0.6 to 2.7 -0.6 to 4.6 V Ambient Operating Temperature (Commercial Temperature Range) TA Vcc Table 7: Absolute maximum ratings NOTE: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. 2. Minimum Voltage may undershoot to -2V during transition and for less than 20ns during transitions. Rev 1.3 / Jun. 2006 19 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash $a$ $''5(66 5(*,67(5 &2817(5 352*5$0 (5$6( &21752//(5 +9*(1(5$7,21 35( $/( &/( :( &( :3 5( ; 0ELW0ELW 1$1')ODVK 0(025<$55$< ' ( & 2 ' ( 5 &200$1' ,17(5)$&( /2*,& 3$*(%8))(5 &200$1' 5(*,67(5 <'(&2'(5 '$7$ 5(*,67(5 %8))(56 ,2 Figure 6: Block Diagram Rev 1.3 / Jun. 2006 20 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Parameter Symbol Test Conditions Sequential Read ICC1 Program Erase 1.8Volt 3.3Volt Unit Min Typ Max Min Typ Max tRC(1.8V=60ns, 3.3V=50ns) CE=VIL, IOUT=0mA - 8 15 - 10 20 mA ICC2 - - 8 15 - 10 20 mA ICC3 - - 8 15 - 10 20 mA Stand-by Current (TTL) ICC4 CE=VIH, WP=PRE=0V/Vcc - - 1 - 1 mA Stand-by Current (CMOS) ICC5 CE=Vcc-0.2, WP=PRE=0V/Vcc - 10 50 - 10 50 uA Input Leakage Current ILI VIN=0 to Vcc (max) - - 10 - - 10 uA Output Leakage Current ILO VOUT =0 to Vcc (max) - - 10 - - 10 uA Input High Voltage VIH - Vcc-0.4 - Vcc+0. 3 2 - Vcc+0 .3 V Input Low Voltage VIL - -0.3 - 0.4 -0.3 - 0.8 V Output High Voltage Level VOH IOH=-100uA Vcc-0.1 - - - - - V IOH=-400uA - - - 2.4 - - V Output Low Voltage Level VOL IOL=100uA - - 0.1 - - - V IOL=2.1mA - - - - - 0.4 V Output Low Current (R/B) IOL (R/B) VOL=0.2V 3 4 - - - - mA VOL=0.4V - - - 8 10 - mA Operating Current Table 8: DC and Operating Characteristics Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load (1.7V - 1.95Volt & 2.7V - 3.3V) Value 1.8Volt 3.3Volt 0V to Vcc 0.4V to 2.4V 5ns 5ns Vcc / 2 1.5V 1 TTL GATE and CL=30pF 1 TTL GATE and CL=50pF Output Load (3.0V - 3.6V) 1 TTL GATE and CL=100pF Table 9: AC Conditions Rev 1.3 / Jun. 2006 21 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Item Symbol Test Condition Min Max Unit Input / Output Capacitance CI/O VIL=0V - 10 pF Input Capacitance CIN VIN=0V - 10 pF Table 10: Pin Capacitance (TA=25C, F=1.0MHz) Parameter Symbol Min Typ Max Unit Program Time tPROG - 200 500 us Dummy Busy Time for the Lock or Lock-tight Block tLBSY - 5 10 us Main Array NOP - - 1 Cycles Spare Array NOP - - 2 Cycles tBERS - 2 3 ms Number of partial Program Cycles in the same page Block Erase Time Table 11: Program / Erase Characteristics Rev 1.3 / Jun. 2006 22 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Parameter Symbol 1.8Volt Min 3.3Volt Max Min Unit Max CLE Setup time tCLS 0 0 ns CLE Hold time tCLH 10 10 ns CE setup time tCS 0 0 ns CE hold time tCH 10 10 ns WE pulse width tWP 40 25 ns (1) ALE setup time tALS 0 0 ns ALE hold time tALH 10 10 ns Data setup time tDS 20 20 ns Data hold time tDH 10 10 ns Write Cycle time tWC 60 50 ns WE High hold time tWH 20 15 ns 15 12 us Data Transfer from Cell to register tR ALE to RE Delay tAR 10 10 ns CLE to RE Delay tCLR 10 10 ns Ready to RE Low tRR 20 20 ns RE Pulse Width tRP 40 25 ns WE High to Busy tWB 100 60 100 ns 50 ns Read Cycle Time tRC RE Access Time tREA 40 30 ns RE High to Output High Z tRHZ 30 30 ns CE High to Output High Z tCHZ 20 20 ns RE or CE high to Output hold tOH 10 10 ns RE High Hold Time tREH 20 15 ns tIR 0 0 ns Output High Z to RE low CE Access Time tCEA WE High to RE low tWHR Last RE High to busy (at sequential read) tRB CE High to Ready (in case of interception by CE at read) tCRY CE High Hold Time (at the last serial read) tCEH Device Resetting Time (Read / Program / Erase) tRST (3) tWW(5) Write Protection time 45 45 50 ns 50 100 80+tr(R/B#) ns 100 (4) 100 ns (4) 60+tr(R/B#) 100 5/10/500(2) 100 ns 5/10/500(2) 100 ns us ns Table 12: AC Timing Characteristics NOTE: 1. If tCS is less than 10ns tWP must be minimum 35ns, otherwise, tWP may be minimum 25ns. 2. If Reset Command (FFh) is written at Ready state, the device goes into Busy for maximum 5us 3. To break the sequential read cycle, CE must be held for longer time than tCEH. 4. The time to Ready depends on the value of the pull-up resistor tied R/B pin. 5. Program / Erase Enable Operation : WP high to WE High. Program / Erase Disable Operation : WP Low to WE High. Rev 1.3 / Jun. 2006 23 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash IO Pagae Program Block Erase Read CODING 0 Pass / Fail Pass / Fail NA Pass: `0' Fail: `1' 1 NA NA NA Pass: `0' Fail: `1' (Only for Cache Program, else Don't care) 2 NA NA NA - 3 NA NA NA - 4 NA NA NA - 5 Ready/Busy Ready/Busy Ready/Busy Active: `0' Idle: `1' 6 Ready/Busy Ready/Busy Ready/Busy Busy: `0' Ready': `1' 7 Write Protect Write Protect Write Protect Protected: `0' Not Protected: `1' Table 13: Status Register Coding DEVICE IDENTIFIER CYCLE DESCRIPTION 1st Manufacturer Code 2nd Device Identifier Table 14: Device Identifier Coding Part Number Voltage Bus Width 1st cycle (Manufacture Code) 2nd cycle (Device Code) HY27US08121A 3.3V X8 ADh 76h HY27US16121A 3.3V X16 ADh 56h HY27SS08121A 1.8V X8 ADh 36h HY27SS16121A 1.8V X16 ADh 46h Table 15: Read ID Table Rev 1.3 / Jun. 2006 24 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Table 16: Lock Status Code &/( W&/6 W&/+ W&6 W&+ &( W:3 :( W$/6 W$/+ $/( W'6 ,2a W'+ &RPPDQG Figure 7: Command Latch Cycle Rev 1.3 / Jun. 2006 25 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash W&/6 &/( W&6 W:& W:& W:& &( W:3 :( W$/6 W:3 W:+ W$/+ W$/+ W:3 W:+ W$/+ W$/+ W:3 W:+ W$/+ W$/+ W$/+ $/( ,2[ W'+ W'6 W'+ W'6 &RO$GG 5RZ$GG W'6 W'+ W'6 W'+ 5RZ$GG 5RZ$GG Figure 8: Address Latch Cycle Rev 1.3 / Jun. 2006 26 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash W&/+ &/( W&+ &( W$/6 W:& $/( W:3 W:3 :( W:3 W:+ W:+ W'6 ,2[ W'+ W'6 ',1 W'+ W'6 ',1 W'+ ',1ILQDO Figure 9. Input Data Latch Cycle tCEA CE tREA tREH tRP tCHZ* tREA tREA tOH RE tRHZ tRHZ* tOH I/Ox Dout tRR Dout Dout tRC R/B Notes : Transition is measured 200mV from steady state voltage with load. This parameter is sampled and not 100% tested. Figure 10: Sequential Out Cycle after Read (CLE=L, WE=H, ALE=L) Rev 1.3 / Jun. 2006 27 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash W&/5 &/( W&/6 W&/+ W&6 &( W&+ W:3 :( W&($ W&+= W:+5 5( W'+ W'6 ,2[ W5($ W,5 W5+= 6WDWXV2XWSXW K Figure 11: Status Read Cycle &/( W&(+ &( W&+= W:& :( W:% W&5< W$5 $/( W5+= W5 W5& 5( W53 ,2[ KRUK &RO$GG &ROXPQ $GGUHVV 5% 5RZ$GG 5RZ$GG 5RZ$GG 'RXW1 'RXW1 'RXW1 'RXW W5% 3DJH 5RZ $GGUHVV %XV\ Figure 12: Read1 Operation (Read One Page) Rev 1.3 / Jun. 2006 28 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash &/( &( :( W:% W&+= W$5 $/( W5 W5& 5( W55 ,2[ KRUK &RO$GG 5RZ$GG 5RZ$GG 5RZ$GG &RO$GG 'RXW1 'RXW1 'RXW1 5RZ$GG 5% %XV\ Figure 13: Read1 Operation intercepted by CE &/( &/( &( &( :( :( W5 W5 W:% W:% $/( $/( W$5 W$5 W55 W55 5( 5( ,2[ ,2[ K K &RO$GG &RO$GG 5% 5% 'RXW 'RXW 0 0 &RO$GG &RO$GG 5RZ$GG 5RZ$GG 5RZ$GG 5RZ$GG5RZ$GG 5RZ$GG 'RXW 'RXW 5RZ$GG 5RZ$GG 0$GGUHVV 0$GGUHVV $$9DOLG$GGUHVV $$9DOLG$GGUHVV $$'RQWFDUH $$'RQWFDUH 6HOHFWHG 6HOHFWHG 5RZ 5RZ 6WDUW 6WDUW $GGUHVV0 $GGUHVV0 Figure 14: Read2 Operation (Read One Page) Rev 1.3 / Jun. 2006 29 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash &/( &( :( $/( 5( ,2[ K 'RXW 1 &RO$GG 5RZ$GG 5RZ$GG 5RZ$GG 'RXW 1 'RXW 'RXW 'RXW 'RXW 5HDG\ 5% %XV\ 0 %XV\ 0 1 2XWSXW 2XWSXW Figure 15: Sequential Row Read Operation Within a Block Rev 1.3 / Jun. 2006 30 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash &/( &( W:& W:& W:& :( W:% W352* $/( 5( ,2[ K 6HULDO'DWD ,QSXW&RPPDQG &RO$GG 5RZ$GG 5RZ$GG 5RZ$GG &ROXPQ $GGUHVV 5RZ$GGUHVV 'LQ 1 'LQ 0 XSWR%\WH 6HULDO,QSXW K 3URJUDP &RPPDQG K ,2R 5HDG6WDWXV &RPPDQG 5% ,2R 6XFFHVVIXO3URJUDP ,2R (UURULQ3URJUDP Figure 16: Page Program Operation Rev 1.3 / Jun. 2006 31 Rev 1.3 / Jun. 2006 5% ,2[ 5( $/( :( &( &/( K W:& &ROPQ $GGUHVV 5RZ$GGUHVV &RO$GG 5RZ$GG 5RZ$GG 5RZ$GG W:% %XV\ W5 &ROPQ $GGUHVV 5RZ$GGUHVV ,2 ,2 (UURULQ3URJUDP 5HDG6WDWXV &RPPDQG K %XV\ ,2 6XFFHVVIXO3URJUDP KZULWHF\FOHQRPRUH &RO$GG 5RZ$GG 5RZ$GG 5RZ$GG &RS\%DFN'DWD ,QSXW&RPPDQG $K W352* HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Figure 17 : Copy Back Program 32 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash &/( &( W:& :( W:% W%(56 $/( 5( ,2[ K 5RZ$GG 5RZ$GG 5RZ$GG 'K K ,2 3DJH 5RZ $GGUHVV 5% %86< $XWR%ORFN(UDVH6HWXS&RPPDQG 5HDG6WDWXV &RPPDQG (UDVH&RPPDQG ,2 6XFFHVVIXO(UDVH ,2 (UURULQ(UDVH Figure 18: Block Erase Operation (Erase One Block) CLE CE WE tAR ALE RE tREA 90h 00h Read ID Command Address 1 cycle I/O x ADh 76h Maker Code Device Code Figure 19: Read ID Operation Rev 1.3 / Jun. 2006 33 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash :3 &/( &( :( ,2[ $K /RFN&RPPDQG Figure 20: Lock Command :3 &/( &( :( $/( ,2[ K 8QRFN&RPPDQG $GG $GG $GG 6WDUW%ORFN$GGUHVVF\FOHV K 8QORFN&RPPDQG $GG $GG $GG (QG%ORFN$GGUHVVF\FOHV Figure 21: Unlock Command Sequence Rev 1.3 / Jun. 2006 34 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash :3 &/( &( :( ,2[ &K /RFNWLJKW&RPPDQG Figure 22: Lock Tight Command :3 &/( &( :( $/( W:+5 5( ,2[ $K 5HDG%ORFN/RFN VWDWXV&RPPDQG $GG $GG $GG %ORFN$GGUHVVF\FOH 'RXW %ORFN/RFN6WDWXV Figure 23: Lock Status Read Timing Rev 1.3 / Jun. 2006 35 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 1.8V Vcc WE CE ALE CLE tR R/B PRE RE I/Ox Data1 Data2 Data3 Last Data Data Output Figure 24: Automatic Read at Power On :( $/( &/( 5( ,2 ))K W567 5% Figure 25: Reset Operation Rev 1.3 / Jun. 2006 36 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 9FF 97+ W :3 :( XV Figure 26: Power On/Off Timing VTH = 1.5 Volt for 1.8 Volt Supply devices; 2.5 Volt for 3.3 Volt Supply devices Rev 1.3 / Jun. 2006 37 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash 5S LEXV\ 9FF 5HDG\ 9FF 5% RSHQGUDLQRXWSXW 9 9 %XV\ WI WU *1' 'HYLFH )LJ5SYVWUWI 5SYVLEXV\ #9FF 97D &&/ S) LEXV\ Q Q Q P P WI N N N N LEXV\>$@ WUWI>V@ P 5S RKP 5SYDOXHJXLGHQFH 5S PLQ 9FF 0D[ 92/ 0D[ 9 ,2/,/ P$,/ ZKHUH,/LVWKHVXPRIWKHLQSXWFXUUQWVRIDOOGHYLFHVWLHGWRWKH5%SLQ 5S PD[ LVGHWHUPLQHGE\PD[LPXPSHUPLVVLEOHOLPLWRIWU Figure 27: Ready/Busy Pin electrical specifications Rev 1.3 / Jun. 2006 38 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Figure 28: Lock/Unlock FSM Flow Cart ['HYLFHV ['HYLFHV $UHD$ K $UHD% K $UHD& K $UHD$ K $UHD& K %\WHV %\WHV %\WHV %\WHV %\WHV $ % & $ & 3DJH%XIIHU 3DJH%XIIHU 3RLQWHU KK 3RLQWHU KKK Figure 29: Pointer operations Rev 1.3 / Jun. 2006 39 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash $5($$ ,2 K K $GGUHVV ,QSXWV 'DWD,QSXW K K K $GGUHVV ,QSXWV 'DWD,QSXW K $UHDV$%&FDQEHSURJUDPPHGGHSHQGLQJRQKRZPXFKGDWDLVLQSXW6XEVHTXHQWKFRPPDQGVFDQEHRPLWWHG $5($% ,2 K K $GGUHVV ,QSXWV 'DWD,QSXW K K K $GGUHVV ,QSXWV 'DWD,QSXW K $UHDV%&FDQEHSURJUDPPHGGHSHQGLQJRQKRZPXFKGDWDLVLQSXW7KHKFRPPDQGPXVWEHUHLVVXHGEHIRUHHDFKSURJUDP $5($& ,2 K K $GGUHVV ,QSXWV 'DWD,QSXW K K K $GGUHVV ,QSXWV 'DWD,QSXW K 2QO\$UHDV&FDQEHSURJUDPPHG6XEVHTXHQWKFRPPDQGFDQEHRPLWWHG Figure 30: Pointer Operations for porgramming Rev 1.3 / Jun. 2006 40 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash System Interface Using CE don't care To simplify system interface, CE may be inactive during data loading or sequential data-reading as shown below. So, it is possible to connect NAND Flash to a microprocessor. The only function that was removed from standard NAND Flash to make CE don't care read operation was disabling of the automatic sequential read function. &/( &(GRQWFDUH &( :( $/( ,2[ K 6WDUW$GG &\FOH 'DWD,QSXW 'DWD,QSXW K Figure 31: Program Operation with CE don't-care. &/( ,IVHTXHQWLDOURZUHDGHQDEOHG &(PXVWEHKHOGORZGXULQJW5 &(GRQWFDUH &( 5( $/( 5% W5 :( ,2[ K 6WDUW$GG &\FOH 'DWD2XWSXW VHTXHQWLDO Figure 32: Read Operation with CE don't-care. Rev 1.3 / Jun. 2006 41 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Bad Block Management Devices with Bad Blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transistor. The devices are supplied with all the locations inside valid blocks erased(FFh). The Bad Block Information is written prior to shipping. Any block where the 6th Byte/ 3rd Word in the spare area of the 1st or 2nd page (if the 1st page is Bad) does not contain FFh is a Bad Block. The Bad Block Information must be read before any erase is attempted as the Bad Block Information may be erased. For the system to be able to recognize the Bad Blocks based on the original information it is recommended to create a Bad Block table following the flowchart shown in Figure 20. The 1st block, which is placed on 00h block address is guaranteed to be a valid block. Block Replacement Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying the data to a valid block. These additional Bad Blocks can be identified as attempts to program or erase them will give errors in the Status Register. As the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by re-programming the current data and copying the rest of the replaced block to an available valid block. The Copy Back Program command can be used to copy the data to a valid block. See the "Copy Back Program" section for more details. Refer to Table 17 for the recommended procedure to follow if an error occurs during an operation. Operation Recommended Procedure Erase Block Replacement Program Block Replacement or ECC (with 1bit/512byte) Read ECC (with 1bit/512byte) Table 17: Block Failure 67$57 %ORFN$GGUHVV %ORFN ,QFUHPHQW %ORFN$GGUHVV 'DWD ))K" 1R 8SGDWH %DG%ORFNWDEOH <HV /DVW EORFN" 1R <HV (1' Figure 33: Bad Block Management Flowchart Rev 1.3 / Jun. 2006 42 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Write Protect Operation The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 34~37) :( W :: ,2[ K K :3 5% Figure 34: Enable Programming :( W :: ,2[ K K :3 5% Figure 35: Disable Programming Rev 1.3 / Jun. 2006 43 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash :( W :: ,2[ K 'K :3 5% Figure 36: Enable Erasing :( W :: ,2[ K 'K :3 5% Figure 37: Disable Erasing Rev 1.3 / Jun. 2006 44 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash H ' $ $ % $ / ',( ( ( & &3 Figure 38: 48-pin TSOP1, 12 x 20mm, Package Outline millimeters Symbol Min Typ A Max 1.200 A1 0.050 0.150 A2 0.980 1.030 B 0.170 0.250 C 0.100 0.200 CP 0.100 D 11.910 12.000 12.120 E 19.900 20.000 20.100 E1 18.300 18.400 18.500 e 0.500 L 0.500 0.680 alpha 0 5 Table 18: 48-pin TSOP1, 12 x 20mm, Package Mechanical Data Rev 1.3 / Jun. 2006 45 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash $QJOH DOSKD H ' % $ $ ( & $ ' &3 & Figure 39. 48-pin USOP1, 12 x 17mm, Package Outline Symbol millimeters Min Typ A Max 0.650 A1 0 0.050 A2 0.470 0.520 0.080 0.570 B 0.130 0.160 0.230 C 0.065 0.100 0.175 C1 0.450 0.650 0.750 D 16.900 17.000 17.100 D1 11.910 12.000 12.120 E 15.300 15.400 15.500 CP 0.100 e alpha 0.500 0 8 Table 19: 48-pin USOP1, 12 x 17mm, Package Mechanical Data Rev 1.3 / Jun. 2006 46 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash ' ' ' )' 6' )' H H ( 6( ( ( )( )( %$//FS $ H E $ $ Figure 40. 63-ball FBGA - 9 x 11 ball array 0.8mm pitch, Pakage Outline NOTE: Drawing is not to scale. Symbol A A1 A2 b D D1 D2 E E1 E2 e FD FD1 FE FE1 SD SE Millimeters Min 0.80 0.25 0.55 0.40 8.90 10.90 Typ 0.90 0.30 0.60 0.45 9.00 4.00 7.20 11.00 5.60 8.80 0.80 2.50 0.90 2.70 1.10 0.40 0.40 Max 1.00 0.35 0.65 0.50 9.10 11.10 Table 20: 63-ball FBGA - 9 x 11 ball array 0.8mm pitch, Pakage Mechanical Data Rev 1.3 / Jun. 2006 47 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash MARKING INFORMATION - TSOP1/USOP Packag TSOP1 / USOP M a r k in g E x a m p le H Y 2 7 x x x x x S - h y n ix : H y n ix S y m b o l - KOR : O r ig in C o u n tr y - H Y27xSxx12xA xxxx : P a rt N u m b e r x K O R x 1 2 X A Y W W x x H Y : H Y N IX 2 7 : N A N D F la s h x : P o w e r S u p p ly : U ( 2 .7 V ~ 3 .6 V ) , L ( 2 .7 V ) , S ( 1 .8 V ) S : C la s s ific a tio n : S in g le L e v e l C e ll+ S in g le D ie + S m a ll B lo c k x x : B it O r g a n iz a tio n : 0 8 (x8 ), 1 6 (x1 6 ) 1 2 : D e n s ity : 5 1 2 M b it x: M ode : 1 ( 1 n C E & 1 R / n B ; S e q u e n tia l R o w R e a d e n a b le ) 2 ( 1 n C E & 1 R / n B ; S e q u e n tia l R o w R e a d D is a b le ) A : V e r s io n : 2 n d G e n e r a tio n x : Package T ype : T (4 8 -T S O P 1 ), S (4 8 -U S O P ) x : P a c k a g e M a te r ia l : B la n k ( N o r m a l) , P ( L e a d F r e e ) x : O p e r a tin g T e m p e r a tu r e : C (0 ~ 7 0 ), E (-2 5 ~ 8 5 ) M (-3 0 ~ 8 5 ), I(-4 0 ~ 8 5 ) x : B a d B lo c k : B ( I n c lu d e d B a d B lo c k ) , S ( 1 ~ 5 B a d B lo c k ) , P ( A ll G o o d B lo c k ) - Y : Y e a r (e x: 5 = ye a r 2 0 0 5 , 0 6 = ye a r 2 0 0 6 ) - w w : W o rk W e e k (e x : 1 2 = w o rk w e e k 1 2 ) - x x : P ro c e ss C o d e N o te - C a p it a l L e t t e r : F ix e d I te m - S m a ll L e t t e r : N o n - fix e d I te m Rev 1.3 / Jun. 2006 48 HY27US(08/16)121A Series HY27SS(08/16)121A Series 512Mbit (64Mx8bit / 32Mx16bit) NAND Flash MARKING INFORMATION - FBGA P a ck a g FBGA M a rk in g E x a m p le H Y 2 7 x x x x x S - h y n ix : H y n ix S y m b o l - KOR : O rig in C o u n try - H Y27xSxx12xA xxxx : P a rt N u m b er x K O R x 1 2 x A Y W W x x H Y : H Y N IX 2 7 : N A N D F lash x : P o w e r S u p p ly : U (2 .7 V ~ 3 .6 V ), L (2 .7 V ), S (1 .8 V ) S : C la ssifica tio n : S in g le Le v el C ell+ S in g le D ie+ S m all B lo ck x x : B it O rg an izatio n : 0 8 (x 8 ), 1 6 (x1 6 ) 1 2 : D e n sity : 5 1 2 M b it x: M ode : 1 (1 n C E & 1 R /n B ; S e q u e n tia l R o w R ea d E n a b le ) 2 (1 n C E & 1 R /n B ; S e q u e n tial R o w R e a d D isa b le ) A : V e rsio n : 2 n d G e n eration x : P acka g e T yp e : F (6 3 F B G A ) x : P acka g e M a te ria l : B lan k (N o rm a l), P (Le a d Free ) x : O p e ra tin g T e m p eratu re : C (0 ~ 7 0 ), E (-2 5 ~ 8 5 ) M (-3 0 ~ 8 5 ), I(-4 0 ~ 8 5 ) x : B a d B lo ck : B (In clu d e d B a d B lo ck ), S (1 ~ 5 B a d B lo ck ), P (A ll G o o d B lo ck ) - Y : Y e a r (e x: 5 = y ea r 2 0 0 5 , 0 6 = y ea r 2 0 0 6 ) - w w : W o rk W e ek (e x : 1 2 = w o rk w e e k 1 2 ) - x x : P ro ce ss C o d e N o te - C a p ita l L e tte r : F ixed Item - S m a ll L e tte r : N o n -fixe d Ite m Rev 1.3 / Jun. 2006 49