Integrated Device Technology, Inc.
MILITARY TEMPERATURE RANGE AUGUST 1996
1996 Integrated Device Technology, Inc. 2986/7
For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
• High speed (equal access and cycle time)
— Military: 25/35/45/55/70/85ns (max.)
• Low power consumption
• Battery backup operation—2V data retention (L version
only)
• JEDEC standard high-density 22-pin ceramic DIP, 22-pin
leadless chip carrier
• Produced with advanced CMOS high-performance
technology
• Separate data input and output
• Input and output directly TTL-compatible
• Military product compliant to MIL-STD-883, Class B
DESCRIPTION:
The IDT7187 is a 65,536-bit high-speed static RAM
organized as 64K x 1. It is fabricated using IDT’s high-
performance, high-reliability CMOS technology. Access times
as fast as 25ns are available.
Both the standard (S) and low-power (L) versions of the
IDT7187 provide two standby modes—ISB and ISB1. ISB
provides low-power operation; ISB1 provides ultra-low-power
operation. The low-power (L) version also provides the capa-
bility for data retention using battery backup. When using a 2V
battery, the circuit typically consumes only 30µW.
Ease of system design is achieved by the IDT7187 with full
asynchronous operation, along with matching access and
cycle times. The device is packaged in an industry standard
22-pin, 300 mil ceramic DIP, or 22-pin leadless chip carriers.
Military grade product is manufactured in compliance with
the latest revision of MIL-STD-883, Class B, making it ideally
suited to military temperature applications demanding the
highest level of performance and reliability.
FUNCTIONAL BLOCK DIAGRAM
ROW
SELECT 65,536-BIT
MEMORY ARRAY
COLUMN I/O
2986 drw 01
WE
CS
V
CC
GND
DATA
OUT
A
A
A
A
A
A
A
AAAAAAA
DATA
IN
6.2 1
CMOS STATIC RAM
64K (64K x 1-BIT) IDT7187S
IDT7187L
6.2 2
IDT7187S/L
CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE
PIN CONFIGURATIONS
2986 drw 02
5
6
7
8
9
10
11
1
2
3
4
22
21
20
19
18
17
D22-1
A0
A1
A2
A3
A4
A5
A6
A7
VCC
A15
A13
A12
16
15
GND CS
14
A14
WE
DATAOUT
A11
13
12
A10
A9
A8
DATAIN
DIP
TOP VIEW 22-PIN LCC
TOP VIEW
5
6
7
8
9
L22-1
20
19
18
17
10 11 12 13
2122 21
INDEX
A4
VCC
GND
WE
A14
A13
A12
16
15
A2
A3
A0
2986 drw 03
A5
A6
14
A11
A10
A7
4
DATAOUT A9
A8
A15
DATAIN
CS
3
A1
TRUTH TABLE(1)
Mode
CS
CS WE
WE
Output Power
Standby H X High-Z Standby
Read L H DOUT Active
Write L L High-Z Active
NOTE: 2986 tbl 02
1. H = VIH, L = VIL, X = don't care.
PIN DESCRIPTIONS
Name Description
A0–A15 Address Inputs
CS
Chip Select
WE
Write Enable
VCC Power
DATAIN Data Input
DATAOUT Data Output
GND Ground 2986 tbl 01
6.2 3
IDT7187S/L
CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE
CAPACITANCE (TA = +25°C, F = 1.0MHZ)
Symbol Parameter(1) Conditions Max. Unit
CIN Input Capacitance VIN = 0V 8 pF
COUT Output Capacitance VOUT = 0V 8 pF
NOTE: 2986 tbl 04
1. This parameter is determined by device characterization, but is not
production tested.
RECOMMENDED DC OPERATING
CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5 V
GND Supply Voltage 0 0 0 V
VIH Input High Voltage 2.2 — 6.0 V
VIL Input Low Voltage –0.5(1) — 0.8 V
NOTE: 2986 tbl 05
1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade Temperature GND VCC
Military –55°C to +125°C 0V 5V ± 10%
Commercial 0°C to +70°C 0V 5V ± 10%
2986 tbl 06
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Com’l. Mil. Unit
VTERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V
with Respect
to GND
TAOperating 0 to +70 –55 to +125 °C
Temperature
TBIAS Temperature –55 to +125 –65 to +135 °C
Under Bias
TSTG Storage –55 to +125 –65 to +150 °C
Temperature
PTPower Dissipation 1.0 1.0 W
IOUT DC Output 50 50 mA
Current
NOTE: 2986 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ± 10%) IDT7187S IDT7187L
Symbol Parameter Test Condition Min. Max. Min. Max. Unit
|ILI| Input Leakage Current VCC = Max., MIL. — 10 — 5 µA
VIN = GND to VCC COM’L. — 5 — 2
|ILO| Output Leakage Current VCC = Max.,
CS
= VIH, MIL. — 10 — 5 µA
VOUT = GND to VCC COM’L. — 5 — 2
VOL Output Low Voltage IOL = 10mA, VCC = Min. 0.5 — 0.5 V
IOL = 8mA, VCC = Min. — 0.4 — 0.4
VOH Output High Voltage IOH = –4mA, VCC = Min. 2.4 — 2.4 — V
2986 tbl 07
6.2 4
IDT7187S/L
CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L Version Only) VHC = VCC - 0.2V, VLC = 0.2V Typ. (1) Max.
VCC @VCC @
Symbol Parameter Test Condition Min. 2.0v 3.0V 2.0V 3.0V Unit
VDR VCC for Data Retention — 2.0 — — — — V
ICCDR Data Retention Current MIL. — 10 15 600 900 µA
COM’L. — 10 15 150 225
tCDR(3) Chip Deselect to Data
CS
≥ VHC 0————ns
Retention Time VIN ≥ VHC or ≤ VLC
tR(3) Operation Recovery Time tRC(2) ————ns
|ILI|(3) Input Leakage Current — — — 2 2 µA
NOTES: 2986 tbl 09
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed, but not tested.
LOW VCC DATA RETENTION WAVEFORM
2986 drw 04
DATA
RETENTION
MODE
4.5V 4.5V
VDR ≥2V
VIH VIH
tR
tCDR
VCC
CS
VDR
DC ELECTRICAL CHARACTERISTICS(1)
(VCC = 5V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
7187S25 7187S35 7187S45 7187S55/70 7187S85
7187L25 7187L35 7187L45 7187L55/70 7187L85
Symbol Parameter Power Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil. Com’l. Mil. Unit
ICC1 Operating Power S — 105 — 105 — 105 — 105 — 105 mA
Supply Current
CS
= VIL, Outputs Open L — 85 — 85 — 85 — 85 — 85
VCC = Max., f = 0(2)
ICC2 Dynamic Operating S — 130 — 120 — 120 — 120 — 120 mA
Current
CS
= VIL, Outputs Open L — 110 — 100 — 95 — 90 — 90
VCC = Max., f = fMAX(2)
ISB Standby Power Supply S — 55 — 50 — 50 — 50 — 50 mA
Current (TTL Level)
CS
≥ VIH, VCC = Max., L — 50 — 40 — 35 — 30/28 — 28
Outputs Open, f = fMAX(2)
ISB1 Full Standby Power S — 20 — 20 — 20 — 20 — 20 mA
Supply Current (CMOS
Level)
CS
≥ VHC, L — 1.5 — 1.5 — 1.5 — 1.5 — 1.5
VCC=Max., VIN ≥ VHC or
VIN ≤ VLC, f = 0(2)
NOTES: 2986 tbl 08
1. All values are maximum guaranteed values.
2. At f = fMAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change.
6.2 5
IDT7187S/L
CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
AC Test Load See Figures 1 and 2
2986 tbl 10
Figure 1. AC Test Load Figure 2. AC Test Load
(for tHZ, tLZ, tWZ and tOW)
*Includes scope and jig capacitances
2986 drw 05
480
Ω
30pF*
255
Ω
DATA
OUT
5V
2986 drw 06
480Ω
5pF*
255Ω
DATAOUT
5V
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
7187S25 7187S35/45(1) 7187S55(1) 7187S70(1) 7187S85(1)
7187L25 7187L35/45(1) 7187L55(1) 7187L70(1) 7187L85(1)
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tRC Read Cycle Time 25 — 35/45 — 55 — 70 — 85 — ns
tAA Address Access Time — 25 — 35/45 — 55 — 70 — 85 ns
tACS Chip Select Access Time — 25 — 35/45 — 55 — 70 — 85 ns
tOH Output Hold from Address Change 5 — 5 — 5 — 5 — 5 — ns
tLZ(2) Output Selection to Output in Low-Z 5 — 5 — 5 — 5 — 5 — ns
tHZ(2) Chip Deselect to Output in High-Z — 12 — 17/20 — 30 — 30 — 40 ns
tPU(2) Chip Select to Power-Up Time 0 — 0 — 0 — 0 — 0 — ns
tPD(2) Chip Deselect to Power-Down Time — 20 — 30/35 — 35 — 35 — 40 ns
NOTES: 2986 tbl 11
1. –55°C to +125°C temperature range only.
2. This parameter guaranteed but not tested.
6.2 6
IDT7187S/L
CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE
TIMING WAVEFORM OF READ CYCLE NO. 1(1,2)
TIMING WAVEFORM OF READ CYCLE NO. 2(1,3)
NOTES:
1.
WE
is HIGH for Read cycle.
2.
CS
is LOW for Read cycle.
3. Address valid prior to or coincident with
CS
transition LOW.
4. Transition is measured ±200mV from steady state voltage with specified loading in Figure 2.
5. All Read cycle timings are referenced from the last valid address to the first transitioning address.
2986 drw 07
ADDRESS
DATA
tRC
tAA
OUT
tOH
PREVIOUS DATA VALID DATA VALID
(5)
2986 drw 08
DATAOUT
CS
tACS
(4)
tLZ
(4)
HZ
t
tPD
tPU
ICC
ISB
SUPPLY
CURRENT
VCC
tRC (5)
HIGH
IMPEDANCE
DATA VALID
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, All Temperature Ranges)
7187S25 7187S35/45(1) 7187S55(1) 7187S70(1) 7187S85(1)
7187L25 7187L35/45(1) 7187L55(1) 7187L70(1) 7187L85(1)
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Write Cycle
tWC Write Cycle Time 25 — 35/45 — 55 — 70 — 85 — ns
tCW Chip Select to End-of-Write 20 — 25/40 — 50 — 55 — 65 — ns
tAW Address Valid to End-of-Write 20 — 25/40 — 50 — 55 — 65 — ns
tAS Address Set-up Time 0 — 0 — 0 — 0 — 0 — ns
tWP Write Pulse Width 20 — 20/25 — 35 — 40 — 45 — ns
tWR Write Recovery Time 0 — 0 — 0 — 0 — 0 — ns
tDW Data Valid to End-of-Write 15 — 15/25 — 25 — 30 — 35 — ns
tDH Data Hold Time 5 — 5 — 5 — 5 — 5 — ns
tWZ(2) Write Enable to Output in High-Z — 12 — 15/30 — 30 — 30 — 40 ns
tOW(2) Output Active from End-of-Write 0 — 0 — 0 — 0 — 0 — ns
NOTES: 2986 tbl 12
1. –55°C to +125°C temperature range only.
2. This parameter guaranteed but not tested.
6.2 7
IDT7187S/L
CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
WE
CONTROLLED TIMING)(1,2,3,4)
NOTES:
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW
CS
and a LOW
WE
.
3. tWR is measured from the earlier of
CS
or
WE
going HIGH to the end of the write cycle.
4. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in the high-impedance state.
5. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig).
NOTES:
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW
CS
and a LOW
WE
.
3. tWR is measured from the earlier of
CS
or
WE
going HIGH to the end of the write cycle.
4. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in the high-impedance state.
5. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig).
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CS
CS
CONTROLLED TIMING)(1,2,4)
CS
2986 drw 09
t
AW
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
WP
t
DH
DATA
OUT
t
WZ
t
OW
t
AS
(5)
VALID DATA
(5)
tWR
CS
2986 drw 10
tAW
tDW
DATAIN
ADDRESS
tWC
WE
tCW
tDH
ASt t
VALID DATA
(3)
6.2 8
IDT7187S/L
CMOS STATIC RAM 64K (64K x 1-BIT) MILITARY TEMPERATURE RANGE
ORDERING INFORMATION
X
Power
XX
Speed
X
Package
X
Process/
Temperature
Range
BMilitary (–55°C to +125°C)
Compliant to MIL-STD-883, Class B
D
L22 300 mil Ceramic DIP (D22-1)
Leadless Chip Carrier (L22-1)
25
35
45
55
70
85
S
LStandard Power
Low Power
IDT7187
Speed in nanoseconds
2989 drw 11
Device
Type
