N E X T G E N E R A T I O N D E S I G N S O F T W A R E Lattice Diamond Leading-edge design and implementation tools optimized for Lattice FPGA architectures. Lattice Diamond(R) design software offers leading-edge design and implementation tools optimized for cost-sensitive, low-power Lattice FPGA architectures. Diamond is the next generation replacement for ispLEVER(R) featuring design exploration, ease of use, improved design flow, and numerous other enhancements. This combination of new and enhanced features allows users to complete designs faster, easier, and with better results than ever before. Diamond software is available as a download from the Lattice website for both Windows and Linux. Once downloaded and installed, it can be used with either a free license or a subscription license. Diamond Software Free License A free license can be requested from the Lattice website. This license provides immediate access to many popular Lattice devices such as MachXO2TM, MachXOTM, LatticeXP2TM and LatticeECP2TM at no cost. It also includes Synopsys(R) Synplify ProTM for Lattice synthesis and Aldec(R) Active-HDLTM Lattice Edition II mixed language simulator.* Key Features and Benefits Design Exploration Features * Explore design alternatives with Implementations & Strategies * Run Manager for accelerating exploration and utilizing multi-core processors * Integrated HDL code checking * Lattice Synthesis Engine (LSE) for additional synthesis exploration options. Ease-of-Use Features * Advanced next generation user interface * Centralized reports and messaging * Extensive cross-probing support * Manage multiple constraint, preference, debug, timing analyzer, and power calculator files within file list view * ECO Editor for specific physical netlist-level changes * Programmer for improved programming support Improved Design Flow * New Timing Analyzer view allows updated timing analysis, including clock jitter analysis, without reimplementing the design * Simulation Wizard for exporting designs * Extensive Tcl scripting dictionaries Additional Software Included with Diamond * LatticeMicoTM system integration for embedded microprocessor applications * EPIC full-featured physical netlist-level editor Diamond Software Subscription License A subscription license can be purchased which adds support for all Lattice FPGAs including the latest MachXO2 and LatticeECP3TM devices. It includes Synopsys Synplify Pro for Lattice synthesis and Aldec Active-HDL Lattice Edition II mixed language simulator*. SUPERIOR DESIGN EXPLORATION EASE OF USE IMPROVED DESIGN FLOW *Aldec Active-HDL Lattice Edition II simulator is only available for Windows. Floating licenses require the additional ALDEC-USBKEY product. www.latticesemi.com/latticediamond Diamond Key New Features Design Exploration Projects / Implementations / Strategies Diamond allows more robust projects and offers new capabilities for improved design exploration. Key features include: Mixing of Verilog, VHDL, EDIF, and schematic sources Implementations allow multiple versions of a design within a single project for easy design exploration Strategies allow implementation "recipes" to be applied to any implementation within a project or shared between projects Manage and choose files for constraints, timing analysis, power calculation, and hardware debug Use Run Manager view for parallel processing of multiple implementations to explore design alternatives for the best results HDL Code Checking SYNTHESIS OPTIONS Save time by analyzing your design prior to synthesis with Diamond's integrated HDL code checking capability. Click "Generate Hierarchy" and HDL Diagram, Hierarchy, Module, and Dictionary views become available to help in analyzing your design. Additionally, a number of BKM (Best Known Methods) rule checks can be run against your design. In addition to Synplify Pro for all devices, for MachXO2TM and MachXOTM devices the new Lattice Synthesis Engine (LSE) is also available for exploring how to achieve the best results. LSE supports both Verilog and VHDL languages and uses the Synopsys Design Compiler Constraints format for constraints. Diamond Environment for Design Exploration Ease of Use GUI for a New Generation of Tools The Diamond user interface combines leading edge features and customization while offering improved ease of use. All tools open in "Views" integrated into a common user interface. Once the operation for a single tool is learned, this knowledge can be applied to other tools. Key GUI elements Common menu and button locations for all views Three user interface sections for tools, projects, and output Start Page - Open projects, import ispLEVER projects, online help, software updates Report View - Centralized location for all reports from implementation tools Improved Design Flow Scripting with Tcl Fast, Easy Timing Analysis Tcl command dictionaries for projects, netlists, HDL code checking, power calculation, and hardware debug. In addition to the Tcl console in the Diamond environment, a separate Tcl console application allows running scripts independently. Timing Analysis view offers an easy-touse graphical environment for navigating timing information. Click on a constraint and see the timing paths, detailed paths, and path schematic views instantly Easy visual cues provide instant design feedback. Rapidly updated analysis when timing constraints are changed Add clock jitter analysis to improve the robustness of your design Easy Export to Simulators The new Simulation Wizard guides you through all the necessary steps to get Speed Common Functions with ECO Editor & Programmer ECO Editor provides quick access to commonly used physical netlist editing functions without using the EPIC full editor Programmer allows fast programming of FPGAs Diamond Timing Analysis View your design to Aldec or ModelSim simulators in the format you choose. Improved Features Feature Description Power Calculator * Uses highly accurate data models and a data-driven power model * Provides power estimation and calculation results, graphical power displays, and reports Spreadsheet View * Enter and view design constraints (pin assignments, clock resource usage, global preferences, timing preferences, and more) * Works with File List view to manage multiple constraints files Package View * Easy graphical assignment of signals to pins * Graphical representation of SSO noise analysis Floorplanning Tasks * * * * * Lattice Synthesis Engine (LSE) * Supports MachXO2 and MachXO device families. * Supports both Verilog and VHDL languages and uses Synopsys Design Compiler Constraints (SDC) format for constraints. Reveal Hardware Debugger * Easy insertion of embedded logic analyzer debug hardware for real-time analysis * New streamlined Reveal Analyzer module with multiple cursors and rubber banding for measuring events in the waveform display IPexpress * The interface to the catalog of modules and intellectual property (IP) optimized for Lattice devices * Import a reference file for each module or IP to easily incorporate the changes resulting from regenerating a module or IP Simulink Blockset * Provides DSP blocks that can be used to build DSP solutions within the MATLAB/Simulink environment * These solutions can be exported in HDL optimized for Lattice FPGA architectures Programmer * Comprehensive device programming manager * Efficiently programs Lattice devices using JEDEC and bitstream files generated by Lattice software Synopsys Synplify Pro for Lattice Synthesis * Automatically produce an RTL schematic of your design * Cross-probe with RTL source code * Mixed VHDL and Verilog synthesis support * Compile points * Automatic re-timing (balancing registers across combinatorial logic) * Automatic gated-clock and generated-clock conversion for efficient implementation of RTL written for an ASIC into an FPGA Aldec Active-HDL Simulation * * * * * Floorplan View - View design placement and edit placement constraints Physical View - Detailed view of physical routing of paths to understand timing issues Netlist View - Browse design ports, instances, and nets. Drag and drop into other views to set constraints. NCD View - Detailed usage information of physical components Device View - View device resources and edit placement constraints Mixed language simulation of VHDL and Verilog (Aldec Active-HDL Lattice Edition II only) Language Assistant Code Execution Tracing Advanced Breakpoint Management Memory Viewing FLOORPLAN VIEW PACKAGE VIEW PHYSICAL VIEW Floorplan View provides the ability to view design placement and edit placement constraints. Easy graphical assignment of signals to pins and a graphical representation of SSO noise analysis. A detailed, read-only view of the physical routing of paths for a more detailed understanding of timing issues. Reveal hardware debugger power calculator IPexpress The Reveal Hardware Debugger uses a signal-centric model that allows easy insertion of embedded logic analyzer debug hardware for real-time analysis. The data driven approach of Power Calculator provides very accurate results for both power estimation and calculation. An interface to the Lattice catalog of modules and IP optimized for Lattice devices. Diamond Software Configuration Summary Lattice Diamond Free License Lattice Diamond Subscription License Lattice Device Support LatticeECP3, LatticeECP2M/S, LatticeSCTM, LatticeSCMTM, LatticeECP2/S MachXO2, MachXO, LatticeECPTM, LatticeECTM, LatticeXPTM, LatticeXP2, LatticeECP2 Key Software Features Complete Diamond Software Environment Synopsys Synplify Pro Aldec Active-HDL Lattice Edition II Windows - XP, Vista and 7 (32-bit app, both 32 & 64-bit OS) Linux - RHEL 4 and 5; Novell SUSE 10 1 Year Nodelocked Only, Renewable 1 Year Subscription, Nodelocked or Floating N/A DIAMOND-E-12M Third-Party Software Operating Systems Licensing and Ordering License Terms Part Number Related Products Product Diamond DVD Media Backup USB Key for Aldec Simulation Floating License Download Cable (1.2V to 5V USB Programming Cable) Description Ordering Part Number Diamond software on DVD media. This is media only and does not include a Diamond license. Required to use Aldec simulation with a floating license. Existing USB keys from ispLEVER can also be used with Diamond software. USB programming cable Download Cable (1.8V to 5V Parallel Port Programming Cable) Parallel port programming cable DIAMOND-I-12M ALDEC-USBKEY HW-USBN-2A HW-DLN-3C Applications Support 1-800-LATTICE (528-8423) (503) 268-8001 techsupport@latticesemi.com www.latticesemi.com Copyright (c) 2011 Lattice Semiconductor Corporation. Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., and Lattice (design), IPexpress, ispLEVER, ispVM, Lattice Diamond, LatticeEC, LatticeECP, LatticeECP2, LatticeECP2M, LatticeECP3, LatticeMico, LatticeMico32, LatticeSC, LatticeSCM, LatticeXP, LatticeXP2, MachXO, MachXO2, Reveal and sysIO are either registered trademarks or trademarks of Lattice Semiconductor Corporation in the United States and/ or other countries. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. July 2011 Order #: I0207C Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Lattice: ALDEC-USBKEY DIAMOND-E-12M DIAMOND-I-12M