DATASHEET DG406, DG407 FN3116 Rev 11.00 October 1, 2013 Single 16-Channel/Differential 8-Channel, CMOS Analog Multiplexers The DG406 and DG407 monolithic CMOS analog multiplexers are drop-in replacements for the popular DG506A and DG507A series devices. They each include an array of sixteen analog switches, a TTL and CMOS compatible digital decode circuit for channel selection, a voltage reference for logic thresholds, and an ENABLE input for device selection when several multiplexers are present. Features These multiplexers feature lower signal ON-resistance (<100) and faster transition time (tTRANS < 300ns) compared to the DG506A and DG507A. Charge injection has been reduced, simplifying sample and hold applications. * TTL, CMOS Compatible The improvements in the DG406 series are made possible by using a high voltage silicon-gate process. An epitaxial layer prevents the latch-up associated with older CMOS technologies. The 44V maximum voltage range permits controlling 30VP-P signals when operating with 15V power supplies. The sixteen switches are bilateral, equally matched for AC or bidirectional signals. The ON-resistance variation with analog signals is quite low over a 5V analog input range. * ON-Resistance (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 * Low Power Consumption (PD) . . . . . . . . . . . . . . . . . . <1.2mW * Fast Transition Time (Max) . . . . . . . . . . . . . . . . . . . . . . . 300ns * Low Charge Injection * Single or Split Supply Operation * Pb-Free (RoHS Compliant) Applications * Battery Operated Systems * Data Acquisition * Medical Instrumentation * Hi-Rel Systems * Communication Systems * Automatic Test Equipment Related Literature * Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" 80 BUFFER ANALOG INPUTS ADC CPU rDS(ON) , ON-RESISTANCE (W) 70 DG406 MUX +125C 60 +85C 50 +25C 40 0C 30 -40C 20 -55C V+ = 15V V- = -15V 10 0 -15 FIGURE 1. TYPICAL APPLICATION FN3116 Rev 11.00 October 1, 2013 -10 -5 0 5 VD , DRAIN VOLTAGE (V) 10 FIGURE 2. 15 DUAL SUPPLY rON CURVES AT VARIOUS TEMPERATURES Page 1 of 15 15 DG406, DG407 Pin Configurations DG407 (28 LD PDIP, SOIC) TOP VIEW DG406 (28 LD PDIP, SOIC) TOP VIEW V+ 1 28 D NC 2 NC 3 V+ 1 28 DA 27 V- DB 2 27 V- 26 S8 NC 3 26 S8A S16 4 25 S7 S8B 4 25 S7A S15 5 24 S6 S7B 5 24 S6A S14 6 23 S5 S6B 6 23 S5A S13 7 22 S4 S5B 7 22 S4A S12 8 21 S3 S4B 8 21 S3A S11 9 20 S2 S3B 9 20 S2A S10 10 19 S1 S2B 10 19 S1A S9 11 18 EN S1B 11 18 EN GND 12 17 A0 GND 12 17 A0 NC 13 16 A1 NC 13 16 A1 A3 14 15 A2 NC 14 15 A2 Pin Description DG406 (PDIP, SOIC) DG407 (PDIP, SOIC) SYMBOL 1 1 V+ Positive Power Supply 2, 3, 13 3, 13, 14, NC No Connect- No Internal Connection 4, 5, 6, 7, 8, 9, 10, 11 - S16 thru S9 12 12 GND 14, 15, 16, 17 - A3 thru A0 Logic Control Inputs - 15, 16, 17 A2 thru A0 Logic Control Inputs 18 18 EN 19, 20, 21, 22, 23, 24, 25, 26 - S1 thru S8 27 27 V- Negative Power Supply (Single supply application this pin will be connected to ground.) 28 - D Drain Switch Terminal (This pin can be an input or output) - 2, 28 DB, DA Drain Switch Terminal (This pin can be an input or output) - 4, 5, 6, 7, 8, 9, 10, 11 S1B thru S8B Source Switch Terminals B (These pins can be an input or output) - 19, 20, 21, 22, 23, 24, 25, 26 S1A thru S8A Source Switch Terminals A (These pins can be an input or output) FN3116 Rev 11.00 October 1, 2013 DESCRIPTION Source Switch Terminals (These pins can be an input or output) Ground (0V) Reference Active High Digital Input (When low device is disabled and all switches are turned off. When high the Ax logic inputs determine which switch is turned on. Source Switch Terminals (These pins can be an input or output) Page 2 of 15 DG406, DG407 Ordering Information PART NUMBER (Notes 2, 4) PART MARKING DG406DJZ TEMP. RANGE (C) DG406DJZ -40 to +85 PACKAGE (Pb-free) PKG. DWG. # 28 Ld PDIP (Note 3) E28.6 DG406DYZ DG406DYZ -40 to +85 28 Ld SOIC M28.3 DG406DYZ-T (Note 1) DG406DYZ -40 to +85 28 Ld SOIC Tape and Reel M28.3 DG407DJZ DG407DJZ -40 to +85 28 Ld PDIP (Note 3) E28.6 DG407DYZ DG407DYZ -40 to +85 28 Ld SOIC M28.3 DG407DYZ-T (Note 1) DG407DYZ -40 to +85 28 Ld SOIC Tape and Reel M28.3 NOTES: 1. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications. 4. For Moisture Sensitivity Level (MSL), please see device information page for DG406, DG407. For more information on MSL, please see tech brief TB363 Schematic Diagram (Typical Channel) V+ GND VREF D A0 V+ LEVEL SHIFT AX DECODE/ DRIVE V- S1 V+ EN SN V- FN3116 Rev 11.00 October 1, 2013 Page 3 of 15 DG406, DG407 Functional Diagrams DG406 DG407 S1A S1 S2A S2 S3A S3 S4A S4 S6A S6 S7A S7 S8A S8 D S9 S10 S1B S11 S2B S12 S3B S13 S4B S14 S5B S15 S6B S16 S7B ADDRESS DECODER 1 OF 16 A1 A2 DB S8B TO DECODER LOGIC CONTROLLING BOTH TIERS OF MUXING A0 DA S5A S5 TO DECODER LOGIC CONTROLLING BOTH TIERS OF MUXING ENABLE A3 ADDRESS DECODER 1 OF 8 ENABLE EN A0 A1 A2 EN Truth Tables TABLE 1. DG406 TRUTH TABLE TABLE 2. DG407 TRUTH TABLE A3 A2 A1 A0 EN ON SWITCH A2 A1 A0 EN ON SWITCH PAIR X X X X 0 None X X X 0 None 0 0 0 0 1 1 0 0 0 1 1 2 0 0 0 1 1A, 1B 0 0 1 0 1 3 0 0 1 1 2A, 2B 0 0 1 1 1 4 0 1 0 1 3A, 3B 0 1 0 0 1 5 0 1 1 1 4A, 4B 0 1 0 1 1 6 1 0 0 1 5A, 5B 0 1 1 0 1 7 1 0 1 1 6A, 6B 0 1 1 1 1 8 1 1 0 1 7A, 7B 1 0 0 0 1 9 1 0 0 1 1 10 1 1 1 1 8A, 8B 1 0 1 0 1 11 1 0 1 1 1 12 1 1 0 0 1 13 1 1 0 1 1 14 1 1 1 0 1 15 1 1 1 1 1 16 FN3116 Rev 11.00 October 1, 2013 Logic "0" = VAL < 0.8V. Logic "1" = VAH > 2.4V. X = Don't Care. Page 4 of 15 DG406, DG407 Absolute Maximum Ratings Thermal Information V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V GND to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V Digital Inputs, VS , VD (Note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(V-) -2V to (V+) +2V or 20mA, Whichever Occurs First Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA Peak Current, S or D (Pulsed 1ms, 10% Duty Cycle Max) . . . . . . . . . . . . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical, Note 5) JA (C/W) PDIP Package*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150C Maximum Storage Temperature Range . . . . . . . . . . . . . .-65C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. Signals on SX , DX , EN or AX exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings. Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VAL = 0.8V, VAH = 2.4V Unless Otherwise Specified. Bold-face limits apply over the operating temperature range, -40C to +85C. PARAMETER TEST CONDITIONS TEMP (C) MIN (Notes 7, 12) TYP (Note 8) MAX (Notes 7, 12) UNITS 25 - 200 300 ns DYNAMIC CHARACTERISTICS Transition Time, tTRANS (See Figure 3) Break-Before-Make Interval, tOPEN (See Figure 5) Enable Turn-ON Time, tON(EN) (See Figure 4) Enable Turn-OFF Time, tOFF(EN) Full - - 400 ns 25 25 50 - ns Full 10 - - ns 25 - 150 200 ns Full - - 400 ns 25 - 70 150 ns Full - - 300 ns Charge Injection, Q CL = 1nF, VS = 0V, RS = 0 25 - 40 - pC OFF-Isolation, OIRR VEN = 0V, RL = 1k, f = 100kHz (Note 11) 25 - -69 - dB Logic Input Capacitance, CIN f = 1MHz 25 - 7 - pF Source OFF Capacitance, CS(OFF) VEN = 0V, VS = 0V, f = 1MHz 25 - 8 - pF Drain OFF Capacitance, CD(OFF) VEN = 0V, VD = 0V, f = 1MHz DG406 25 - 160 - pF DG407 25 - 80 - pF Drain ON Capacitance, CD(ON) VEN = 5V, VD = 0V, f = 1MHz DG406 25 - 180 - pF DG407 25 - 90 - pF Full 2.4 - - V DIGITAL INPUT CHARACTERISTICS Logic High Input Voltage, VINH Full - - 0.8 V Logic High Input Current, IAH VA = 2.4V, 15V Full -1 - 1 A Logic Low Input Current, IAL VEN = 0V, 2.4V, VA = 0V Full -1 - 1 A Logic Low Input Voltage, VINL ANALOG SWITCH CHARACTERISTICS Drain-Source ON-Resistance, rDS(ON) rDS(ON) Matching Between Channels, rDS(ON) FN3116 Rev 11.00 October 1, 2013 VD = 10V, IS = +10mA (Note 9) VD = 10V, -10V (Note 10) 25 - 50 100 Full - - 125 25 - 5 - % Page 5 of 15 DG406, DG407 Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VAL = 0.8V, VAH = 2.4V Unless Otherwise Specified. Bold-face limits apply over the operating temperature range, -40C to +85C. (Continued) PARAMETER Source OFF Leakage Current, IS(OFF) TEST CONDITIONS VEN = 0V, VS = 10V, VD = +10V TEMP (C) MIN (Notes 7, 12) TYP (Note 8) MAX (Notes 7, 12) UNITS 25 -0.5 0.01 0.5 nA Full -5 - 5 nA 25 -1 0.04 1 nA Full -40 - 40 nA 25 -1 0.04 1 nA Full -20 - 20 nA 25 -1 0.04 1 nA Full -40 - 40 nA 25 -1 0.04 1 nA Full -20 - 20 nA 25 - 13 30 A Full - - 75 A Drain OFF Leakage Current, ID(OFF) DG406 DG407 Drain ON Leakage Current, ID(ON) VS = VD = 10V (Note 9) DG406 DG407 POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ VEN = VA = 0V or 5V (Standby) Negative Supply Current, IPositive Supply Current, I+ VEN = 2.4V, VA = 0V (Enabled) Negative Supply Current, I- Electrical SpecificationsMSingle Supply Test Conditions: 25 -1 -0.01 - A Full -10 - - A 25 - 80 100 A Full - - 200 A 25 -1 -0.01 - A Full -10 - - A V+ = 12V, V- = 0V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified. TEST CONDITIONS TEMP (C) MIN (Notes 7, 12) TYP (Note 8) MAX (Notes 7, 12) UNITS Switching Time of Multiplexer, tTRANS VS1 = 8V, VS8 = 0V, VIN = 2.4V 25 - 300 450 ns Enable Turn-ON Time, tON(EN) VINH = 2.4V, VINL = 0V, VS1 = 5V 25 - 250 600 ns 25 - 150 300 ns CL = 1nF, VS = 6V, RS = 0 25 - 20 - pC Full 0 - 12 V 25 - 90 120 25 - 5 - % 25 - 0.01 - nA DG406 25 - 0.04 - nA DG407 25 - 0.04 - nA PARAMETER DYNAMIC CHARACTERISTICS Enable Turn-OFF Time, tOFF(EN) Charge Injection, Q ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG Drain-Source ON-Resistance, rDS(ON) VD = 3V, 10V, IS = -1mA (Note 9) rDS(ON) Matching Between Channels (Note 6), rDS(ON) Source Off Leakage Current,IS(OFF) Drain Off Leakage Current, ID(OFF) FN3116 Rev 11.00 October 1, 2013 VEN = 0V, VD = 10V or 0.5V, VS = 0.5V or 10V Page 6 of 15 DG406, DG407 Electrical SpecificationsMSingle Supply Test Conditions: V+ = 12V, V- = 0V, VAL = 0.8V, VAH = 2.4V, Unless Otherwise Specified. (Continued) TEST CONDITIONS TEMP (C) MIN (Notes 7, 12) TYP (Note 8) MAX (Notes 7, 12) UNITS DG406 25 - 0.04 - nA DG407 25 - 0.04 - nA 25 - 13 30 A Full - 13 75 A 25 -1 -0.01 - A Full -5 -0.01 - A PARAMETER Drain On Leakage Current, ID(ON) VS = VD = 10V (Note 9) POWER SUPPLY CHARACTERISTICS VEN = 0V or 5V, VA = 0V or 5V Positive Supply Current (I+) (Standby) Negative Supply Current (I-) (Enabled) NOTES: 7. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 8. Typical values are for design only and are not production tested. 9. Sequence each switch ON. 10. rDS(ON) = (rDS(ON)(Max) - rDS(ON)(Min)) rDS(ON) average. 11. Worst case isolation occurs on channel 8B due to proximity to the drain pin. 12. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Test Circuits and Waveforms +15V +15V EN A3 A2 V+ S2 - S15 DG406 S 16 A1 A0 GND V- D 50 EN A2 LOGIC INPUT 10V LOGIC INPUT +2.4V 10V S1 A1 A0 VO 300 V+ S1B DG407 GND S8B V- 50 35pF 10V 10V +2.4V DB VO 300 35pF -15V -15V = S1A - S8A , S2B - S7B , DA FIGURE 3A. DG406 TEST CIRCUIT LOGIC INPUT SWITCH OUTPUT VO FIGURE 3B. DG407 TEST CIRCUIT tr < 20ns tf < 20ns 3V 50% 0V VS1B 50% S1 ON 80% VS1 0V 80% VS8B tTRANS VS8 S8 ON tTRANS FIGURE 3C. MEASUREMENT POINTS FIGURE 3. TRANSITION TIME FN3116 Rev 11.00 October 1, 2013 Page 7 of 15 DG406, DG407 Test Circuits and Waveforms (Continued) +15V +15V A3 A2 A1 LOGIC INPUT VIN V+ A2 -5V S1 A1 S2 - S16 LOGIC INPUT VIN DG406 A0 EN GND V- VO D 50 300 A0 EN 50 V+ -5V S1B DG407 DA AND DB GND V- VO 300 35pF 35pF -15V -15V = S1A - S8A , S2B - S8B , DA FIGURE 4A. DG406 TEST CIRCUIT LOGIC INPUT VIN FIGURE 4B. DG407 TEST CIRCUIT tr < 20ns tf < 20ns 3V 50% 50% 0V tON(EN) tOFF(EN) 0V SWITCH OUTPUT VO VO 90% VO FIGURE 4C. MEASUREMENT POINTS FIGURE 4. ENABLE SWITCHING TIMES +15V +2.4V EN A3 LOGIC INPUT V+ ALL S AND DA +5V (VS) 0V DG406 DG407 A1 D, A0 GND V- DB A2 LOGIC INPUT 50 tr < 20ns tf < 20ns 3V VO 300 35pF SWITCH OUTPUT VO VS 0V tOPEN -15V FIGURE 5A. TEST CIRCUIT 80% FIGURE 5B. MEASUREMENT POINTS FIGURE 5. BREAK-BEFORE-MAKE INTERVAL FN3116 Rev 11.00 October 1, 2013 Page 8 of 15 DG406, DG407 160 80 140 70 rDS(ON) , ON-RESISTANCE () rDS(ON) , ON RESISTANCE () Typical Performance Curves 120 5V 100 80 8V 10V 12V 15V 60 40 20V 20 0 -20 -16 +125C 60 +85C 50 +25C 40 0C 30 -40C 20 -55C V+ = 15V V- = -15V 10 -12 -8 -4 0 4 8 VD , DRAIN VOLTAGE (V) 12 16 0 -15 20 FIGURE 6. rDS(ON) vs VD AND SUPPLY 120 ID , IS , CURRENT (pA) rDS(ON) , ON-RESISTANCE () 80 160 10V 120 12V 80 15V 20V 22V 0 4 8 12 16 40 IS(OFF) 0 -40 DG406 ID(ON) , ID(OFF) DG407 ID(ON) , ID(OFF) -120 -15 20 VD , DRAIN VOLTAGE (V) TIME (ns) ID , IS , CURRENT (A) 250 ID(ON) , ID(OFF) 10pA IS(OFF) 25 45 65 85 105 TEMPERATURE (oC) FIGURE 10. ID , IS LEAKAGE vs TEMPERATURE FN3116 Rev 11.00 October 1, 2013 15 tTRANS 200 tON(EN) 150 tOFF(EN) 50 5 10 100 1pA -15 5 300 1nA -35 0 350 10nA 0.1pA -55 -5 FIGURE 9. ID, IS LEAKAGE CURRENTS vs ANALOG VOLTAGE V+ = 15V, V- = -15V VS OR VD = 10V 100pA -10 VS , VD , SOURCE DRAIN VOLTAGE (V) FIGURE 8. rDS(ON) vs VD AND SUPPLY 100nA 15 -80 40 0 10 V+ = 15V, V- = -15V VS = -VD FOR ID(OFF) VD = VS(OPEN) FOR ID(ON) V+ = 7.5V 200 -5 0 5 VD , DRAIN VOLTAGE (V) FIGURE 7. rDS(ON) vs VD AND TEMPERATURE V- = 0V 240 -10 125 0 5 10 15 VSUPPLY, SUPPLY VOLTAGE (V) FIGURE 11. SWITCHING TIMES vs BIPOLAR SUPPLIES Page 9 of 15 20 DG406, DG407 Typical Performance Curves (Continued) 700 -140 600 -120 500 -100 tTRANS 400 300 ISOL (dB) TIME (ns) V- = 0V tON(EN) -80 -60 -40 200 tOFF(EN) -20 100 0 5 10 15 0 100 20 1k 10k V+, SUPPLY VOLTAGE (V) 300 10 EN = 5V, AX = 0V OR 5V 280 V+ = 15V, V- = -15V 240 I+ 4 220 2 TIME (ns) I, CURRENT (mA) 10M 260 6 0 IGND -2 tTRANS 200 180 tON(EN) 160 140 -4 120 I- -6 100 -8 -10 10 1M FIGURE 13. OFF-ISOLATION vs FREQUENCY FIGURE 12. SWITCHING TIMES vs SINGLE SUPPLY 8 100k f, FREQUENCY (Hz) tOFF(EN) 80 100 1K 10K 100K 1M 60 -55 10M -35 -15 f, FREQUENCY (Hz) 5 25 45 65 85 105 TEMPERATURE (C) FIGURE 14. SUPPLY CURRENTS vs SWITCHING FREQUENCY FIGURE 15. tON /tOFF vs TEMPERATURE 3 VA , (V) 2 1 0 0 5 10 15 20 VSUPPLY, SUPPLY VOLTAGE (V) FIGURE 16. SWITCHING THRESHOLD vs SUPPLY VOLTAGE FN3116 Rev 11.00 October 1, 2013 Page 10 of 15 125 DG406, DG407 Die Characteristics PASSIVATION: Type: Nitride Thickness: 8kA 1kA DIE DIMENSIONS: 2490m x 4560m x 485m WORST CASE CURRENT DENSITY: METALLIZATION: 9.1 x 104 A/cm2 Type: SiAl Thickness: 12kA 1kA Metallization Mask Layout DG407 DB V+ DA V- S8A S8B S7A S7B S6A S6B S5A S5B S4A S4B S3A S3B S2A S2B S1A S1B GND FN3116 Rev 11.00 October 1, 2013 NC A2 A1 A0 EN Page 11 of 15 DG406, DG407 Die Characteristics PASSIVATION: Type: Nitride Thickness: 8kA 1kA DIE DIMENSIONS: 2490m x 4560m x 485m WORST CASE CURRENT DENSITY: METALLIZATION: 9.1 x 104 A/cm2 Type: SiAl Thickness: 12kA 1kA Metallization Mask Layout DG406 NC D V- S16 S5 S15 S7 S14 S6 S13 S5 S12 S4 S11 S3 S10 S2 S9 S1 GND A3 FN3116 Rev 11.00 October 1, 2013 V+ A2 A1 A0 EN Page 12 of 15 DG406, DG407 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE October 1, 2013 FN3116.11 Converted to new Intersil template. Removed obsolete parts from ordering information as follows: DG406DJ DG406DY DG406DY-T DG407DY DG407DJ Added P/N DG407DYZ-T to Ordering Information table. March 13, 2006 FN3116.9 Redline Release parts added to ordering information. September 17, 2004 FN3116.8 Pb-free parts added. August 1, 2000 FN3116.6 Initial Release to web. About Intersil Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at http://www.intersil.com/en/support/qualandreliability.html#reliability FN3116 Rev 11.00 October 1, 2013 Page 13 of 15 DG406, DG407 Dual-In-Line Plastic Packages (PDIP) E28.6 (JEDEC N INDEX AREA 1 2 3 INCHES N/2 -B- -AD E BASE PLANE -C- SEATING PLANE A2 A L D1 e B1 D1 B 0.010 (0.25) M MS-011-AB ISSUE B) 28 LEAD DUAL-IN-LINE PLASTIC PACKAGE E1 A1 eC C A B S MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A - 0.250 - 6.35 4 A1 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.030 0.070 0.77 1.77 8 eA C 0.008 0.015 C D 1.380 1.565 eB D1 0.005 - 0.13 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 C L NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. e 0.204 0.381 35.1 0.100 BSC 39.7 - 5 5 2.54 BSC - 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eA 0.600 BSC 15.24 BSC 6 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. eB - 0.700 - 7 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. L 0.115 0.200 2.93 N 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 28 17.78 5.08 28 4 9 Rev. 1 12/00 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). FN3116 Rev 11.00 October 1, 2013 Page 14 of 15 DG406, DG407 Small Outline Plastic Packages (SOIC) M28.3 (JEDEC MS-013-AE ISSUE C) N 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B- 1 2 3 L SEATING PLANE -A- A D h x 45o a e A1 B C 0.10(0.004) 0.25(0.010) M C A M B S MAX MILLIMETERS MIN MAX NOTES A 0.0926 0.1043 2.35 2.65 - A1 0.0040 0.0118 0.10 0.30 - B 0.013 0.0200 0.33 0.51 9 C 0.0091 0.0125 0.23 0.32 - D 0.6969 0.7125 17.70 18.10 3 E 0.2914 0.2992 7.40 7.60 4 e -C- MIN 0.05 BSC h 0.01 0.029 0.25 0.75 5 L 0.016 0.050 0.40 1.27 6 10.00 - 0.394 N 0.419 1.27 BSC H 28 0o 10.65 - 28 8o 0o 7 8o Rev. 1, 1/13 NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. TYPICAL RECOMMENDED LAND PATTERN (1.50mm) 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. (9.38mm) 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) (1.27mm TYP) (0.51mm TYP) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (c) Copyright Intersil Americas LLC 2000-2013. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN3116 Rev 11.00 October 1, 2013 Page 15 of 15