FN3116 Rev 11.00 Page 1 of 15
October 1, 2013
FN3116
Rev 11.00
October 1, 2013
DG406, DG407
Single 16-Channel/Differential 8-Channel, CMOS Analog Multiplexers
DATASHEET
The DG406 and DG407 monolithic CMOS analog multiplexers
are drop-in replacements for the popular DG506A and
DG507A series devices. They each include an array of sixteen
analog switches, a TTL and CMOS compatible digital decode
circuit for channel selection, a voltage reference for logic
thresholds, and an ENABLE input for device selection when
several multiplexers are present.
These multiplexers feature lower signal ON-resistance
(<100) and faster transition time (tTRANS < 300ns)
compared to the DG506A and DG507A. Charge injection has
been reduced, simplifying sample and hold applications.
The improvements in the DG406 series are made possible by
using a high voltage silicon-gate process. An epitaxial layer
prevents the latch-up associated with older CMOS
technologies. The 44V maximum voltage range permits
controlling 30VP-P signals when operating with ±15V power
supplies.
The sixteen switches are bilateral, equally matched for AC or
bidirectional signals. The ON-resistance variation with analog
signals is quite low over a ±5V analog input range.
Features
• ON-Resistance (Max) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100
•Low Power Consumption (P
D) . . . . . . . . . . . . . . . . . . <1.2mW
• Fast Transition Time (Max) . . . . . . . . . . . . . . . . . . . . . . . 300ns
• Low Charge Injection
• TTL, CMOS Compatible
• Single or Split Supply Operation
• Pb-Free (RoHS Compliant)
Applications
• Battery Operated Systems
• Data Acquisition
• Medical Instrumentation
• Hi-Rel Systems
• Communication Systems
• Automatic Test Equipment
Related Literature
•Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
FIGURE 1. TYPICAL APPLICATION FIGURE 2. ±15 DUAL SUPPLY rON CURVES AT VARIOUS
TEMPERATURES
CPU
ADC
DG406
BUFFER
ANALOG
INPUTS
MUX
+125°C
-40°C
-55°C
+25°C
+85°C
0°C
V+ = 15V
V- = -15V
80
70
60
50
40
30
20
10
0
-15 -10 -5 5 10015
VD, DRAIN VOLTAGE (V)
rDS(ON), ON-RESISTANCE (W)
DG406, DG407
FN3116 Rev 11.00 Page 2 of 15
October 1, 2013
Pin Configurations
DG406
(28 LD PDIP, SOIC)
TOP VIEW
DG407
(28 LD PDIP, SOIC)
TOP VIEW
V+
NC
NC
S16
S15
S14
S13
S12
S11
S10
S9
GND
NC
A3
D
S8
S7
S6
S5
S3
S1
EN
A0
A1
A2
V-
S4
S2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
V+
DB
NC
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
GND
NC
NC
DA
S8A
S7A
S6A
S5A
S3A
S1A
EN
A0
A1
A2
V-
S4A
S2A
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Description
DG406
(PDIP, SOIC)
DG407
(PDIP, SOIC) SYMBOL DESCRIPTION
1 1 V+ Positive Power Supply
2, 3, 13 3, 13, 14, NC No Connect- No Internal Connection
4, 5, 6, 7, 8, 9, 10, 11 - S16 thru S9Source Switch Terminals (These pins can be an input or output)
12 12 GND Ground (0V) Reference
14, 15, 16, 17 - A3 thru A0Logic Control Inputs
- 15, 16, 17 A2 thru A0Logic Control Inputs
18 18 EN Active High Digital Input (When low device is disabled and all switches are
turned off. When high the Ax logic inputs determine which switch is turned
on.
19, 20, 21, 22, 23, 24, 25,
26
- S1 thru S8 Source Switch Terminals (These pins can be an input or output)
27 27 V-Negative Power Supply (Single supply application this pin will be connected
to ground.)
28 - D Drain Switch Terminal (This pin can be an input or output)
-2, 28D
B, DADrain Switch Terminal (This pin can be an input or output)
- 4, 5, 6, 7, 8, 9, 10, 11 S1B thru S8B Source Switch Terminals B (These pins can be an input or output)
- 19, 20, 21, 22, 23, 24, 25,
26
S1A thru S8A Source Switch Terminals A (These pins can be an input or output)
DG406, DG407
FN3116 Rev 11.00 Page 3 of 15
October 1, 2013
Schematic Diagram (Typical Channel)
Ordering Information
PART
NUMBER
(Notes 2, 4)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
DG406DJZ DG406DJZ -40 to +85 28 Ld PDIP (Note 3) E28.6
DG406DYZ DG406DYZ -40 to +85 28 Ld SOIC M28.3
DG406DYZ-T (Note 1) DG406DYZ -40 to +85 28 Ld SOIC Tape and Reel M28.3
DG407DJZ DG407DJZ -40 to +85 28 Ld PDIP (Note 3) E28.6
DG407DYZ DG407DYZ -40 to +85 28 Ld SOIC M28.3
DG407DYZ-T (Note 1) DG407DYZ -40 to +85 28 Ld SOIC Tape and Reel M28.3
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications.
4. For Moisture Sensitivity Level (MSL), please see device information page for DG406, DG407. For more information on MSL, please see tech brief
TB363
V+
GND
A0
AX
EN
V-
VREF
LEVEL
SHIFT
DECODE/
DRIVE
V+
V+ V-
D
S1
SN
DG406, DG407
FN3116 Rev 11.00 Page 4 of 15
October 1, 2013
Truth Tables
Functional Diagrams
DG406 DG407
S1
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
S12
S13
S14
S15
S16
D
TO DECODER LOGIC
CONTROLLING BOTH
TIERS OF MUXING
ADDRESS DECODER
1 OF 16 ENABLE
A0A1A2A3EN
S2A
S3A
S4A
S5A
S6A
S7A
S8A
S1B
S2B
S3B
S4B
S5B
S6B
S7B
S8B
DA
TO DECODER LOGIC
CONTROLLING BOTH
TIERS OF MUXING
ADDRESS DECODER
1 OF 8 ENABLE
A0A1A2EN
S1A
DB
TABLE 1. DG406 TRUTH TABLE
A3A2A1A0EN ON SWITCH
XXXX0 None
00001 1
00011 2
00101 3
00111 4
01001 5
01011 6
01101 7
01111 8
10001 9
10011 10
10101 11
10111 12
11001 13
11011 14
11101 15
11111 16
TABLE 2. DG407 TRUTH TABLE
A2A1A0EN ON SWITCH PAIR
XXX0 None
0 0 0 1 1A, 1B
0 0 1 1 2A, 2B
0 1 0 1 3A, 3B
0 1 1 1 4A, 4B
1 0 0 1 5A, 5B
1 0 1 1 6A, 6B
1 1 0 1 7A, 7B
1 1 1 1 8A, 8B
Logic “0” = VAL < 0.8V.
Logic “1” = VAH > 2.4V.
X = Don’t Care.
DG406, DG407
FN3116 Rev 11.00 Page 5 of 15
October 1, 2013
Absolute Maximum Ratings Thermal Information
V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44.0V
GND to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25V
Digital Inputs, VS, VD (Note 6)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(V-) -2V to (V+) +2V or 20mA,
Whichever Occurs First
Continuous Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . 30mA
Peak Current, S or D
(Pulsed 1ms, 10% Duty Cycle Max) . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Thermal Resistance (Typical, Note 5) JA (°C/W)
PDIP Package*. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
*Pb-free PDIPs can be used for through-hole wave solder processing only.
They are not intended for use in Reflow solder processing applications.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. Signals on SX, DX, EN or AX exceeding V+ or V- are clamped by internal diodes. Limit diode current to maximum current ratings.
Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VAL = 0.8V, VAH = 2.4V Unless Otherwise Specified. Bold-face limits
apply over the operating temperature range, -40°C to +85°C.
PARAMETER TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 7, 12)
TYP
(Note 8)
MAX
(Notes 7, 12) UNITS
DYNAMIC CHARACTERISTICS
Transition Time, tTRANS (See Figure 3) 25 - 200 300 ns
Full - - 400 ns
Break-Before-Make Interval, tOPEN (See Figure 5) 25 25 50 - ns
Full 10 --ns
Enable Turn-ON Time, tON(EN) (See Figure 4) 25 - 150 200 ns
Full - - 400 ns
Enable Turn-OFF Time, tOFF(EN) 25 - 70 150 ns
Full - - 300 ns
Charge Injection, Q CL = 1nF, VS = 0V, RS = 025 - 40 - pC
OFF-Isolation, OIRR VEN = 0V, RL = 1k,
f = 100kHz (Note 11)
25 - -69 - dB
Logic Input Capacitance, CIN f = 1MHz 25 - 7 - pF
Source OFF Capacitance, CS(OFF) VEN = 0V, VS = 0V, f = 1MHz 25 - 8 - pF
Drain OFF Capacitance, CD(OFF) VEN = 0V, VD = 0V, f = 1MHz
DG406 25 - 160 - pF
DG407 25 - 80 - pF
Drain ON Capacitance, CD(ON) VEN = 5V, VD = 0V, f = 1MHz
DG406 25 - 180 - pF
DG407 25 - 90 - pF
DIGITAL INPUT CHARACTERISTICS
Logic High Input Voltage, VINH Full 2.4 --V
Logic Low Input Voltage, VINL Full --0.8 V
Logic High Input Current, IAH VA = 2.4V, 15V Full -1 -1µA
Logic Low Input Current, IAL VEN = 0V, 2.4V, VA = 0V Full -1 -1µA
ANALOG SWITCH CHARACTERISTICS
Drain-Source ON-Resistance, rDS(ON) VD = ±10V, IS = +10mA
(Note 9)
25 - 50 100
Full - - 125
rDS(ON) Matching Between Channels, rDS(ON) VD = 10V, -10V (Note 10) 25 - 5 - %
DG406, DG407
FN3116 Rev 11.00 Page 6 of 15
October 1, 2013
Source OFF Leakage Current, IS(OFF) VEN = 0V, VS = ±10V,
VD = +10V
25 -0.5 0.01 0.5 nA
Full -5 -5nA
Drain OFF Leakage Current, ID(OFF)
DG406 25 -1 0.04 1 nA
Full -40 -40 nA
DG407 25 -1 0.04 1 nA
Full -20 -20 nA
Drain ON Leakage Current, ID(ON) VS = VD = ±10V (Note 9)
DG406 25 -1 0.04 1 nA
Full -40 -40 nA
DG407 25 -1 0.04 1 nA
Full -20 -20 nA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current, I+ VEN = VA = 0V or 5V
(Standby)
25 - 13 30 µA
Full - - 75 µA
Negative Supply Current, I- 25 -1 -0.01 - µA
Full -10 --µA
Positive Supply Current, I+ VEN = 2.4V, VA = 0V
(Enabled)
25 - 80 100 µA
Full - - 200 µA
Negative Supply Current, I- 25 -1 -0.01 - µA
Full -10 --µA
Electrical Specifications Test Conditions: V+ = +15V, V- = -15V, VAL = 0.8V, VAH = 2.4V Unless Otherwise Specified. Bold-face limits
apply over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 7, 12)
TYP
(Note 8)
MAX
(Notes 7, 12) UNITS
Electrical SpecificationsMSingle Supply Test Conditions: V+ = 12V, V- = 0V, VAL = 0.8V, VAH = 2.4V,
Unless Otherwise Specified.
PARAMETER
TEST
CONDITIONS
TEMP
(°C)
MIN
(Notes 7, 12)
TYP
(Note 8)
MAX
(Notes 7, 12) UNITS
DYNAMIC CHARACTERISTICS
Switching Time of Multiplexer, tTRANS VS1 = 8V, VS8 = 0V, VIN = 2.4V 25 - 300 450 ns
Enable Turn-ON Time, tON(EN) VINH = 2.4V, VINL = 0V,
VS1 = 5V
25 - 250 600 ns
Enable Turn-OFF Time, tOFF(EN) 25 - 150 300 ns
Charge Injection, Q CL = 1nF, VS = 6V, RS = 025 - 20 - pC
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG Full 0-12 V
Drain-Source ON-Resistance,
rDS(ON)
VD = 3V, 10V, IS = -1mA
(Note 9)
25 - 90 120
rDS(ON) Matching Between
Channels (Note 6), rDS(ON)
25 - 5 - %
Source Off Leakage Current,IS(OFF) VEN = 0V, VD = 10V or 0.5V,
VS= 0.5V or 10V
25 - 0.01 - nA
Drain Off Leakage Current, ID(OFF)
DG406 25 - 0.04 - nA
DG407 25 - 0.04 - nA
DG406, DG407
FN3116 Rev 11.00 Page 7 of 15
October 1, 2013
Drain On Leakage Current, ID(ON) VS = VD = ±10V (Note 9)
DG406 25 - 0.04 - nA
DG407 25 - 0.04 - nA
POWER SUPPLY CHARACTERISTICS
Positive Supply Current (I+)
(Standby)
VEN = 0V or 5V, VA = 0V or 5V 25 - 13 30 µA
Full - 13 75 µA
Negative Supply Current (I-)
(Enabled)
25 -1 -0.01 - µA
Full -5 -0.01 - µA
NOTES:
7. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
8. Typical values are for design only and are not production tested.
9. Sequence each switch ON.
10. rDS(ON) = (rDS(ON)(Max) - rDS(ON)(Min)) rDS(ON) average.
11. Worst case isolation occurs on channel 8B due to proximity to the drain pin.
12. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Electrical SpecificationsMSingle Supply Test Conditions: V+ = 12V, V- = 0V, VAL = 0.8V, VAH = 2.4V,
Unless Otherwise Specified. (Continued)
PARAMETER
TEST
CONDITIONS
TEMP
(°C)
MIN
(Notes 7, 12)
TYP
(Note 8)
MAX
(Notes 7, 12) UNITS
Test Circuits and Waveforms
FIGURE 3A. DG406 TEST CIRCUIT FIGURE 3B. DG407 TEST CIRCUIT
FIGURE 3C. MEASUREMENT POINTS
FIGURE 3. TRANSITION TIME
EN
A3
DG406
GND
A2
A1
S1
S2 - S15
S16
D
V-
V+
±
±10V
VO
35pF30050
+15V
+2.4V
-15V
A0
10V
LOGIC
INPUT
EN
A0
DG407
GND
A1
A2
S1B
†
S8B
DB
V-
V+ ±10V
VO
35pF30050
+15V
+2.4V
-15V
† = S1A - S8A, S2B - S7B, DA
±
10V
LOGIC
INPUT
LOGIC
INPUT
SWITCH
OUTPUT
VO
3V
VS1B
50%
tr < 20ns
tf < 20ns
tTRANS
50%
0V
0V
VS8B
tTRANS
S8 ON
80%
80%
S1 ON
VS8
VS1
DG406, DG407
FN3116 Rev 11.00 Page 8 of 15
October 1, 2013
FIGURE 4A. DG406 TEST CIRCUIT FIGURE 4B. DG407 TEST CIRCUIT
FIGURE 4C. MEASUREMENT POINTS
FIGURE 4. ENABLE SWITCHING TIMES
FIGURE 5A. TEST CIRCUIT FIGURE 5B. MEASUREMENT POINTS
FIGURE 5. BREAK-BEFORE-MAKE INTERVAL
Test Circuits and Waveforms (Continued)
EN
A3
DG406
GND
A2
A1
S1
S2 - S16
D
V-
V+ -5V
VO
35pF30050
+15V
-15V
A0
LOGIC
INPUT VIN
EN
A0
DG407
GND
A1
A2S1B
†
DA AND DB
V-
V+ -5V
VO
35pF30050
+15V
-15V
† = S1A - S8A, S2B - S8B, DA
LOGIC
INPUT VIN
LOGIC
INPUT
SWITCH
OUTPUT
VO
3V
VO
50%
tr < 20ns
tf < 20ns
tON(EN)
0V
50%
tOFF(EN)
90%
0V
VIN
VO
EN
A3
DG406
GND
A2
A1
ALL S
D,
V-
V+
+5V (VS)
VO
35pF30050
+15V
+2.4V
-15V
A0
DG407
AND DA
DB
LOGIC
INPUT
LOGIC
INPUT
SWITCH
OUTPUT
VO
3V
VS
tr < 20ns
tf < 20ns
tOPEN
0V
0V
80%
DG406, DG407
FN3116 Rev 11.00 Page 9 of 15
October 1, 2013
Typical Performance Curves
FIGURE 6. rDS(ON) vs VD AND SUPPLY FIGURE 7. rDS(ON) vs VD AND TEMPERATURE
FIGURE 8. rDS(ON) vs VD AND SUPPLY FIGURE 9. ID, IS LEAKAGE CURRENTS vs ANALOG VOLTAGE
FIGURE 10. ID, IS LEAKAGE vs TEMPERATURE FIGURE 11. SWITCHING TIMES vs BIPOLAR SUPPLIES
±5V
±8V
±10V
±12V
±15V
±20V
160
140
120
100
80
60
40
20
0
-20 -16 -12 -8 -4 0 4 8 12 16 20
VD, DRAIN VOLTAGE (V)
rDS(ON), ON RESISTANCE ()
+125°C
-40°C
-55°C
+25°C
+85°C
0°C
V+ = 15V
V- = -15V
80
70
60
50
40
30
20
10
0
-15 -10 -5 5 10015
VD, DRAIN VOLTAGE (V)
rDS(ON), ON-RESISTANCE ()
V- = 0V
V+ = 7.5V
10V
12V
15V 20V 22V
240
200
160
120
80
40
0048121620
VD, DRAIN VOLTAGE (V)
rDS(ON), ON-RESISTANCE ()
-10 -5 5 10015
VS, VD, SOURCE DRAIN VOLTAGE (V)
V+ = 15V, V- = -15V
VS = -VD FOR ID(OFF)
VD = VS(OPEN) FOR ID(ON)
IS(OFF)
DG406 ID(ON), ID(OFF)
-15
120
80
40
0
-40
-80
-120
ID, IS, CURRENT (pA)
DG407 ID(ON), ID(OFF)
V+ = 15V, V- = -15V
VS OR VD = 10V
IS(OFF)
ID(ON), ID(OFF)
100nA
10nA
1nA
100pA
10pA
1pA
0.1pA
ID, IS, CURRENT (A)
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE (oC)
350
300
250
200
150
100
50
05101520
VSUPPLY, SUPPLY VOLTAGE (V)
TIME (ns)
tTRANS
tON(EN)
tOFF(EN)
DG406, DG407
FN3116 Rev 11.00 Page 10 of 15
October 1, 2013
FIGURE 12. SWITCHING TIMES vs SINGLE SUPPLY FIGURE 13. OFF-ISOLATION vs FREQUENCY
FIGURE 14. SUPPLY CURRENTS vs SWITCHING FREQUENCY FIGURE 15. tON/tOFF vs TEMPERATURE
FIGURE 16. SWITCHING THRESHOLD vs SUPPLY VOLTAGE
Typical Performance Curves (Continued)
700
600
500
400
300
200
100
05101520
V+, SUPPLY VOLTAGE (V)
TIME (ns)
tTRANS
tON(EN)
tOFF(EN)
V- = 0V
1k 10k 1M100k 10M
f, FREQUENCY (Hz)
100
-140
-120
-100
-80
-60
-40
-20
ISOL (dB)
0
100 1K 100K 1M10K 10M
f, FREQUENCY (Hz)
EN = 5V, AX = 0V OR 5V
IGND
10
10
8
6
0
-4
-8
-10
I, CURRENT (mA)
I+
I-
4
2
-2
-6
300
280
260
240
220
200
140
120
60
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE (°C)
TIME (ns)
180
160
100
80
tTRANS
tON(EN)
tOFF(EN)
V+ = 15V, V- = -15V
5101520
VSUPPLY, SUPPLY VOLTAGE (V)
0
0
1
2
3
VA,(V)
DG406, DG407
FN3116 Rev 11.00 Page 11 of 15
October 1, 2013
Die Characteristics
DIE DIMENSIONS:
2490µm x 4560µm x 485µm
METALLIZATION:
Type: SiAl
Thickness: 12kÅ ±1kÅ
PASSIVATION:
Type: Nitride
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
9.1 x 104 A/cm2
Metallization Mask Layout
DG407
A0ENA1
A2
NCGND
S8A
S7A
S6A
S5A
S4A
S3A
S2A
S1A
V-DA
DBV+
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
DG406, DG407
FN3116 Rev 11.00 Page 12 of 15
October 1, 2013
Die Characteristics
DIE DIMENSIONS:
2490µm x 4560µm x 485µm
METALLIZATION:
Type: SiAl
Thickness: 12kÅ ±1kÅ
PASSIVATION:
Type: Nitride
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
9.1 x 104 A/cm2
Metallization Mask Layout
DG406
V-
S16
DNC V+
S5
A0EN
S7
S6
S5
S4
S3
S2
S1
A1
A2
A3
GND
S15
S14
S13
S12
S11
S10
S9
DG406, DG407
FN3116 Rev 11.00 Page 13 of 15
October 1, 2013
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
computing and high-end consumer markets. For more information about Intersil, visit our website at www.intersil.com.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting
www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
DATE REVISION CHANGE
October 1, 2013 FN3116.11 Converted to new Intersil template.
Removed obsolete parts from ordering information as follows:
DG406DJ
DG406DY
DG406DY-T
DG407DY
DG407DJ
Added P/N DG407DYZ-T to Ordering Information table.
March 13, 2006 FN3116.9 Redline Release parts added to ordering information.
September 17, 2004 FN3116.8 Pb-free parts added.
August 1, 2000 FN3116.6 Initial Release to web.
DG406, DG407
FN3116 Rev 11.00 Page 14 of 15
October 1, 2013
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JEDEC
seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold
flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be
perpendicular to datum .
7. eB and eC are measured at the lead tips with the leads unconstrained. eC
must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
eA
-C-
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
E28.6 (JEDEC MS-011-AB ISSUE B)
28 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A-0.250 -6.35 4
A1 0.015 -0.39 -4
A2 0.125 0.195 3.18 4.95 -
B0.014 0.022 0.356 0.558 -
B1 0.030 0.070 0.77 1.77 8
C0.008 0.015 0.204 0.381 -
D1.380 1.565 35.1 39.7 5
D1 0.005 -0.13 -5
E0.600 0.625 15.24 15.87 6
E1 0.485 0.580 12.32 14.73 5
e 0.100 BSC 2.54 BSC -
eA0.600 BSC 15.24 BSC 6
eB-0.700 -17.78 7
L0.115 0.200 2.93 5.08 4
N28 289
Rev. 1 12/00
FN3116 Rev 11.00 Page 15 of 15
October 1, 2013
DG406, DG407
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
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For additional products, see www.intersil.com/en/products.html
© Copyright Intersil Americas LLC 2000-2013. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
Small Outline Plastic Packages (SOIC)
a
INDEX
AREA
E
D
N
123
-B-
0.25(0.010) C AMBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H0.25(0.010) BM M
(1.50mm)
(9.38mm)
(1.27mm TYP) (0.51mm TYP)
TYPICAL RECOMMENDED LAND PATTERN
M28.3 (JEDEC MS-013-AE ISSUE C)
28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.0200 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.6969 0.7125 17.70 18.10 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.01 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N28 287
0o8o0o8o-
Rev. 1, 1/13