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High Frequency 50 GHz Thin Film Chip Resistor
DESIGN SUPPORT TOOLS
Those miniaturized components are designed in such a way
that their internal reactance is very small. When correctly
mounted and utilized, they function as almost pure resistors
on a very large range of frequency, up to 50 GHz.
FEATURES
Operating frequency 50 GHz
Thin film microwave resistors
SMD wraparound or flip chip resistor
Small size, down to 20 mils by 16 mils
Edged trimmed block resistors
Pure alumina substrate (99.5 %)
Ohmic range: 10R to 500R
Design kits available
Small internal reactance (LC down to 1 × 10-24)
Tolerance 1 %, 2 %, 5 %, 10 %
TCR: 100 ppm/°C in (-55 °C, +155 °C) temperature range
Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
Notes
(1) For CH0402 and CH0603 with P termination, A dimension is increased by 0.2 mm
(2) + or - 0.07 mm
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Available
Models
STANDARD ELECTRICAL SPECIFICATIONS
MODEL SIZE
RESISTANCE
RANGE
RATED POWER
Pn
W
LIMITING
ELEMENT
VOLTAGE
V
TOLERANCE
± %
TEMPERATURE
COEFFICIENT
± ppm/°C
CH02016 02016 10 to 500 0.030 30 2, 5, 10 100
CH0402 0402 10 to 500 0.050 37 1, 2, 5, 10 100
CH0603 0603 10 to 500 0.125 50 1. 2, 5, 10 100
DIMENSIONS in millimeters (inches)
CASE SIZE
MAX. TOL.
+ 0.1 (+ 0.004)
MIN. TOL.
- 0.1 (- 0.004)
DIMENSIONS
A (1) BC D/E
MAX. TOL.
+ 0.1 (+ 0.004)
MIN. TOL.
- 0.1 (- 0.004)
MAX. TOL.
+ 0.1 (+ 0.004)
MIN. TOL.
- 0.1 (- 0.004)
MAX. TOL.
+ 0.127 (+ 0.005)
MIN. TOL.
- 0.127 (- 0.005)
MIN. MAX.
02016 0.48 (0.020) 0.39 (0.016) 0.42 (0.02) (2) 0.11 (0.004) 0.15 (0.008)
0402 1.00 (0.040) 0.6 (0.023) 0.5 (0.02) 0.15 (0.006) 0.35 (0.014)
0603 1.52 (0.060) 0.75 (0.030) 0.5 (0.02) 0.25 (0.010) 0.51 (0.020)
A (1)
DD
C
(P) (N) and (G)
A
D
D
C
E
E
B
A
DD
C
(F)
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Note
Suggested land pattern: According to IPC-7351
Dimension and tolerance of land pattern shall be defined by PCB designer; PCB can be designed according to IPC-7351A
“Generic Requirements for Surface Mount Design and Land Pattern Standard”
Example of land pattern: Fabrication allowance, assembly location and min. or max. level density board are not included in the
exemple bellow.
According to IPC-7351A “Generic Requirements for Surface Mount Design and Land Pattern Standard”:
Zmax. = Amin. + 2JT + with C: “Unilateral profile tolerance for the component”;
Gmin. = Fmax. + 2JH - F: ”Unilateral profile tolerance for the board land pattern”;
Xmax. = Bmin. + 2JS + and P: “Diameter of true position placement accuracy to the center of land pattern”.
For rectangular component Flip-Chip mounting, we
suggest:
Note
(1) 1 % tolerance not applicable for case 02016
LAND PATTERN FLIP CHIP TERMINATIONS in millimeters
CHIP SIZE Zmax. Xmax. Gmin.
02016 0.53 0.44 0.15
0402 1.4 0.650 0.4
0603 1.71 0.9 0.760
Gmin.
Zmax.
Xmax.
CA
2F2P2
++
CF
2F2P2
++
CB
2F2P2
++
COMPONENT
JHJS
JT
Land Pattern Footprint
JT (TOE) 0 mm
JH (HELL) 0 mm
JS (SDE) 0 mm
WRAPAROUND TERMINATIONS in millimeters
CHIP SIZE Zmax. Gmin. Xmax.
0402 1.55 0.15 0.73
0603 2.37 0.35 0.98
TOLERANCE VS. OHMIC VALUES
Ohmic range 10 R < 50 50  R < 100 100  R 500
Tolerance 5 %, 10 % 2 %, 5 %, 10 % 1 %, 2 %, 5 %, 10 % (1)
Gmin.
Zmax.
X
max.
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PREFERRED MODELS AND VALUES
Vishay Sfernice highly recommend to use the smallest sizes and flip chip version to get the best performances.
Recommended Values:
10R/18R/25R/50R/75R/100R/150R/180R/200R/250R/330R/500R
Those values are available with a MOQ of 100 pieces.
Other values can be ordered upon request, but higher MOQ will apply: 1000 pieces for CH02016, 500 pieces for CH0402,
50 pieces for CH0603.
Recommended terminations:
F
Recommended tolerance:
2 %
Design kits are available Ex Stock in CH02016 and CH0402 sizes. There are 20 pieces per recommended value. F termination.
5 % tolerance.
Those kits are packaged in pieces of tape and delivered in ESD bags.
PACKAGING
Standard packaging is waffle pack for sizes 0402 and 0603 and plastic tape and reel (low conductivity) for size 02016.
Paper tape and reel is available for size 0402 and either paper tape and reel or plastic tape and reel (low conductivity) for size
0603.
Depending on the type of terminations, parts will be packed differently:
One face:
Gold terminations: Active face up
Tin/silver termination: Active face down
Note
Please refer to Vishay Sfernice Application Note “Guidelines for Vishay Sfernice Resistive and Inductive Products” for soldering
recommendation (document number 52029, 3. Guidelines for Surface Mounting Components (SMD), profile number 3 applies
PACKAGING RULES
Waffle Pack
Can be filled up to maximum quantity indicated in the table
here above, taking into account the minimum order quantity.
When quantity ordered exceeds maximum quantity of a
single waffle pack, the waffle packs are stacked up on the
top of each other and closed by one single cover. To get
“not stacked up” waffle pack in case of ordered quantity
> maximum number of pieces per package: Please consult
Vishay Sfernice for specific ordering code.
Tape and Reel
See Part Numbering information to get the quantity desired
by tape.
SIZE MOQ
NUMBER OF PIECES PER PACKAGE
TAPE WIDTH
WAFFLE PACK
2" X 2"
TAPE AND REEL
Min. Max.
02016 See MOQ mentioned
on preferred models
and values
484
100 5000 8 mm0402 100
0603 100
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Notes
Historical part numbers are not recommended but can still be used for ordering
(1) Gold termination for application in hermetic package
GLOBAL PART NUMBER INFORMATION
New Global Part Numbering: CH0402-50RJF (preferred part number format)
GLOBAL MODEL SIZE OHMIC VALUE TOLERANCE TERMINATION PACKAGING OPTION
CH 02016
0402
0603
10R to 500R F = 1 %
G = 2 %
J = 5 %
K = 10 %
F (Flip Chip):
SnAg over nickel barrier
N (W/A):
SnAg over nickel barrier
(except 02016)
P (one face): (1)
Gold bonding pads
G (W/A): Gold
(except 02016)
For more
information see
Codification of
Packaging table
From
1 to 3 digits.
Leave blank
if no option.
Historical Part Number example: CH02016-100RGFPT1K (tapes of 1K pieces)
CH0402-50RJF (waffle pack)
CODIFICATION OF PACKAGING
WAFFLE PACK (standard packaging for CH0402 and CH0603)
W100 min., 1 mult
PLASTIC TAPE (standard packaging for CH02016 and CH0603)
T100 min., 1 mult
TA 100 min., 100 mult
TB 250 min., 250 mult
TC 500 min., 500 mult
TD 1000 min., 1000 mult
TE 2500 min., 2500 mult
TF Full tape (qunatity depending on size of chips)
PAPER TAPE (standard packaging for CH0402 - available for CH0603)
PT 100 min., 1 mult
PA 100 min., 100 mult
PB 250 min., 250 mult
PC 500 min., 500 mult
PD 1000 min., 1000 mult
PE 2500 min., 2500 mult
PF Full tape (quantity depending on size of chips)
TYPICAL HIGH FREQUENCY PERFORMANCE ELECTRICAL MODEL
CInternal shunt capacitance
LInternal inductance
R Resistance
ZInternal impedance (R, L, C)
LcExternal connection inductance
CgExternal capacitance to ground
LcCg
Z0
C
LR
Z
Z0
Lc
H0402 - 50RCJF 9T 9 9
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The complex impedance of the chip resistor is given by the following equations:
Notes
= 2 x x f
f: Frequency
The chip resistor itself is purely resistive when . The smaller the L x C product the greater the frequency range over
which the resistor looks approximately resistive.
This can be seen on the graphs showing the ratio versus frequency.
R, L and C are relevant to the chip resistor itself.
Lc and Cg also depends on the way the chip resistor is mounted.
It is important to notice that after assembly the external reactance of Lc and Cg will be combined to internal reactance of L and
C. This combination can upgrade or downgrade the HF behavior of the component.
This is why we are displaying two sets of data:
versus frequency curves which aims to show at a glance the intrinsic HF performance of a given chip resistor
S-parameters versus frequency curves relevant to chip resistor when assembled on ideal Z0 impedance transmission line
These lines are terminated with adapted source and load impedance respectively Zs and Zl with Z0 = ZL = Zs (for others
configurations please consult us).
Equivalent circuit for S-parameters:
S-parameters are computed taking into account all the resistive, inductive and capacitive elements (Z total) and Z0 = ZL = Zs = R.
ZR jL R2C L2C2
+
1CR2C 2L
2 L2C4
++
--------------------------------------------------------------------------------------
=
tan 1L R2C L2C2

R
------------------------------------------------------------
=
RL
C
----=
Z
R
--------
Z
R
--------
LcCg
Z0
C
LR
Z total
Z0
Lc
ZS
GZL
Cg
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INTERNAL IMPEDANCE CURVES
0.1 1 10 100
f (GHz)
IZI/R
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
25 Ω
Internal impedance curve for 02016 size (F and P terminations)
10 Ω
50 Ω
75 Ω
100 Ω
150 Ω
200 Ω
250 Ω
500 Ω
0.1 1 10 100
f (GHz)
IZI/R
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
25 Ω
Internal impedance curve for 0402 size (F and P terminations)
10 Ω
50 Ω
75 Ω
100 Ω
150 Ω
200 Ω
250 Ω
500 Ω
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INTERNAL IMPEDANCE CURVES
0.1 1 10 100
f (GHz)
IZI/R
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1 25 Ω
Internal impedance curve for 0402 size (N and G terminations)
10 Ω
75 Ω
100 Ω
150 Ω
200 Ω
250 Ω
500 Ω
50 Ω
0.1 1 10 100
f (GHz)
IZI/R
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
25 Ω
Internal impedance curve for 0603 size (F and P terminations)
10 Ω
50 Ω
75 Ω
100 Ω
150 Ω
200 Ω
250 Ω
500 Ω
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INTERNAL IMPEDANCE CURVES
S-PARAMETER
CH02016 (F and P Terminations)
0.1 1 10 100
f (GHz)
IZI/R
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1 25 Ω
Internal impedance curve for 0603 size (N and G terminations)
10 Ω50 Ω
75 Ω
100 Ω
150 Ω
200 Ω
250 Ω
500 Ω
0.1 1 10 100
f (GHz)
Magnitude (dB)
- 10
- 9
- 8
- 7
- 6
- 5
- 4
- 3
- 2
CH02016 flip chip (Z0 = ZI = Zs = R = 50 Ω)
S21
S11
0.1 1 10 100
f (GHz)
Magnitude (dB)
- 10
- 9
- 8
- 7
- 6
- 5
- 4
- 3
- 2
CH02016 flip chip (Z0 = ZI = Zs = R = 100 Ω)
S21
S11
CH
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S-PARAMETER
CH0402 (F and P Terminations)
CH0402 (N and G Terminations)
CH0603 (F and P Terminations)
0.1 1 10 100
f (GHz)
Magnitude (dB)
- 10
- 9
- 8
- 7
- 6
- 5
- 4
- 3
- 2
CH0402 flip chip (Z0 = ZI = Zs = R = 50 Ω)
S21
S11
0.1 1 10 100
f (GHz)
Magnitude (dB)
- 10
- 9
- 8
- 7
- 6
- 5
- 4
- 3
- 2
CH0402 flip chip (Z0 = ZI = Zs = R = 100 Ω)
S21
S11
0.1 1 10 100
f (GHz)
Magnitude (dB)
- 10
- 9
- 8
- 7
- 6
- 5
- 4
- 3
- 2
CH0402 wraparound (Z0 = ZI = Zs = R = 50 Ω)
S21
S11
0.1 1 10 100
f (GHz)
Magnitude (dB)
- 10
- 9
- 8
- 7
- 6
- 5
- 4
- 3
- 2
CH0402 wraparound (Z0 = ZI = Zs = R = 100 Ω)
S21
S11
0.1 1 10 100
f (GHz)
Magnitude (dB)
- 10
- 9
- 8
- 7
- 6
- 5
- 4
- 3
- 2
CH0603 flip chip (Z0 = ZI = Zs = R = 50 Ω)
S21
S11
0.1 1 10 100
f (GHz)
Magnitude (dB)
- 10
- 9
- 8
- 7
- 6
- 5
- 4
- 3
- 2
CH0603 flip chip (Z0 = ZI = Zs = R = 100 Ω)
S21
S11
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S-PARAMETER
CH0603 (N and G Terminations)
0.1 1 10 100
f (GHz)
Magnitude (dB)
- 10
- 9
- 8
- 7
- 6
- 5
- 4
- 3
- 2
CH0603 wraparound (Z0 = ZI = Zs = R = 50 Ω)
S21
S11
0.1 1 10 100
f (GHz)
Magnitude (dB)
- 10
- 9
- 8
- 7
- 6
- 5
- 4
- 3
- 2
CH0603 wraparound (Z0 = ZI = Zs = R = 100 Ω)
S21
S11
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“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other
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