Rev 2.1 ©2011 Advanced Linear Devices, Inc. 415 Tasman Drive, Sunnyvale, CA 94089-1706 Tel: (408) 747-1155 Fax: (408) 747-1286
www.aldinc.com
GENERAL DESCRIPTION
The ALD1721/ALD1721G is a monolithic CMOS micropower high slew
rate operational amplifier intended for a broad range of precision applica-
tions requiring exremely low input signal power. Input signal power is the
product of input offset voltage and input bias current, which represents the
minimum required power draw from the signal source in order to drive the
input of the operational amplifier. Input signal power is also a figure of
merit in source loading and its associated error, and is a measure of the
basic signal resolution possible through the operational amplifier for a
given signal source. For certain types of signal sources, signal loading
directly translates into a significant distortion or "interface noise equiva-
lent" term.
The ALD1721/ALD1721G is designed to set a new standard in low input
signal power requirements. The typical input loading at its input is 0.05 mV
offset voltage and 0.01 pA input bias current at 25C, resulting in 0.0005
fW input signal power draw. This input characteristic virtually eliminates
any loading effects on most types of signal sources, offering unparalled
accuracy and signal integrity and fidelity. Obviously, for capacitive and
high sensitivity, high impedance signal sources, the ALD1721/
ALD1721G is ideally suited. It is readily suited for +5V single supply (or
±1V to ±5V) systems, with low operating power dissipation, a traditional
strength of CMOS technology. It is offered with industry standard pin
configuration of µA741 and ICL7611 types.
The ALD1721/ALD1721G can operate with rail to rail large signal input
and output voltages with relatively high slew rate. The input voltage can
be equal to or exceed the positive and negative supply voltages while the
output voltage can swing close to these supply voltage rails. This feature
significantly reduces the supply overhead voltage required to operate the
operational amplifier and allows numerous analog serial stages to oper-
ate in a low power supply environment. In addition, the device can
accommodate mixed applications where digital and analog circuits may
operate off the same power supply or battery. Finally, the output stage
can typically drive up to 50pF capacitive and 10KΩ resistive loads.
These features make the ALD1721/ALD1721G a versatile, micropower
high precision operational amplifier that is user friendly and easy to use
with virtually no source loading and zero input-loading induced source
errors. Additionally, robust design and rigorous screening make this
device especially suitable for operation in temperature-extreme environ-
ments and rugged conditions.
FEATURES & BENEFITS
• Lead Free - RoHS compatible
• Robust high-temperature operation
• Guaranteed extremely low input signal
power of 1.5 fW
• Input offset voltage of 0.05 mV typical
(0.15 mV max.)
• Low input bias currents of 0.01pA typical
(10pA max.)
• Rail to rail input and output voltage ranges
• All parameters specified for +5V single
supply or ±2.5V dual supplies
• Unity gain stable, no compensation needed
• High voltage gain -- typically 100V/mV @
±2.5V(100dB)
• Drive as low as 10KΩ load
• Output short circuit protected
• Unity gain bandwidth of 0.7MHz
• Slew rate of 0.7V/µs
• Micro power dissipation
• Suitable for rugged, temperature-extreme
environments
APPLICATIONS
• Voltage amplifier
• Voltage follower/buffer
• Charge integrator
• Photodiode amplifier
• Data acquisition systems
• High performance portable instruments
• Signal conditioning circuits
• Sensor and transducer amplifiers
• Low leakage amplifiers
• Active filters
• Sample/Hold amplifier
• Picoammeter
• Current to voltage converter
Operating Temperature Range
0°C to +70°C0°C to +70°C -55°C to +125°C
8-Pin 8-Pin 8-Pin
Small Outline Plastic Dip CERDIP
Package (SOIC) Package Package
ALD1721SAL ALD1721PAL ALD1721DA
ALD1721GSAL ALD1721GPAL ALD1721GDA
* Contact factory for leaded (non-RoHS) or high temperature versions.
ORDERING INFORMATION
(“L” suffix denotes lead-free (RoHS))
PIN CONFIGURATION
* N/C pins are internally connected. Do not connect externally.
1
2
2
3
4
8
7
6
5
TOP VIEW
N/C
-IN
+IN
N/C
OUT
N/C
V-
V+
TOP VIEW
SAL, PAL, DA PACKAGES
e
EPAD
TM
®
N
A
B
L
E
D
E
PRECISION MICROPOWER CMOS OPERATIONAL AMPLIFIER
ALD1721/ALD1721G
A
DVANCED
L
INEAR
D
EVICES,
I
NC.
ALD1721/ALD1721G Advanced Linear Devices 2 of 9
Supply voltage, V+ 10.6V
Differential input voltage range -0.3V to V+ +0.3V
Power dissipation 600 mW
Operating temperature range SAL, PAL packages 0°C to +70°C
DA package -55°C to +125°C
Storage temperature range -65°C to +150°C
Lead temperature, 10 seconds +260°C
CAUTION: ESD Sensitive Device. Use static control procedures in ESD controlled environment.
Supply VS±1.0 ±5.0 ±1.0 ±5.0 Dual Supply
Voltage V+2.0 10.0 2.0 10.0 V Single Supply
Input Offset VOS 0.05 0.15 0.15 0.35 mV RS ≤ 100KΩ
Voltage 0.6 1.0 mV 0°C ≤ TA ≤ +70°C
Input Offset IOS 0.01 10 0.01 10 pA TA = 25°C
Current 240 240 pA 0°C ≤ TA ≤ +70°C
Input Bias IB0.01 10 0.01 10 pA TA = 25°C
Current 240 240 pA 0°C ≤ TA ≤ +70°C
Input Voltage VIR -0.3 5.3 -0.3 5.3 V V+ = +5V
Range -2.8 2.8 -2.8 2.8 V VS = ±2.5V
Input RIN 1014 1014 Ω
Resistance
Input Offset TCVOS 57µV/°CR
S
≤ 100KΩ
Voltage Drift
Power Supply PSRR 65 80 65 80 dB RS ≤ 100KΩ
Rejection Ratio 65 80 65 80 dB 0°C ≤ TA ≤ +70°C
Common Mode CMRR 65 83 65 83 dB RS ≤ 100KΩ
Rejection Ratio 65 83 65 83 dB 0°C ≤ TA ≤ +70°C
Large Signal AV32 100 32 100 V/ mV RL = 100KΩ
Voltage Gain 1000 1000 V/ mV RL ≥ 1MΩ
20 20 V/ mV RL = 100KΩ
0°C ≤ TA ≤ +70°C
Output VO low 0.001 0.01 0.001 0.01 V RL =1MΩ V+ = +5V
Voltage VO high 4.99 4.999 4.99 4.999 V 0°C ≤ TA ≤ +70°C
Range VO low -2.48 -2.40 -2.48 -2.40 V RL =100KΩ
VO high 2.40 2.48 2.40 2.48 V 0°C ≤ TA ≤ +70°C
Output Short ISC 1 1mA
Circuit Current
Supply Current IS110 200 110 200 µAV
IN = 0V
No Load
Power PD0.6 1.0 0.6 1.0 mW VS = ±2.5V
Dissipation
OPERATING ELECTRICAL CHARACTERISTICS
TA = 25°C VS = ±2.5V unless otherwise specified
1721 1721G Test
Parameter Symbol Min Typ Max Min Typ Max Unit Conditions
ABSOLUTE MAXIMUM RATINGS
ALD1721/ALD1721G Advanced Linear Devices 3 of 9
Input CIN 11pF
Capacitance
Bandwidth BW400 700 400 700 KHz
Slew Rate SR0.33 0.7 0.33 0.7 V/µsA
V
= +1
RL = 100KΩ
Rise time t r 0.2 0.2 µsR
L
= 100KΩ
Overshoot 20 20 % RL =100KΩ
Factor CL = 50pF
Settling Time t s10.0 10.0 µs 0.1%
AV = -1RL=100KΩ
CL = 50pF
1721 1721G Test
Parameter Symbol Min Typ Max Min Typ Max Unit Conditions
Power Supply PSRR 83 83 dB RS ≤ 100KΩ
Rejection Ratio
Common Mode CMRR 83 83 dB RS ≤ 100KΩ
Rejection Ratio
Large Signal AV250 250 V/mV RL =100KΩ
Voltage Gain
Output Voltage VO low -4.98 -4.90 -4.98 -4.90 V RL =100KΩ
Range VO high 4.90 4.98 4.90 4.98 V
Bandwidth BW1.0 1.0 MHz
Slew Rate SR1.0 1.0 V/µsA
V
= +1
CL = 50pF
1721 1721G Test
Parameter Symbol Min Typ Max Min Typ Max Unit Conditions
1721 1721G Test
Parameter Symbol Min Typ Max Min Typ Max Unit Conditions
VS = ±2.5V -55°C ≤ TA ≤ +125°C unless otherwise specified
Input Offset VOS 1.0 2.0 mV RS ≤ 100KΩ
Voltage
Input Offset IOS 2.0 2.0 nA
Current
Input Bias IB2.0 2.0 nA
Current
Power Supply PSRR 60 75 60 75 dB RS ≤ 100KΩ
Rejection Ratio
Common Mode CMRR 60 83 60 83 dB RS ≤ 100KΩ
Rejection Ratio
Large Signal AV15 50 15 50 V/ mV RL = 100KΩ
Voltage Gain
Output Voltage VO low -2.47 -2.40 -2.47 -2.40 V
Range VO high 2.35 2.45 2.35 2.45 V RL = 100KΩ
TA = 25°C VS = ±5.0V unless otherwise specified
TA = 25°C VS = ±2.5V unless otherwise specified (cont'd)
OPERATING ELECTRICAL CHARACTERISTICS (cont'd)
ALD1721/ALD1721G Advanced Linear Devices 4 of 9
Design & Operating Notes:
1. The ALD1721/ALD1721G CMOS operational amplifier uses a 3 gain
stage architecture and an improved frequency compensation
scheme to achieve large voltage gain, high output driving capability,
and better frequency stability. The ALD1721/ALD1721G is internally
compensated for unity gain stability. This compensation produces a
clean single pole roll off in the gain characteristics while providing for
more than 70 degrees of phase margin at the unity gain frequency,
reducing or eliminating low levels of oscillation or ringing with many
types of loading conditions.
2. The ALD1721/ALD1721G has complementary p-channel and n-
channel input differential stages connected in parallel to accomplish
rail to rail input common mode voltage range. With different ranges
of common mode input voltage, one or both of the two differential
stages is active. The transition between the two input stages takes
place at about 1.5V below the positive supply voltage. Input offset
voltage trimming on the ALD1721/ALD1721G is made when the
input voltage is symmetrical to the supply voltages, this internal
transition switching does not affect a variety of applications such as
an inverting amplifier or non-inverting amplifier with a gain larger
than 2.5 (5V operation), where the common mode voltage does not
make excursions above this switching point. If the operational
amplifier is connected as a unity gain buffer, and full input and/or
output rail to rail range is used, then provision should be made to
allow for slight input offset voltage variations. Likewise the output
has push-pull(source-sink) output stages working in tandem to
provide full (see note 4) rail to rail output. In addition, the source and
sink currents are designed to provide symmetrical drives to the load.
3. The input bias and offset currents are essentially input protection
diode reverse bias leakage currents, and are typically less than
0.01pA at room temperature. This low input bias current assures
that the analog signal from the source will not be distorted by input
bias currents. Normally, this extremely high input impedance of
greater than 1014Ω would be limited by the source impedance which
would limit the node impedance. However, for applications where
source impedance is also very high, it may be necessary to limit
noise and hum pickup through proper ground shielding.
4. The output stage consists of class AB complementary output drivers,
capable of driving a low resistance load to either supply rail. The
output voltage swing is limited by the drain to source on-resistance
of the output transistors as determined by the bias circuitry, and the
value of the load resistor. When connected in the voltage follower
configuration, the oscillation resistant feature, combined with the rail
to rail input and output feature, makes an effective analog signal
buffer for medium to high source impedance sensors, transducers,
and other circuit networks.
5. The ALD1721/ALD1721G operational amplifier has been designed
to provide static discharge protection. Internally, the design has
been carefully implemented to minimize latch up. However, care
must be exercised when handling the device to avoid strong static
fields that may degrade a diode junction, causing increased input
leakage currents. The user is advised to power up the circuit before,
or simultaneously with any input voltages applied, and to limit input
voltages not to exceed 0.3V of the power supply voltage levels at all
times, including during power up and power down cycles.
6. The ALD1721/ALD1721G, with its micropower operation, offers
benefits in reduced power supply requirements, less noise coupling
and current spikes, less thermally induced drift, better overall reli-
ability due to lower self heating, and lower input bias current. It
requires practically no warm up time as the chip junction heats up to
0.1°C or less above ambient temperature under most operating
conditions.
7. The ALD1721/ALD1721G has an internal design architecture that
provides robust high temperature operation. Contact factory for
custom screening versions.
TYPICAL PERFORMANCE CHARACTERISTICS
OPEN LOOP VOLTAGE GAIN AS A
FUNCTION OF LOAD RESISTANCE
10M
LOAD RESISTANCE (Ω)
10K 100K 1M
1000
100
10
1
OPEN LOOP VOLTAGE
GAIN (V/mV)
V
S
= ±2.5V
T
A
= 25°C
COMMON MODE INPUT VOLTAGE RANGE
AS A FUNCTION OF SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
COMMON MODE INPUT
VOLTAGE RANGE (V)
±7
±6
±5
±4
±3
±2
±1
00 ±1 ±2 ±3 ±4 ±5 ±6 ±7
T
A
= 25°C
SUPPLY CURRENT (µA)
SUPPLY CURRENT AS A FUNCTION
OF SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
500
400
200
300
0
100
0±1±2±3±4±5±6
T
A
= -55°C
+25°C
+70°C+125°C
INPUTS GROUNDED
OUTPUT UNLOADED
-25°C
INPUT BIAS CURRENT AS A FUNCTION
OF AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (°C)
100
10
1.0
0.01
0.1
INPUT BIAS CURRENT (pA)
100-25 0 75 1255025-50
1000
V
S
= ±2.5V
ALD1721/ALD1721G Advanced Linear Devices 5 of 9
TYPICAL PERFORMANCE CHARACTERISTICS (cont'd)
LARGE - SIGNAL TRANSIENT
RESPONSE
5V/div
2V/div 5µs/div
V
S
= ±2.5V
T
A
= 25°C
R
L
= 100KΩ
C
L
= 50pF
OPEN LOOP VOLTAGE GAIN AS A FUNCTION
OF FREQUENCY
FREQUENCY (Hz)
1 10 100 1K 10K 1M 10M100K
120
100
80
60
40
20
0
-20
OPEN LOOP VOLTAGE
GAIN (dB)
90
0
45
180
135
PHASE SHIFT IN DEGREES
V
S
= ±2.5V
T
A
= 25°C
OPEN LOOP VOLTAGE GAIN AS A FUNCTION
OF SUPPLY VOLTAGE AND TEMPERATURE
SUPPLY VOLTAGE (V)
1000
100
10
1
OPEN LOOP VOLTAGE
GAIN (V/mV)
0 ±2 ±4 ±6 ±8
-55°C ≤ T
A
≤ +125°C
R
L
= 100KΩ
OUTPUT VOLTAGE SWING AS A FUNCTION
OF SUPPLY VOLTAGE
SUPPLY VOLTAGE (V)
0±1±2±3±4±7±6±5
±6
±5
±4
±3
±2
±1
OUTPUT VOLTAGE SWING (V)
-55°C ≤ T
A
≤ +125°C
R
L
= 100KΩ
LARGE - SIGNAL TRANSIENT
RESPONSE
2V/div
500mV/div 5µs/div
V
S
= ±1.0V
T
A
= 25°C
R
L
= 100KΩ
C
L
= 50pF
SMALL - SIGNAL TRANSIENT
RESPONSE
100mV/div
20mV/div 2µs/div
V
S
= ±2.5V
T
A
= 25°C
R
L
= 100KΩ
C
L
= 50pF
ALD1721/ALD1721G Advanced Linear Devices 6 of 9
TYPICAL APPLICATIONS
Performance waveforms.
Upper trace is the output of a
Wien Bridge Oscillator. Lower
trace is the output of Rail-to-rail
voltage follower.
0V
+5V
OUTPUT
0V
+5V
INPUT
RAIL-TO-RAIL WAVEFORM
RAIL-TO-RAIL VOLTAGE COMPARATOR
WIEN BRIDGE OSCILLATOR (RAIL-TO-RAIL)
SINE WAVE GENERATOR
LOW VOLTAGE INSTRUMENTATION AMPLIFIER
-
+
OUTPUT
50K
0.1µF
+5V
10M
+5V
VIN
RAIL-TO-RAIL VOLTAGE FOLLOWER/BUFFER
HIGH INPUT IMPEDANCE RAIL-TO-RAIL
PRECISION DC SUMMING AMPLIFIER
+
-
+2.5V
-2.5V
R
F
= 5M
I
PHOTODIODE
V
OUT
= 1 X R
F
R
L
= 100K
PHOTO DETECTOR CURRENT TO
VOLTAGE CONVERTER
-
+
OUTPUT
5V
0.1µF
* See Rail to Rail Waveform
0≤ V
IN
≤ 5V
V
IN
Z
IN
= 10
12
Ω
~
10K
-
+
OUTPUT
10K
10K
+2.5V
-2.5V
.01µF
1
2πR
C
f = ~ 1.6KHz
C = .01µFR = 10K
* See Rail to Rail Waveform
~
50K
100K
100K
f max = 20KHz
-40mV ≤ V
IN
≤ 40mV
0.1µF
0.1µF
V+
V-
GAIN = 25 V- ≤ V
OUT
≤ V+. All resistors are 1%.
V+ = +1.0V, V- = -1.0V. Short circuit input current 1µA.
-
+
V-
-
+
100K
100K
1M
0.1µF
V+
0.1µF
-
500K
0.1µF
V+
V+ 1M
+
1M V-
V- 0.1µF
V
OUT
1M
- 2.5V
10M
10M
10M
10M
10M
10M
R
IN
= 10MΩ Accuracy limited by resistor tolerances and input offset voltage
+2.5V
-
+
0.1µF
0.1µFV
OUT
V- ≤ V
IN
≤ V+
V- ≤ V
OUT
≤ V+
V
1
V
4
V
3
V
2
V
OUT
= V
1
+ V
2
- V
3
- V
4
ALD1721/ALD1721G Advanced Linear Devices 7 of 9
8 Pin Plastic SOIC Package
Millimeters Inches
Min Max Min MaxDim
A
A
1
b
C
D-8
E
e
H
L
S
1.75
0.25
0.45
0.25
5.00
4.05
6.30
0.937
8°
0.50
0.053
0.004
0.014
0.007
0.185
0.140
0.224
0.024
0°
0.010
0.069
0.010
0.018
0.010
0.196
0.160
0.248
0.037
8°
0.020
1.27 BSC 0.050 BSC
1.35
0.10
0.35
0.18
4.69
3.50
5.70
0.60
0°
0.25
ø
SOIC-8 PACKAGE DRAWING
L
C
H
S (45°)
ø
e
A
A
1
b
D
S (45°)
E
ALD1721/ALD1721G Advanced Linear Devices 8 of 9
8 Pin Plastic DIP Package
Millimeters Inches
Min Max Min MaxDim
A
A
1
A
2
b
b
1
c
D-8
E
E
1
e
e
1
L
S-8
ø
3.81
0.38
1.27
0.89
0.38
0.20
9.40
5.59
7.62
2.29
7.37
2.79
1.02
0°
5.08
1.27
2.03
1.65
0.51
0.30
11.68
7.11
8.26
2.79
7.87
3.81
2.03
15°
0.105
0.015
0.050
0.035
0.015
0.008
0.370
0.220
0.300
0.090
0.290
0.110
0.040
0°
0.200
0.050
0.080
0.065
0.020
0.012
0.460
0.280
0.325
0.110
0.310
0.150
0.080
15°
PDIP-8 PACKAGE DRAWING
b
1
S
b
EE1
D
e
A2
A
1
A
L
ce
1
ø
ALD1721/ALD1721G Advanced Linear Devices 9 of 9
8 Pin CERDIP Package
CERDIP-8 PACKAGE DRAWING
A
A
1
b
b
1
C
D-8
E
E
1
e
e
1
L
L
1
L
2
S
Ø
3.55
1.27
0.97
0.36
0.20
--
5.59
7.73
3.81
3.18
0.38
--
0°
5.08
2.16
1.65
0.58
0.38
10.29
7.87
8.26
5.08
--
1.78
2.49
15°
Millimeters Inches
Min Max Min MaxDim 0.140
0.050
0.038
0.014
0.008
--
0.220
0.290
0.150
0.125
0.015
--
0°
0.200
0.085
0.065
0.023
0.015
0.405
0.310
0.325
0.200
--
0.070
0.098
15°
2.54 BSC
7.62 BSC
0.100 BSC
0.300 BSC
EE
1
C
e
1
ø
s
b
L
D
b
1
e
A
L
2
A
1
L
1
