This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
March 2014 DocID024132 Rev 3 1/22
22
STGIPN3H60-H
SLLIMM™-nano (small low-loss intelligent molded module)
IPM, 3 A - 600 V 3-phase IGBT inverter bridge
Datasheet
-
preliminary data
Features
•IPM 3 A, 600 V, 3-phase IGBT inverter bridge
including control ICs for gate driving and
freewheeling diodes
•Optimized for low electromagnetic interference
•V
CE(sat)
negative temperature coefficient
•3.3 V, 5 V, 15 V CMOS/TTL inputs
comparators with hysteresis and pull down/pull
up resistors
•Undervoltage lockout
•Internal bootstrap diode
•Interlocking function
•Smart shutdown function
•Comparator for fault protection against
overtemperature and overcurrent
•Op amp for advanced current sensing
•Optimized pin out for easy board layout
Applications
•3-phase inverters for motor drives
•Dish washers, ref rigerator compressors,
heating systems, air-conditioning fans,
draining and recirculation pumps
Description
This intelligent power module implements a
compact, high performance AC motor d rive in a
simple, rugged design. It is composed of six
IGBTs with freewheeling diodes and three half-
bridge HVICs for gate driving, providing low
electromagnetic interference (EMI) characteristics
with optimized switching speed. The package is
optimized for thermal performance and
compactness in built-in motor applications, or
other low power applications where assembly
space is limited. This IPM includes an operational
amplifier, completely uncommitted, and a
comparator that can be used to design a fast and
efficient protection circuit. SLLIMM™ is a
trademark of STMicroelectronics.
NDIP-26L
Table 1. Device summary
Order code Marking Package Packaging
STGIPN3H60-H GIPN3H60-H NDIP-26L Tube
www.st.com
Contents STGIPN3H60-H
2/22 DocID024132 Rev 3
Contents
1 Internal schematic diagram and pin configuration . . . . . . . . . . . . . . . . 3
2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3.1 Control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3.2 Waveform definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Smart shutdown function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.1 Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DocID024132 Rev 3 3/22
STGIPN3H60-H Internal schematic diagram and pin configuration
1 Internal schematic diagram and pin configuration
Figure 1. Internal schematic diagram
GND
VCC
HIN
VBOOT
LVG
OUT
HVG
CIN
GND
VCC
HIN
SD-OD
LIN
VBOOT
LVG
OUT
HVG
GND
OPOUT
OP-
VCC
HIN
VBOOT
LVG
OUT
HVG
OP+
LIN U
SD-OD
HIN U
Vcc U
CIN
LIN V
HIN V
Vcc V
OP-
OPOUT
OP+
LIN W
HIN W
Vcc W
SD-OD
GND N W
W, OUT W
Vboot W
N V
V, OUT V
P
Vboot V
N U
U,OUT U
Vboot U
PIN 1
PIN 16 PIN 17
PIN 26
SD-OD
LIN
SD-OD
LIN
AM09916v2
Internal schematic diagram and pin configuration STGIPN3H60-H
4/22 DocID024132 Rev 3
Table 2. Pin description
Pin Symbol Description
1 GND Ground
2SD / OD Shut down logic i nput (active low) / ope n drain (com parator output)
3V
CC
W Low voltage power supply W phase
4 HIN W High side logic in put for W phase
5 LIN W Low side logic input for W phase
6 OP+ Op amp non inverting input
7OP
OUT
Op amp outpu t
8 OP- Op amp inverting input
9V
CC
V Low voltage power supply V phase
10 HIN V High side logic input for V phase
11 LIN V Low side logic input for V phase
12 CIN Comparator input
13 V
CC
U Low voltage power supply for U phase
14 HIN U High side logic input for U phase
15 SD / OD Shut down logic i nput (active low) / ope n drain (com parator output)
16 LIN U Low side logic input for U phase
17 V
BOOT
U Bootstrap voltage for U phase
18 P Positive DC input
19 U, OUT
U
U phase output
20 N
U
Negative DC input for U phase
21 V
BOOT
V Bootstrap voltage for V phase
22 V, OUT
V
V phase output
23 N
V
Negative DC input for V phase
24 V
BOOT
W Bootstrap voltage for W phase
25 W, OUT
W
W phase output
26 N
W
Negative DC input for W phase
DocID024132 Rev 3 5/22
STGIPN3H60-H Internal schematic diagram and pin configuration
Figure 2. Pin layout (top view)
(*) Dummy pin internally connected to P (positive DC input).
Electrical ratings STGIPN3H60-H
6/22 DocID024132 Rev 3
2 Electrical ratings
2.1 Absolute maximum ratings
Table 3. Inverter part
Symbol Parameter Value Unit
V
CES
Each IGBT collector em itter voltage (V
IN(1)
= 0)
1. Applied between
HIN
i
, LIN
i and
GND
for i = U, V, W
600 V
± I
C (2)
2. Calculated according to the iterative formula:
Each IGBT continuous collector current
at T
C
= 25°C 3A
± I
CP (3)
3. Pulse width limited by max junction temperature
Each IGBT pulsed collector current 18 A
P
TOT
Each IGBT total dissipation at T
C
= 25°C 8 W
Table 4. Control part
Symbol Parameter Min. Max. Unit
V
OUT
Output voltage applied between OUT
U
, OUT
V
,
OUT
W
- GND V
boot
- 21 V
boot
+ 0.3 V
V
CC
Low voltage power supply - 0.3 21 V
V
CIN
Comparator input voltage - 0.3 V
CC
+0.3 V
V
op+
OPAMP non-inverting input - 0.3 V
CC
+0.3 V
V
op-
OPAMP inverting input - 0.3 V
CC
+0.3 V
V
boot
Bootstrap voltage - 0.3 620 V
V
IN
Logic input voltage applied between HIN, LIN
and GND - 0.3 15 V
V
SD/OD
Open drain voltage - 0.3 15 V
ΔV
OUT/dT
Allowed outp ut sle w rate 50 V/ns
Table 5. Total system
Symbol Parameter Value Unit
V
ISO
Isolation withstand voltage applied between each
pin and heatsink plate (AC voltage, t = 60 sec.) 1000 V
T
j
Power chips operating junction temperature -40 to 150 °C
T
C
Module case operation temperature -40 to 125 °C
I
C
T
C
() T
jmax()
T
C
–
R
thj c–
V
CE sat()max()
T
jmax()
I
C
T
C
(),()×
------ ------ ------- -------------------------------------------------------------------------------- ----=
DocID024132 Rev 3 7/22
STGIPN3H60-H Electrical ratings
2.2 Thermal data
Table 6. Thermal data
Symbol Parameter Value Unit
R
thJA
Thermal resistance junction-ambient 50 °C/W
Electrica l characteristics STGIPN3H60-H
8/22 DocID024132 Rev 3
3 Electrical characteristics
T
J
= 25 °C unless otherwise specified.
Note: t
ON
and t
OFF
include the propagation delay time of the internal drive. t
C(ON)
and t
C(OFF)
are
the switching time of IGBT itself under the internally given gate driving condition.
Figure 3. Switching time test circuit
Table 7. Inverter part
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
CE(sat)
Collector-emitter
saturati on vol t age
V
CC
= V
boot
= 15 V, V
IN(1)
= 0 - 5 V,
I
C
= 1 A - 2.15 2.6 V
V
CC
= V
boot
= 15 V, V
IN(1)
= 0 - 5 V,
I
C
= 1 A, T
J
= 125 °C -1.65
I
CES
Collector-cut off current
(V
IN(1)
= 0 “logic state”) V
CE
= 550 V, V
CC
= V
Boot
= 15 V - 250 µA
V
F
Diode forward voltage V
IN(1)
= 0 “logic state”, I
C
= 1 A - 1.7 V
Inductive load switching time and energy
t
on
Turn-on time
V
DD
= 300 V,
V
CC
= V
boot
= 15 V,
V
IN(1)
= 0 - 5 V,
I
C
= 1 A
(see Figure 4)
-275
ns
t
c(on)
Crossover time (on) - 90
t
off
Turn-off time - 890
t
c(off)
Crossover time (off) - 125
t
rr
Rever se r ec ove r y time - 5 0
E
on
Turn-on switching losses - 18 µJ
E
off
Turn-off switching losses - 13
1. Applied between
HIN
i
, LIN
i and
GND
for i = U, V, W.
VBOOT>VCC
RSD
L
IC
VCE
+5V
VCC
INPUT
0
1
BUS
Lin
/SD
Hin
Vcc
DT LVG
HVG
OUT
BOOT
CP+GND
AM06019v3
DocID024132 Rev 3 9/22
STGIPN 3H6 0-H Electri cal characterist ics
Note: Figure 4 “Switching time definition” refers to HIN, LIN inputs (active high).
3.1 Control part
Figure 4. Switching time definition
V
CE
I
C
I
C
V
IN
t
ON
t
C(ON)
VIN(ON) 10% IC 90% IC 10% VCE
(a) turn-on (b) turn-off
t
rr
100% IC 100% IC
V
IN
V
CE
t
OFF
t
C(OFF)
VIN(OFF) 10% VCE 10% IC
AM09223V1
Table 8. Low voltage power supply (V
CC
= 15 V unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
CC_hys
V
CC
UV hysteresis 1.2 1.5 1.8 V
V
CC_thON
V
CC
UV turn ON threshold 11.5 12 12.5 V
V
CC_thOFF
V
CC
UV turn OFF threshold 10 10.5 11 V
I
qccu
Undervoltage quiescent
supply current
V
CC
= 10 V
SD/OD = 5 V; LIN = 0;
H
IN
= 0, C
IN
= 0 150 µA
I
qcc
Quiescent cur rent V
cc
= 15 V
SD/OD = 5 V; LIN = 0;
H
IN
= 0, C
IN
= 0 1mA
V
ref
Internal com p a rato r (CIN)
reference voltage 0.5 0.54 0.58 V
Electrica l characteristics STGIPN3H60-H
10/22 DocID024132 Rev 3
Table 9. Bootstrapped voltage (V
CC
= 15 V unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
BS_hys
V
BS
UV
hysteresis 1.2 1.5 1.8 V
V
BS_thON
V
BS
UV
turn ON threshold 11.1 11.5 12.1 V
V
BS_thOFF
V
BS
UV
turn OFF threshold 9.8 10 10.6 V
I
QBSU
Undervoltage V
BS
quiescent
current
V
BS
< 9 V
SD/OD = 5 V; LIN = 0
HIN = 5 V; C
IN
= 0 70 110 µA
I
QBS
V
BS
quiescent current V
BS
= 15 V
SD/OD = 5 V; LIN = 0
HIN = 5 V; C
IN
= 0 200 300 µA
R
DS(on)
Boot s trap driver on res istance LVG ON 120 Ω
Table 10. Logic inputs (V
CC
= 15 V unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
il
Low logic level voltage 0.8 1.1 V
V
ih
High logic level voltage 1.9 2.25 V
I
HINh
HIN logic “1” input bias current HIN = 15 V 20 40 100 µA
I
HINl
HIN logic “0” input bias current HIN = 0 V 1 µA
I
LINh
LIN logic “1” input bias current LIN = 15 V 20 40 100 µA
I
LINl
LIN logic “0” input bias current LIN = 0 V 1 µA
I
SDh
SD logic “0” input bias current SD = 15 V 30 120 300 µA
I
SDl
SD logic “1” input bias current SD = 0 V 3 µA
Dt Dead time see Figure 5 180 ns
DocID024132 Rev 3 11/22
STGIPN 3H6 0-H Electri cal characterist ics
Table 11. OPAMP characteristics (V
CC
= 15 V unless otherwise specified)
Symbol Parameter Test condition Min. Typ. Max. Unit
V
io
Input offset voltage V
ic
= 0 V, V
o
= 7.5 V 6 mV
I
io
Input offset current V
ic
= 0 V, V
o
= 7.5 V 440nA
I
ib
Input bias current
(1)
100 200 nA
V
icm
Input common mode voltage
range 0V
V
OL
Low level output voltage R
L
= 10 kΩ to V
CC
75 150 mV
V
OH
High level output voltage R
L
= 10 kΩ to GND 14 14.7 V
I
o
Output short circuit current
Source,
V
id
= +1; V
o
= 0 V 16 30 mA
Sink,
V
id
= -1; V
o
= V
CC
50 80 mA
SR Slew rate V
i
= 1 - 4 V; C
L
= 100 pF;
unity gain 2.5 3.8 V/μs
GBWP Gain bandwidth product V
o
= 7.5 V 8 12 MHz
A
vd
Large signal voltage gain R
L
= 2 kΩ70 85 dB
SVR Supply voltage rejection ratio vs. V
CC
60 75 dB
CMRR Common mode rejection ratio 55 70 dB
1. The direction of input current is out of the IC.
Table 12. Sense comparator characteristics (V
CC
= 15 V unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit
I
ib
Input bias curr ent V
CIN
= 1 V 3 µA
V
ol
Open drain low level output
voltage I
od
= 3 mA 0.5 V
t
d_comp
Compar ator delay SD/OD pulled to 5 V through
100 kΩ resistor 90 130 ns
SR Slew rate C
L
= 180 pF; R
pu
= 5 kΩ60 V/µsec
t
sd
Shutdown to high / low side
driver propagation delay V
OUT
= 0, V
boot
= V
CC
,
V
IN
= 0 to 3.3 V 50 125 200
ns
t
isd
Comparator triggering to high /
low side driver turn-off
propagation delay
Measured applying a voltage
step from 0 V to 3.3 V to pin
CIN 50 200 250
Electrica l characteristics STGIPN3H60-H
12/22 DocID024132 Rev 3
Note: X: don’t care
Table 13. Truth table
Condition Logic input (V
I
) Output
SD/OD LIN HIN LVG HVG
Shutdown enable
half-brid ge tri-s tate LXXLL
Interlocking
half-brid ge tri-s tate HHHLL
0 “logic state”
half-brid ge tri-s tate HLLLL
1 “logic state”
low side direct driving HHLHL
1 “logic state”
high side direct driving HLHLH
DocID024132 Rev 3 13/22
STGIPN 3H6 0-H Electri cal characterist ics
3.2 Waveform definitions
Figure 5. Dead time and interlocking waveform definitions
INTERLOCKING
INTERLOCKING
INTERLOCKING
INTERLOCKING
G
Smart shutdown function STGIPN3H60-H
14/22 DocID024132 Rev 3
4 Smart shutdown function
The STGIPN3H60-H integrates a comparator for fault sensing purposes. The comparator
has an internal voltage reference V
REF
connected to the inverting input, while the non-
inverting input, available on pin (CIN), can be connected to an external shunt resistor in
order to implement a simple over-current protection function. When the comparator triggers,
the device is set in shutdown state and both its outputs are set to low-level leading the
halfbridge in tri-state. In the common overcurrent protection architectures the comparator
output is usually connected to the shutdown input through a RC network, in order to provide
a mono-stable circuit, which implements a protection time that follows the fault condition.
Our smart shutdown architecture allows to immediately turn-off the output gate driver in
case of overcurrent, the fault signal has a preferential path which directly switches off the
outputs. The time delay between the fault and the outputs turn-off is no more dependent on
the RC values of the external network connected to the shutdown pin. At the same time the
DMOS connected to the open-drain output is turned on by the internal logic which holds it on
until the shutdown voltage is lower than the logic input lower threshold (V
il
). Finally, the
smart shutdown function provides the possibility to increase the real disable time without
increasing the constant time of the external RC network.
DocID024132 Rev 3 15/22
STGIPN3H60-H Smart shutdown function
Figure 6. Smart shutdown timing waveforms
Please refer to Table 12 for internal propagation delay time details.
Application information STGIPN3H60-H
16/22 DocID024132 Rev 3
5 Application information
Figure 7. Typical application circuit
AM09367v1
DocID024132 Rev 3 17/22
STGIPN3H60-H Application information
5.1 Recommendations
•Input signals HIN, LIN are active high logic. A 375 kΩ (typ.) pull d own resist or is bui lt-in
for each input. If an external RC filter is used, for noise immunity, pay attention to the
variation of the input signal level.
•To prevent input signal oscillation, the wiring of each input should be as short as
possible.
•By integrating an application-specific type HVIC inside the module, direct coupling to
the MCU terminals without an opto-coupler is possible.
•Each capacitor should be located as close as possible to the pins of the IPM.
•Low inductance shunt resistors should be used for phase leg current sensing.
•Elec tr ol yt i c bu s c apacitor s sh ou l d b e m oun t ed a s cl os e t o the mo du l e bu s t erm i na ls as
possible. Additional high frequency ceramic capacitors mounted close to the module
pins will further improve performance.
•The SD/OD signal should be pulled up to 5 V / 3.3 V with an external resistor (see
Section 4: Smart shutdown function for detailed inf o) .
Note: For further details refer to AN4043.
Table 14. Recommended operating conditions
Symbol Parameter Test conditions Min. Typ. Max. Unit
V
PN
Supply voltage Applied between P-Nu,
Nv, Nw 300 500 V
V
CC
Control supply voltage Applied between V
CC
-
GND 13.5 15 18 V
V
BS
High side bias voltage Applied between V
BOOTi
-
OUT
i
for i = U, V, W 13 18 V
t
dead
Blanking time to prevent
Arm-short For each input signal 1.5 µs
f
PWM
PWM input signal -40°C < T
c
< 100°C
-40°C < T
j
< 125°C 25 kHz
T
C
Case operation temperature 100 °C
Package mechanical data STGIPN3H60-H
18/22 DocID024132 Rev 3
6 Package mechanical data
In order to meet environmental requirements , ST offers these devices in different grades of
ECOPACK
®
packages, depending on their level of environmental compliance. ECOPACK
®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK
®
is an ST trademark.
Figure 8. NDIP-26 L drawin g
b1,b3
b,b2
c
c1
BASE METAL
WITH PLATING
SECTION F-F&G-G
D
E
eB1
eB2
e
b
D1
A3
e1
D2
A1
A4
PIN 1 PIN 16
PIN 1
PIN 26 PIN 17
PIN 26 PIN 17
L
A
A2
FF
GG
b2
D3
PIN 16
0.075
0.075
PIN#1 ID
8278949B
DocID024132 Rev 3 19/22
STGIPN3H60-H Package mechanical data
Table 15. NDIP-26L mechanical data
Dim. mm.
Min. Typ. Max.
A4.40
A1 0.80 1.00 1.20
A2 3.00 3.10 3.20
A3 1.70 1.80 1.90
A4 5.70 5.90 6.10
b 0.53 0.72
b1 0.52 0.60 0.68
b2 0.83 1.02
b3 0.82 0.90 0.98
c 0.46 0.59
c1 0.45 0.50 0.55
D 29.05 29.15 29.25
D1 0.50 0.77 1.00
D2 0.35 0.53 0.70
D3 29.55
E 12.35 12.45 12.55
e 1.70 1.80 1.90
e1 2.40 2.50 2.60
eB1 16.10 16.40 16.70
eB2 21.18 21.48 21.78
L 1.24 1.39 1.54
Package mechanical data STGIPN3H60-H
20/22 DocID024132 Rev 3
Figure 9. NDIP-26L tube dimensions (dimensions are in mm.)
Note: Base quantity 17 pcs, bulk quantity 476 pcs.
ANTIS TATIC S 03 PVC
AM10474v1
8313150_A
DocID024132 Rev 3 21/22
STGIPN3H60-H Revision history
7 Revision history
Table 16. Document revision histor y
Date Revision Changes
15-Jan-2013 1Initial rele as e.
02-May-2013 2 Modified: Figur e 3 on page 8, Section 4 on page 14 and
Figu re 6 on page 15 .
14-Mar-2014 3
Updated Figure 3: Switching time test circuit, Table 9:
Bootstrapped voltage (VCC = 15 V unless otherwise specified)
and Table 10: Logic inp ut s (VCC = 15 V unless otherwise
specified).
Updated Section 6: Package mechanical data.
STGIPN3H60-H
22/22 DocID024132 Rev 3
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