4239-00 - Peregrine Semiconductor

Page 1 of 9

RFC

RF1 RF2

CMOS

Control

Driver

CTRL CTRL or VDD

The PE4239 UltraCMOS® RF switch is designed to cover a

broad range of applications from DC through 3.0 GHz. This

reflective switch integrates on-board CMOS control logic with a

low voltage CMOS-compatible control interface, and can be

controlled using either single-pin or complementary control

inputs. Using a nominal +3V power supply voltage, a typical

input 1 dB compression point of +27 dBm can be achieved.

The PE4239 UltraCMOS RF switch is manufactured on

Peregrine’s UltraCMOS process, a patented variation of silicon-

on-insulator (SOI) technology on a sapphire substrate, offering

the performance of GaAs with the economy and integration of

conventional CMOS.

Product Specification

SPDT UltraCMOS® RF Switch

Product Description

Figure 1. Functional Diagram

Figure 2. Package Type SC-70

PE4239

Features

 Single-pin or complementary CMOS

logic control inputs

 +3.0V power supply needed for single-

pin control mode

 Low insertion loss: 0.7 dB at 1.0 GHz,

0.9 dB at 2.0 GHz

 Isolation of 32 dB at 1.0 GHz, 23 dB at

2.0 GHz

 Typical input 1 dB compression point of

+27 dBm

 Ultra-small 6-lead SC-70 package

Parameter Conditions Minimum Typical Maximum Units

Operation Frequency1 DC 3000 MHz

Insertion Loss 1000 MHz

2000 MHz 0.7

0.9

0.85

1.05

dB

Isolation 1000 MHz

2000 MHz

30

21

32

23 dB

dB

Return Loss 1000 MHz

2000 MHz

18

16

20

18 dB

dB

‘ON’ Switching Time 50% CTRL to 0.1 dB of final value, 1 GHz 300 ns

‘OFF’ Switching Time 50% CTRL to 25 dB isolation, 1 GHz 200 ns

Video Feedthrough2 15 mVpp

Input 1 dB Compression 2000 MHz 26 27 dBm

Input IP3 2000 MHz, 14 dBm input power 43 45 dBm

Notes: 1. Device linearity will begin to degrade below 10 MHz.

2. The DC transient at the output of any port of the switch when the control voltage is switched from Low to High or High to Low in a 50Ω test

set-up, measured with 1ns risetime pulses and 500 MHz bandwidth.

Table 1. Electrical Specifications @ +25 °C, VDD = 3V (ZS = ZL = 50Ω)

6-lead SC-70

Product Specification

PE4239

Page 2 of 9

Table 2. Pin Descriptions

Note 1: All RF pins must be DC blocked with an external series

capacitor or held at 0 VDC.

Figure 3. Pin Configuration (Top View) Table 3. Absolute Maximum Ratings

Electrostatic Discharge (ESD) Precautions

When handling this UltraCMOS device, observe

the same precautions that you would use with

other ESD-sensitive devices. Although this device

contains circuitry to protect it from damage due to

ESD, precautions should be taken to avoid

exceeding the specified rating.

Latch-Up Avoidance

Unlike conventional CMOS devices, UltraCMOS

devices are immune to latch-up.

Table 4. DC Electrical Specifications

No.

Name Description

1 RF1 RF1 port (Note 1)

2 GND

Ground connection. Traces should be

physically short and connected to

ground plane for best performance.

3 RF2 RF2 port (Note 1)

4 CTRL Switch control input, CMOS logic level.

5 RFC Common RF port for switch (Note 1)

6 CTRL or

VDD

This pin supports two interface options:

Single-pin control mode. A nominal 3V

supply connection is required.

Complementary-pin control mode. A

complementary CMOS control signal

to CTRL is supplied to this pin. By-

passing on this pin is not required in

this mode.

Symbol Parameter/Conditions Min Max Units

VDD Power supply voltage -0.3 4.0 V

VI Voltage on any input -0.3 VDD+

0.3 V

TST Storage temperature

range -65 150 °C

TOP Operating temperature

range -55 85 °C

PIN Input power (50Ω) 30 dBm

VESD ESD voltage (Human

Body Model) 1500 V

Parameter Min Typ Max Units

VDD Power Supply

Voltage 2.7 3.0 3.3 V

IDD Power Supply Current

(VDD = 3V, VCTRL = 3V) 250 500 nA

Control Voltage High 0.7x VDD V

Control Voltage Low 0.3x VDD V

1

2

3 4

5

6CTRL or VDD

RFC

CTRL

RF1

GND

RF2

. 239

pin 1

Product Specification

PE4239

Page 3 of 9

Control Voltages Signal Path

Pin 6 (CTRL or VDD) = VDD

Pin 4 (CTRL) = High RFC to RF1

Pin 6 (CTRL or VDD) = VDD

Pin 4 (CTRL) = Low RFC to RF2

Table 5. Single-pin Control Logic Truth Table

Table 6. Complementary-pin Control Logic

Truth Table

Control Voltages Signal Path

Pin 6 (CTRL or VDD) = Low

Pin 4 (CTRL) = High RFC to RF1

Pin 6 (CTRL or VDD) = High

Pin 4 (CTRL) = Low RFC to RF2

Control Logic Input

The PE4239 is a versatile RF switch that supports

two operating control modes; single-pin control

mode and complementary-pin control mode.

Single-pin control mode enables the switch to

operate with a single control pin (pin 4) supporting

a +3V CMOS logic input, and requires a dedicated

+3V power supply connection on pin 6 (VDD). This

mode of operation reduces the number of control

lines required and simplifies the switch control

interface typically derived from a CMOS 

Processor I/O port.

Complementary-pin control mode allows the

switch to operate using complementary control

pins CTRL and CTRL (pins 4 & 6), that can be

directly driven by +3V CMOS logic or a suitable 

Processor I/O port. This enables the PE4239 to be

used as a potential alternate source for SPDT RF

switch products used in positive control voltage

mode and operating within the PE4239 operating

limits.

Product Specification

PE4239

Page 4 of 9

Evaluation Kit

The SPDT switch Evaluation Kit board was

designed to ease customer evaluation of the

PE4239 SPDT switch. The RF common port is

connected through a 50Ω transmission line to the

top left SMA connector, J1. Port 1 and Port 2 are

connected through 50Ω transmission lines to the

top two SMA connectors on the right side of the

board, J3 and J2, respectively. A through

transmission line connects SMA connectors J4

and J5. This transmission line can be used to

estimate the loss of the PCB over the

environmental conditions being evaluated.

The board is constructed of a two metal layer FR4

material with a total thickness of 0.031”. The

bottom layer provides ground for the RF

transmission lines. The transmission lines were

designed using a coplanar waveguide with ground

plane model using a trace width of 0.0476”, trace

gaps of 0.030”, dielectric thickness of 0.028”,

metal thickness of 0.0021” and εr of 4.4.

J6 provides a means for controlling DC and digital

inputs to the device. Starting from the lower left

pin, the second pin to the right (J6-3) is connected

to the device V1 or CTRL input. The fourth pin to

the right (J6-7) is connected to the device V2 or

CTRL/VDD input.

Figure 4. Evaluation Board Layout

Figure 5. Evaluation Board Schematic

Peregrine Specification 102/0104

Peregrine Specification 101/0083

Product Specification

PE4239

Page 5 of 9

20

30

40

50

60

20

30

40

50

60

0500 1000 1500 2000 2500 3000

IIP3 (dBm)

1dB Compression Point (dBm)

Frequency (MHz)

Typical Performance Data @ -40 °C to 85 °C (Unless otherwise noted)

Figure 7. Input 1 dB Compression Point & IIP3

(Typical performance @ 25 °C)

Figure 9. Isolation – RFC to RF1 Figure 8. Insertion Loss – RFC to RF2

Figure 6. Insertion Loss – RFC to RF1

-1.5

-1.2

-0.9

-0.6

-0.3

0

0 500 1000 1500 2000 2500 3000

Insertion Loss (dB)

Frequency (MHz)

Insertion Loss (dB)

-40°C

25°C85°C

-100

-80

-60

-40

-20

0

0 500 1000 1500 2000 2500 3000

Isolation (dB)

Frequency (MHz)

-1.5

-1.2

-0.9

-0.6

-0.3

0

0 500 1000 1500 2000 2500 3000

Insertion Loss (dB)

Frequency (MHz)

Insertion Loss (dB)

-40°C

25°C85°C

Product Specification

PE4239

Page 6 of 9

-100

-80

-60

-40

-20

0

0 500 1000 1500 2000 2500 3000

Isolation (dB)

Frequency (MHz)

-100

-80

-60

-40

-20

0

0 500 1000 1500 2000 2500 3000

Isolation (dB)

Frequency (MHz)

Figure 11. Isolation – RF1 to RF2, RF2 to RF1

Figure 13. Return Loss – RF1, RF2 Figure 12. Return Loss – RFC to RF1, RF2

Figure 10. Isolation – RFC to RF2

Typical Performance Data @ -40 °C to 85 °C (Unless otherwise noted)

-40

-30

-20

-10

0

0 500 1000 1500 2000 2500 3000

Return Loss (dB)

Frequency (MHz)

RF2

RF1

-40

-30

-20

-10

0

0 500 1000 1500 2000 2500 3000

Return Loss (dB)

Frequency (MHz)

RF2

RF1

Product Specification

PE4239

Page 7 of 9

Figure 14. Package Drawing

6-lead SC-70

2.05±0.20

1.25±0.10

1.30

0.65 0.225±0.075

2.15±0.15 0.90±0.10

0.05±0.05

Top View Side View

End View

A0.10 C

(2X)

C

0.10 C

0.05 C

SEATING PLANE

B

0.10 C

(2X)

Pin #1 Corner

Recommended Land Pattern

1.95

0.65

0.50 MIN

1.30

0.40 MIN

1 3

64

0.36+0.10

-0.15

0.165±0.085

0.10 A B

ALL FEATURES

DOC-01923

Product Specification

PE4239

Page 8 of 9

Figure 15. Tape and Reel Specifications

Pin 1

Tape Feed Direction

Product Specification

PE4239

Page 9 of 9

Sales Contact and Information

For sales and contact information please visit www.psemi.com.

Advance Information:

The product is in a formative or design stage. The datasheet contains design

target specifications for product development. Specifications and features may change in any manner

without notice.

Preliminary Specification:

The datasheet contains preliminary data. Additional data

may be added at a later date. Peregrine reserves the right to change specifications at any time without

notice in order to supply the best possible product.

Product Specification:

The datasheet contains

final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers

of the intended changes by issuing a CNF (Customer Notification Form).

The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for

the use of this information. Use shall be entirely at the user’s own risk.

No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party.

Peregrine’s products are not designed or intended for use in devices or systems intended for surgical implant, or in

other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product

could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages,

including consequential or incidental damages, arising out of the use of its products in such applications.

The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE are

trademarks of Peregrine Semiconductor Corp. Peregrine products are protected under one or more of the following

U.S. Patents: http://patents.psemi.com.

Table 7. Ordering Information

Order Code Part Marking Description Package Shipping Method

4239-01 239 PE4239-06SC70-7680A 6-lead SC-70 7680 units / Canister

4239-02 239 PE4239-06SC70-3000C 6-lead SC-70 3000 units / T&R

4239-00 PE4239-EK PE4239-06SC70-EK Evaluation Kit 1 / Box

4239-51 239 PE4239G-06SC70-7680A Green 6-lead SC-70 7680 units / Canister

4239-52 239 PE4239G-06SC70-3000C Green 6-lead SC-70 3000 units / T&R