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CY7S1041G
CY7S1041GE
4-Mbit (256K words × 16 bit) Static RAM with
PowerSnooze™ and Error Correcting Code (ECC)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-92576 Rev. *G Revised January 5, 2018
4-Mbit (256K words × 16 bit) Static RAM with PowerSnooze™ and Error Correcting Code (ECC)
Features
■High speed
❐Access time (tAA) = 10 ns / 15 ns
■Ultra-low power Deep-Sleep (DS) current
❐IDS = 15 µA
■Low active and standby currents
❐Active Current ICC = 38-mA typical
❐Standby Current ISB2 = 6-mA typical
■Wide operating voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V,
4.5 V to 5.5 V
■Embedded ECC for single-bit error correction[1]
■1.0-V data retention
■TTL- compatible inputs and outputs
■Error indication (ERR) pin to indicate 1-bit error detection and
correction
■Available in Pb-free 44-pin TSOP II, 44-SOJ and 48-ball
VFBGA
Functional Description
The CY7S1041G is a high-performance PowerSnooze™ static
RAM organized as 256K words × 16 bits. This device features
fast access times (10 ns) and a unique ultra-low power
Deep-Sleep mode. With Deep-Sleep mode currents as low as
15 µA, the CY7S1041G/ CY7S1041GE devices combine the
best features of fast and low- power SRAMs in industry-standard
package options. The device also features embedded ECC. logic
which can detect and correct single-bit errors in the accessed
location.
Deep-Sleep input (DS) must be deasserted HIGH for normal
operating mode.
To perform data writes, assert the Chip Enable (CE) and Write
Enable (WE) inputs LOW, and provide the data and address on
device data pins (I/O0 through I/O15) and address pins (A0
through A17) respectively. The Byte High Enable (BHE) and Byte
Low Enable (BLE) inputs control byte writes, and write data on
the corresponding I/O lines to the memory location specified.
BHE controls I/O8 through I/O15 and BLE controls I/O0 through
I/O7.
To perform data reads, assert the Chip Enable (CE) and Output
Enable (OE) inputs LOW and provide the required address on
the address lines. Read data is accessible on the I/O lines (I/O0
through I/O15). You can perform byte accesses by asserting the
required byte enable signal (BHE or BLE) to read either the
upper byte or the lower byte of data from the specified address
location
The device is placed in a low-power Deep-Sleep mode when the
Deep-Sleep input (DS) is asserted LOW. In this state, the device
is disabled for normal operation and is placed in a low power data
retention mode. The device can be activated by deasserting the
Deep-Sleep input (DS) to HIGH.
The CY7S1041G is available in 44-pin TSOP II, 48-ball VFBGA
and 44-pin (400-mil) Molded SOJ.
Product Portfolio
Product [2] Range VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC,
(mA) Standby, ISB2
(mA)
Deep-Sleep
current (µA)
f = fmax
Typ [3] Max Typ [3] Max Typ [3] Max
CY7S1041G(E)18
Industrial
1.65 V–2.2 V 15 – 40 6 8 – 15
CY7S1041G(E)30 2.2 V–3.6 V 10 38 45
CY7S1041G(E) 4.5–5.5 V 10 38 45
Notes
1. This device does not support automatic write back on error detection.
2. ERR pin is available only for devices which have ERR option “E” in the ordering code. Refer Ordering Information for details.
3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V – 2.2 V),
VCC =3V (for V
CC range of 2.2 V – 3.6 V), and VCC = 5 V (for VCC range of 4.5 V – 5.5 V), TA = 25 °C.
Document Number: 001-92576 Rev. *G Page 2 of 22
CY7S1041G
CY7S1041GE
Logic Block Diagram – CY7S1041G / CY7S1041GE
MEMORY
ARRAY
ROWDECODER
A1
A2
A3
A4
A5
A6
A7
A8
A9
A0
COLUMNDECODER
A10
SENSEAMPLIFIERS
ECCDECODER
A11
A12
A13
A14
A15
A16
A17
ECCENCODER INPUTBUFFER
I/O0‐I/O7
I/O8‐I/O15
BHE
WE
OE
BLE
CE
POWERMANAGEMENT
BLOCK
DS
ERR(Optional)
Document Number: 001-92576 Rev. *G Page 3 of 22
CY7S1041G
CY7S1041GE
Contents
Pin Configurations ........................................................... 4
Maximum Ratings ............................................................. 6
Operating Range ...............................................................6
DC Electrical Characteristics .......................................... 6
Capacitance ......................................................................7
Thermal Resistance .......................................................... 7
AC Test Loads and Waveforms ....................................... 7
Data Retention Characteristics ....................................... 8
Data Retention Waveform ................................................ 8
Deep-Sleep Mode Characteristics ...................................9
AC Switching Characteristics ....................................... 10
Switching Waveforms ....................................................11
Truth Table ...................................................................... 15
ERR Output – CY7S1041GE ...........................................15
Ordering Information ...................................................... 16
Ordering Code Definitions ......................................... 16
Package Diagrams .......................................................... 17
Acronyms ........................................................................ 20
Document Conventions ................................................. 20
Units of Measure ....................................................... 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC®Solutions ....................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Document Number: 001-92576 Rev. *G Page 4 of 22
CY7S1041G
CY7S1041GE
Pin Configurations
Figure 1. 44-pin TSOP II / 44-SOJ pinout, CY7S1041G
Figure 2. 48-ball VFBGA (6 × 8 × 1.0 mm) pinout,
Single Chip Enable without ERR, CY7S1041G [4],
Package/Grade ID: BVJXI [6]
Figure 3. 48-ball VFBGA (6 × 8 × 1.0 mm) pinout,
Single Chip Enable with ERR, CY7S1041GE [4, 5],
Package/Grade ID: BVJXI [6]
A16A1 243
A15A2 342
/OEA3 441
I/O15I/O0 738
/BLE
639
/CE
I/O13I/O2 936
I/O12I/O3 10 35
VSSVCC 11 34
VCCVSS 12 33
I/O11
I/O4 13 32
I/O10
I/O5 14 31
I/O9
I/O6 15 30
I/O8
I/O7 16 29
/DS/WE 17 28
A14A5 18 27
A13A6 19 26
A12
A7 20 25
A11
A8 21 24
A9 22 23
A17A0 144
I/O14I/O1 837
/BHEA4 540
A10
OEBLE A0A2
A1
BHEI/O8A3CEA4I/O0
I/O10
I/O9A5I/O1
A6I/O2
I/O11
VSS A17 I/O3
A7VCC
I/O12
VCC NC I/O4
A16 VSS
I/O13
I/O14 A14 I/O5
A15 I/O6
NCI/O15 A12 WEA13 I/O7
A8
NC A9A11
A10 NC
12 3456
A
B
C
D
E
F
G
H
DS
OEBLE A0A2
A1
BHEI/O8A3CEA4I/O0
I/O10
I/O9A5I/O1
A6I/O2
I/O11
VSS A17 I/O3
A7VCC
I/O12
VCC ERR I/O4
A16 VSS
I/O13
I/O14 A14 I/O5
A15 I/O6
NCI/O15 A12 WEA13 I/O7
A8
NC A9A11
A10 NC
12 3456
A
B
C
D
E
F
G
H
DS
Notes
4. NC pins are not connected internally to the die.
5. ERR is an output pin.
6. Package type BVJXI is JEDEC compliant compared to package type BVXI. The difference between the two is that the higher and lower byte I/Os (I/O[7:0] and I/O[15:8]
balls are swapped.
Document Number: 001-92576 Rev. *G Page 5 of 22
CY7S1041G
CY7S1041GE
Figure 4. 48-ball VFBGA (6 × 8 × 1.0 mm) pinout,
Single Chip Enable without ERR, CY7S1041G [7],
Package/Grade ID: BVXI [9]
Figure 5. 48-ball VFBGA (6 × 8 × 1.0 mm) pinout,
Single Chip Enable with ERR, CY7S1041GE [7, 8],
Package/Grade ID: BVXI [9]
Pin Configurations (continued)
OEBLE A0A2
A1DS
BHEI/O0A3CEA4I/O8
I/O2
I/O1A5I/O10
A6I/O9
I/O3
VSS A17 I/O11
A7VCC
I/O4
VCC ERR I/O12
A16 VSS
I/O5
I/O6A14 I/O13
A15 I/O14
NCI/O7A12 WEA13 I/O15
A8
NC A9A11
A10 NC
12 3456
A
B
C
D
E
F
G
H
Notes
7. NC pins are not connected internally to the die.
8. ERR is an output pin.
9. Package type BVJXI is JEDEC compliant compared to package type BVXI. The difference between the two is that the higher and lower byte I/Os (I/O[7:0] and I/O[15:8]
balls are swapped.
Document Number: 001-92576 Rev. *G Page 6 of 22
CY7S1041G
CY7S1041GE
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –65 C to +150 C
Ambient temperature
with power applied ................................... –55 C to +125 C
Supply voltage
on VCC relative to GND [10] .........................–0.5 V to + 6.0 V
DC voltage applied to outputs
in HI-Z State [10] ..................................–0.5 V to VCC + 0.5 V
DC input voltage [10] ........................... –0.5 V to VCC + 0.5 V
Current into outputs (LOW) ........................................ 20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ................................. > 2001 V
Latch-up current .................................................... > 140 mA
Operating Range
Range Ambient Temperature VCC
Industrial –40 C to +85 C 1.65 V to 2.2 V,
2.2 V to 3.6 V,
4.5 V to 5.5 V
DC Electrical Characteristics
Over the Operating Range of –40 C to +85 C
Parameter Description Test Conditions 10 ns / 15 ns Unit
Min Typ [11] Max
VOH Output HIGH
voltage
1.65 V to 2.2 V VCC = Min, IOH = –0.1 mA 1.4 – – V
2.2 V to 2.7 V VCC = Min, IOH = –1.0 mA 2 – –
2.7 V to 3.0 V VCC = Min, IOH = –4.0 mA 2.2 – –
3.0 V to 3.6 V VCC = Min, IOH = –4.0 mA 2.4 – –
4.5 V to 5.5 V VCC = Min, IOH = –4.0 mA 2.4 – –
4.5 V to 5.5 V VCC = Min, IOH = –0.1 mA VCC – 0.5[13] ––
VOL Output LOW
voltage
1.65 V to 2.2 V VCC = Min, IOL = 0.1 mA – – 0.2 V
2.2 V to 2.7 V VCC = Min, IOL = 2 mA – – 0.4
2.7 V to 3.6 V VCC = Min, IOL = 8 mA – – 0.4
3.6 V to 5.5 V VCC = Min, IOL = 8 mA – – 0.4
VIH[10, 12] Input HIGH
voltage
1.65 V to 2.2 V 1.4 – VCC + 0.2 V
2.2 V to 2.7 V 2 – VCC + 0.3
2.7 V to 3.6 V 2 – VCC + 0.3
3.6 V to 5.5 V 2 – VCC + 0.5
VIL [10, 12] Input LOW
voltage
1.65 V to 2.2 V –0.2 – 0.4 V
2.2 V to 2.7 V –0.3 – 0.6
2.7 V to 3.6 V –0.3 – 0.8
3.6 V to 5.5 V –0.5 – 0.8
IIX Input leakage current GND < VIN < VCC –1 – +1 A
IOZ Output leakage current GND < VOUT < VCC, Output disabled –1 – +1 A
ICC VCC operating supply current VCC = Max, IOUT = 0 mA,
CMOS levels
f = 100 MHz – 38 45 mA
f = 66.7 MHz – 40 40
ISB1 Standby current – TTL inputs Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX
––15mA
Notes
10. VIL (min) = –2.0 V and VIH (max) = VCC + 2 V for pulse durations of less than 20 ns.
11. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = 1.8 V (for VCC range of 1.65 V – 2.2 V),
VCC =3V (for V
CC range of 2.2V – 3.6 V), and VCC = 5 V (for VCC range of 4.5 V – 5.5 V), TA = 25 °C.
12. For the DS pin, VIH (min) is VCC – 0.2 V and VIL (max) is 0.2 V.
13. This parameter is guaranteed by design and not tested.
Document Number: 001-92576 Rev. *G Page 7 of 22
CY7S1041G
CY7S1041GE
ISB2 Standby current – CMOS inputs Max VCC, CE > VCC – 0.2 V,
DS > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
–68mA
IDS Deep-Sleep current Max VCC, CE > VCC – 0.2 V, DS < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
––15µA
DC Electrical Characteristics (continued)
Over the Operating Range of –40 C to +85 C
Parameter Description Test Conditions 10 ns / 15 ns Unit
Min Typ [11] Max
Capacitance
Parameter [14] Description Test Conditions All packages Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VCC(typ) 10 pF
COUT I/O capacitance 10 pF
Thermal Resistance
Parameter [14] Description Test Conditions 48-ball VFBGA 44-pin SOJ 44-pin TSOP II Unit
JA Thermal resistance
(junction to ambient)
Still air, soldered on a
3 × 4.5 inch, four-layer
printed circuit board
31.35 55.37 68.85 C/W
JC Thermal resistance
(junction to case)
14.74 30.41 15.97 C/W
AC Test Loads and Waveforms
Figure 6. AC Test Loads and Waveforms [15]
90%
10%
VHIGH
GND
90%
10%
All Input Pulses
VCC
Output
5 pF*
* Including
JIG and
Scope (b)
R1
R2
Rise Time: Fall Time:
> 1 V/ns
(c)
Output
50
Z
0
= 50
V
TH
30 pF*
* Capacitive Load Consists
of all Components of the
Test Environment
HI-Z Characteristics:
(a)
> 1 V/ns
Parameters 1.8 V 3.0 V 5.0 V Unit
R1 1667 317 317
R2 1538 351 351
VTH VCC/2 1.5 1.5 V
VHIGH 1.8 3.0 3.0 V
Notes
14. Tested initially and after any design or process changes that may affect these parameters.
15. Full-device AC operation assumes a 100-s ramp time from 0 to VCC(min) or 100-s wait time after VCC stabilization.
Document Number: 001-92576 Rev. *G Page 8 of 22
CY7S1041G
CY7S1041GE
Data Retention Characteristics
Over the Operating Range of –40C to +85 C
Parameter Description Conditions[16] Min Max Unit
VDR VCC for data retention 1.0 – V
ICCDR Data retention current VCC = VDR, CE > VCC – 0.2 V, DS > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
–8mA
tCDR [17] Chip deselect to data retention
time
0–ns
tR[17, 18] Operation recovery time 2.2 V < VCC < 5.5 V 10 – ns
VCC < 2.2 V 15 – ns
Data Retention Waveform
Figure 7. Data Retention Waveform [18]
tCDR tR
VDR = 1.0 V
DATA RETENTION MODE
VCC(min) VCC(min)
VCC
CE
Notes
16. DS signal must be HIGH during Data Retention Mode.
17. These parameters are guaranteed by design
18. Full-device operation requires linear VCC ramp from VDR to VCC(min) 100 s or stable at VCC(min) 100 s.
Document Number: 001-92576 Rev. *G Page 9 of 22
CY7S1041G
CY7S1041GE
Deep-Sleep Mode Characteristics
Over the Operating Range of –40 C to +85 C
Parameter Description Conditions Min Max Unit
IDS Deep-Sleep mode current VCC = VCC (max), DS < 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
–15µA
tPDS[19] Minimum time for DS to be LOW
for part to successfully exit
Deep-Sleep mode
100 – ns
tDS[20] DS assertion to Deep-Sleep
mode transition time
–1ms
tDSCD[19] DS deassertion to chip disable If tPDS > tPDS(min) –100s
If tPDS < tPDS(min) –0s
tDSCA DS deassertion to chip access
(Active/Standby)
If tPDS > tPDS(min) 300 – s
If tPDS < tPDS(min)
Figure 8. Active, Standby, and Deep-Sleep Operation Modes
DS
Chip
Access
Mode Active/Standby
Mode
Standby
Mode DeepSleepMode
tDS tDSCD
Allowed NotAllowed Allowed
ENABLE/
DISABLE DON’TCARE
CE DISABLE ENABLE/
DISABLE
Standby
Mode
tDSCA
Active/Standby
Mode
tPDS
Note
19. CE must be pulled HIGH within tDSCD time of DS deassertion to avoid SRAM data loss.
20. After assertion of DS signal, device will take a maximum of tDS time to stabilize to Deep-Sleep current IDS. During this period, DS signal must continue to be asserted
to logic level LOW to keep the device in Deep-Sleep mode.
Document Number: 001-92576 Rev. *G Page 10 of 22
CY7S1041G
CY7S1041GE
AC Switching Characteristics
Over the Operating Range of –40 C to +85 C
Parameter [21] Description 10 ns 15 ns Unit
Min Max Min Max
Read Cycle
tRC Read cycle time 10 – 15 – ns
tAA Address to data valid – 10 – 15 ns
tOHA Data hold from address change 3 – 3 – ns
tACE CE LOW to data valid – 10 – 15 ns
tDOE OE LOW to data valid – 4.5 – 8 ns
tLZOE OE LOW to low impedance [22, 23, 24] 0–0–ns
tHZOE OE HIGH to HI-Z [22, 23, 24] –5–8ns
tLZCE CE LOW to low impedance [22, 23, 24] 3–3–ns
tHZCE CE HIGH to HI-Z [22, 23, 24] –5–8ns
tPU CE LOW to power-up [ 24] 0–0–ns
tPD CE HIGH to power-down [ 24] –10–15ns
tDBE Byte enable to data valid – 4.5 – 8 ns
tLZBE Byte enable to low impedance [22, 23, 24] 0–0–ns
tHZBE Byte disable to HI-Z [22, 23, 24] –6–8ns
Write Cycle [25, 26]
tWC Write cycle time 10 – 15 – ns
tSCE CE LOW to write end 7 – 12 – ns
tAW Address setup to write end 7 – 12 – ns
tHA Address hold from write end 0–0 – ns
tSA Address setup to write start 0 – 0 – ns
tPWE WE pulse width 7 – 12 – ns
tSD Data setup to write end 5 – 8 – ns
tHD Data hold from write end 0 – 0 – ns
tLZWE WE HIGH to low impedance [22, 23, 24] 3–3–ns
tHZWE WE LOW to HI-Z [22, 23, 24] –5–8ns
tBW Byte Enable to End of Write 7–12 –ns
Notes
21. Test conditions assume a signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse
levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3 V). Test conditions for the read cycle use output loading shown in part (a) of Figure 6 on page 7, unless specified otherwise.
22. tHZOE, tHZCE, tHZWE, tHZBE, tLZOE, tLZCE, tLZWE, and tLZBE are specified with a load capacitance of 5 pF as in (b) of Figure 6 on page 7. Transition is measured 200 mV from steady
state voltage.
23. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
24. These parameters are guaranteed by design
25. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL ,DS = VIH and BHE or BLE = VIL. WE, CE, BHE and BLE signals must be LOW
and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE, BHE and BLE signals or LOW transition on DS signal can terminate the operation.
The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
26. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be the sum of tHZWE and tSD.
Document Number: 001-92576 Rev. *G Page 11 of 22
CY7S1041G
CY7S1041GE
Switching Waveforms
Figure 9. Read Cycle No. 1 of CY7S1041G (Address Transition Controlled) [27, 28, 29]
Figure 10. Read Cycle No. 2 of CY7S1041GE (Address Transition Controlled) [27, 28, 29]
ADDRESS
DATA I/O PREVIOUS DATAOUT
VALID DATAOUT VALID
tRC
tOHA
tAA
ADDRESS
DATA I/O PREVIOUS DATAOUT
VALID DATAOUT VALID
tRC
tOHA
tAA
ERR PREVIOUS ERR VALID ERR VALID
tOHA
tAA
Notes
27. The device is continuously selected. OE = VIL, CE = VIL, BHE or BLE or both = VIL.
28. WE is HIGH for read cycle.
29. DS is HIGH for chip access.
Document Number: 001-92576 Rev. *G Page 12 of 22
CY7S1041G
CY7S1041GE
Figure 11. Read Cycle No. 3 (OE Controlled) [30, 31, 32]
Switching Waveforms (continued)
tRC
tHZCE
tPD
tACE
tDOE
tLZOE
tDBE
tLZBE
tLZCE
tPU
HIGH IMPEDANCE DATA OUT
VALID HIGH
IMPEDANCE
ADDRESS
CE
OE
BHE /
BLE
tHZOE
tHZBE
ISB
VCC
SUPPLY
CURRENT
DATA I/O
Notes
30. WE is HIGH for read cycle.
31. Address valid prior to or coincident with CE LOW transition.
32. DS must be HIGH for chip access
Document Number: 001-92576 Rev. *G Page 13 of 22
CY7S1041G
CY7S1041GE
Figure 12. Write Cycle No. 1 (CE Controlled) [33, 34, 35]
Figure 13. Write Cycle No. 2 (WE Controlled, OE LOW) [33, 34, 35, 36]
Switching Waveforms (continued)
ADDRESS
CE
WE
BHE/
BLE
DATA I/O
OE
tWC
tSCE
tAW
tSA
tPWE
tHA
tBW
tHD
tHZOE tSD
DATAIN VALID
ADDRESS
CE
DATA I/O
tWC
tSCE
tHD
tSD
tBW
BHE/
BLE
tAW tHA
tSA tPWE
tLZWE
tHZWE
WE
DATAIN VALID
Notes
33. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL ,DS = VIH and BHE or BLE = VIL. WE, CE, BHE and BLE signals must be LOW
and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE, BHE and BLE signals or LOW transition on DS signal can terminate the operation.
The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
34. Data I/O is in HI-Z state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
35. DS must be HIGH for chip access.
36. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
Document Number: 001-92576 Rev. *G Page 14 of 22
CY7S1041G
CY7S1041GE
Figure 14. Write Cycle No. 3 (WE Controlled) [37, 38, 39]
Figure 15. Write Cycle No. 4 (BLE or BHE Controlled) [37, 38, 39]
Switching Waveforms (continued)
ADDRESS
CE
WE
BHE/BLE
DATA I/O
OE
tWC
tSCE
tAW
tSA
tPWE
tHA
tBW
tHD
tHZOE tSD
DATAIN VALID
Note 40
DATAIN VALID
ADDRESS
CE
WE
DATA I/O
tWC
tSCE
tAW
tSA tBW
tHA
tHD
tHZWE tSD
BHE/
BLE
tPWE
tLZWE
Note 40
Notes
37. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL ,DS = VIH and BHE or BLE = VIL. WE, CE, BHE and BLE signals must be LOW
and DS must be HIGH to initiate a write, and a HIGH transition of any of WE, CE, BHE and BLE signals or LOW transition on DS signal can terminate the operation.
The input data setup and hold timing should be referenced to the edge of the signal that terminates the write.
38. Data I/O is in HI-Z state if CE = VIH, or OE = VIH or DS = VIL or BHE, and/or BLE = VIH.
39. DS must be HIGH for chip access.
40. During this period, the I/Os are in output state. Do not apply input signals.
Document Number: 001-92576 Rev. *G Page 15 of 22
CY7S1041G
CY7S1041GE
Truth Table
DS CE OE WE BLE BHE I/O0–I/O7I/O8–I/O15 Mode Power
HHX
[41] X[41] X[41] X[41] HIGH-Z HIGH-Z Standby Standby (ISB)
H L L H L L Data out Data out Read all bits Active (ICC)
H L L H L H Data out HI-Z Read lower bits only Active (ICC)
H L L H H L HI-Z Data out Read upper bits only Active (ICC)
H L X L L L Data in Data in Write all bits Active (ICC)
H L X L L H Data in HI-Z Write lower bits only Active (ICC)
H L X L H L HI-Z Data in Write upper bits only Active (ICC)
H L H H X X HI-Z HI-Z Selected, outputs disabled Active (ICC)
L[42] X X X X X HI-Z HI-Z Deep-Sleep Deep-Sleep Ultra Low Power
(IDS)
ERR Output – CY7S1041GE
Output [43] Mode
0 Read operation, no single-bit error in the stored data.
1 Read operation, single-bit error detected and corrected.
HI-Z Device deselected or outputs disabled or Write operation.
Notes
41. The input voltage levels on these pins should be either at VIH or VIL.
42. VIL on DS must be < 0.2 V.
43. ERR is an Output pin.If not used, this pin should be left floating.
Document Number: 001-92576 Rev. *G Page 16 of 22
CY7S1041G
CY7S1041GE
Ordering Code Definitions
Ordering Information
Speed
(ns)
Voltage
Range Ordering Code Package
Diagram Package Type (All Pb-free) Operating
Range
10 2.2 V–3.6 V CY7S1041GE30-10BVXI 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), ERR output Industrial
CY7S1041GE30-10BVXIT 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), ERR output, Tape and
Reel
CY7S1041G30-10BVXI 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm)
CY7S1041G30-10BVXIT 51-85150 48-ball VFBGA (6 × 8 × 1.0 mm), Tape and Reel
CY7S1041G30-10VXI 51-85082 44-pin SOJ (400 Mils)
CY7S1041G30-10VXIT 51-85082 44-pin SOJ (400 Mils), Tape and Reel
CY7S1041G30-10ZSXI 51-85087 44-pin TSOP II
CY7S1041G30-10ZSXIT 51-85087 44-pin TSOP II, Tape and Reel
4.5 V–5.5 V CY7S1041G-10ZSXI 51-85087 44-pin TSOP II
CY7S1041G-10ZSXIT 51-85087 44-pin TSOP II, Tape and Reel
SCY 1 -10 I7 04 G1 XX X
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range:
I = Industrial
Pb-free
Package Type: XX = BV or V or ZS
BV = 48-ball VFBGA;
V = 44-pin Molded SOJ;
ZS = 44-pin TSOP II
Speed: 10 ns
Voltage Range: No digits or 30 or 18
No digits = 4.5 V to 5.5 V; 30 = 2.2 V to 3.6 V;18 = 1.65 V to 2.2 V
X = blank or E
blank = without ERR output;
E = with ERR output
Process Technology: Revision Code “G” = 65 nm Technology
Data Width: 1 = × 16-bits
Density: 04 = 4-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
S = Deep-Sleep feature
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
30
XX
Document Number: 001-92576 Rev. *G Page 17 of 22
CY7S1041G
CY7S1041GE
Package Diagrams
Figure 16. 44-pin TSOP II Package Outline, 51-85087
51-85087 *E
Document Number: 001-92576 Rev. *G Page 18 of 22
CY7S1041G
CY7S1041GE
Figure 17. 44-pin SOJ (400 Mils) Package Outline, 51-85082
Package Diagrams (continued)
51-85082 *E
Document Number: 001-92576 Rev. *G Page 19 of 22
CY7S1041G
CY7S1041GE
Figure 18. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
Package Diagrams (continued)
51-85150 *H
Document Number: 001-92576 Rev. *G Page 20 of 22
CY7S1041G
CY7S1041GE
Acronyms Document Conventions
Units of Measure
Acronym Description
BHE Byte High Enable
BLE Byte Low Enable
CE Chip Enable
CMOS Complementary Metal Oxide Semiconductor
ECC Error Correcting Code
I/O Input/Output
OE Output Enable
SRAM Static Random Access Memory
TSOP Thin Small Outline Package
TTL Transistor-Transistor Logic
VFBGA Very Fine-Pitch Ball Grid Array
WE Write Enable
Symbol Unit of Measure
°C degrees Celsius
MHz megahertz
Amicroampere
smicrosecond
mA milliampere
mm millimeter
ns nanosecond
ohm
%percent
pF picofarad
Vvolt
Wwatt
Document Number: 001-92576 Rev. *G Page 21 of 22
CY7S1041G
CY7S1041GE
Document History Page
Document Title: CY7S1041G/CY7S1041GE, 4-Mbit (256K words × 16 bit) Static RAM with PowerSnooze™ and Error Correcting
Code (ECC)
Document Number: 001-92576
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
*D 4867081 NILE 07/31/2015 Changed status from Preliminary to Final.
*E 5020880 VINI 11/19/2015 Updated Pin Configurations:
Removed 44-pin SOJ package related information.
Updated Thermal Resistance:
Removed 44-pin SOJ package related information.
Added 48-ball VFBGA package related information.
Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions.
Updated Package Diagrams:
Removed spec 51-85082 *E.
*F 5432554 NILE 09/10/2016 Added 44-pin SOJ package related information in all instances across the
document.
Updated Logic Block Diagram – CY7S1041G / CY7S1041GE.
Updated Maximum Ratings:
Updated Note 10 (Replaced “2 ns” with “20 ns”).
Updated DC Electrical Characteristics:
Removed Operating Range “2.7 V to 3.6 V” and all values corresponding to
VOH parameter.
Included Operating Ranges “2.7 V to 3.0 V” and “3.0 V to 3.6 V” and all values
corresponding to VOH parameter.
Changed minimum value of VIH parameter from 2.2 V to 2 V corresponding to
Operating Range “3.6 V to 5.5 V”.
Updated Ordering Information:
Updated part numbers.
Updated Ordering Code Definitions.
Updated Package Diagrams:
Added spec 51-85082 *E.
Updated to new template.
Completing Sunset Review.
*G 6015058 AESATMP9 01/05/2018 Updated logo and copyright.
Document Number: 001-92576 Rev. *G Revised January 5, 2018 Page 22 of 22
© Cypress Semiconductor Corporation, 2014-2018. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
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(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product. In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
CY7S1041G
CY7S1041GE
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