LH532000B
FEATURES
•• 262,144 words × 8 bit o rgan izatio n
(Byte mo de)
131 ,0 72 words × 16 b it orga niza tio n
(Word mod e)
•• BYTE i npu t pin sel ects b it co nfiguration
•• Access times: 120 /1 50 ns (MAX.)
•• Low-pow e r con sumptio n :
Ope rating : 27 5 mW (MAX.)
Stan db y: 550 µW (MAX.)
•• Progra mmabl e OE /OE and OE1/OE1/DC
•• Static operation
•• TTL compatible I/O
•• Th ree-state o utputs
•• Sing le +5 V p ower suppl y
•• Packages:
4 0-pi n , 600 -mil DIP
4 0-pi n , 525 -mil SO P
4 8-pi n , 12 × 18 mm2 T SOP (Type I)
••×16 word-wide pinout
DESCRIPTION
The LH532000B is a 2M-bit mask-programmable
ROM with two programmable memory organizations,
byte and word modes. It is fabricated using silicon-gate
C MOS pro cess technolog y.
PIN CONNECTIONS
CMOS 2M (256K × 8 /128K × 1 6) MROM
532000B-1
TOP VIEW
1
2
3
4
7
8
A
2
A
5
48
37
36
35
34
33
30
27
A
7
A
6
5
6
A
3
A
4
32
31
OE
1
/OE
1
/DC
A
10
A
11
A
13
A
15
BYTE
GND
D
14
9
10
11
40
39 A
9
A
1
12 29 D
15
/A
-1
(LSB)
28 D
7
OE/OE
A
0
CE
A
12
40-PIN DIP
40-PIN SOP
13
14
15
16
17
18
19
20
24
21
26
25
23
22
D
13
D
5
D
12
D
4
D
2
D
10
D
9
GND
D
8
D
1
D
0
D
3
D
11
V
CC
A
8
A
14
A
16
D
6
Figu re 1. Pin Connection s for DIP an d
SOP Packages
1
532000B-5
TOP VIEW
2
3
4
5
8
9
A
10
A
13
45
44
43
42
41
40
37
34
A
15
A
14
6
7
A
11
A
12
39
38
D
7
D
3
10
11
12
47
46 D
15
/A
-1
A
9
13 36
35
A
8
48-PIN TSOP (Type I)
14
15
16
17
18
19
20
21
31
28
33
32
30
29
D
2
D
9
D
1
D
8
OE/OE
D
10
GND
48
1
A
16
BYTE
22 27
D
0
GND
23 26
V
CC
24 25
GND
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
CE
GND
D
14
D
13
D
5
D
12
D
4
D
6
V
CC
GND
D
11
GND
NC
NC
NC
OE
1
/OE
1
/DC
NOTE: Reverse bend available on request.
Fi gur e 2. Pin Connecti ons for T SO P Package
LH532000B CMOS 2 M MROM
2
NOTES:
1. D15/A–1 p in becomes LSB address input (A–1) when the b it configuration is set in byte mo de,
and dat a output (D15) when in word m ode. BYTE input pin selects bit configuration.
2. The active l evels of OE/OE and OE1/OE1/DC are mask-program mable.
S elect ing D C all ows t he outputs t o be act ive f or both high and low levels applied to this pin.
I t is recom mended to apply e ith er a HIG H or a LOW to t he DC pin.
532000B-2
A
3
A
2
A
1
A
12
A
11
A
10
A
9
A
8
29
A
7
A
6
V
CC
A
4
MEMORY
MATRIX
(262,144 x 8)
(131,072 x 16)
SENSE AMPLIFIER
GND
A
5
A
13
ADDRESS BUFFER
A
0
ADDRESS DECODER
COLUMN SELECTOR
CE
BUFFER
A
14
A
15
TIMING
GENERATOR
A
16
NOTE: Pin numbers apply to the 40-pin DIP or SOP.
A
-1
D
3
D
2
D
1
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
4
D
5
D
13
D
0
D
14
D
15
DATA SELECTOR/OUTPUT BUFFER
21 11 30
OE
BUFFER
ADDRESS
BUFFER
BYTE/WORD
SWITCHOVER
CIRCUIT
31
OE
1
/OE
1
/DC
OE/OE
CE
BYTE
10
12
1
3
6
7
8
5
4
9
36
37
38
39
2
40
35
34
33
32
20
18
16
14
24
17
15
13
26
19
28
22
23
25
27
29
Figure 3. LH532000B Block Diagram
PIN DESCRIPTI ON
SIG NA L PI N N AM E NO TE
A–1 Address input (BYTE mode) 1
A0 – A16 A ddre ss inp ut
D0 – D15 Da ta output 1
CE Ch ip ena ble in put
OE/OE Ou tpu t e nab le inp ut 2
SIG NA L PIN NA ME NOTE
OE1/OE1/DC Ou tpu t en abl e i npu t o r
Do n’t ca re 2
BYTE By te/ wor d mo de swi tch
VCC Po wer su ppl y (+ 5 V)
GND Ground
CMOS 2M MROM LH532000B
3
TRUT H TABLE
CE OE/OE OE1/OE1BYTE A–1
(D15)DATA OUTPUT A DDRESS INPUT SUPPLY CURRENT
D0 – D7D8 – D15 LSB MSB
H X X X X High-Z High-Z – – Standby (ISB)
L L/H X X X H igh-Z H igh-Z – – Operating (ICC)
L X L/H X X H igh-Z H igh-Z – – Operating (ICC)
L H/L H/L H Input
inhibit D0 – D7D8 – D15 A0A16 Operating (ICC)
L H/L H/L L L D0 – D7High-Z A–1 A16 Operating (ICC)
L H/L H/L L H D8 – D15 High-Z A–1 A16 Operating (ICC)
NOTE:
1. X = H or L, High-Z = Hi gh- impedance.
ABSOLUTE MAXIMUM RATINGS
PARAMETER SYMBOL RATING UNIT
Sup pl y v olt age VCC –0.3 to +7.0 V
Input vol tage VIN –0.3 to VCC + 0.3 V
Out put vo lta ge VOUT –0.3 to VCC + 0.3 V
Ope rat ing te mpe ratu re Topr 0 to +70 °C
Sto rag e t emp era ture Tstg –65 to +150 °C
RECOMM ENDED OPERATING CONDI TIO NS (TA = 0 to +70°C)
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Sup pl y v olt age VCC 4.5 5.0 5.5 V
DC CHARACTERIS TICS (VCC = 5 V ±10 %, TA = 0 to +70°C)
PARAMETER SYMBOL CONDITIONS MIN. TYP. MAX. UNIT NOTE
Input ‘Low’ voltage VIL –0.3 0.8 V
Input ‘High’ voltage VIH 2.2 VCC + 0.3 V
Out put ‘L ow’ v olt age VOL IOL = 2 .0 mA 0.4 V
Out put ‘H igh ’ vol tag e VOH IOH = –400 µA 2.4 V
Inp ut lea kag e c urr ent | ILI | VIN = 0 V to VCC 10 µA
Out put le aka ge cur ren t | ILO | VOUT = 0 V to VCC 10 µA1
Ope rat ing cu rre nt
ICC1 tRC = tRC ( MIN .) 50 mA 2
ICC2 tRC = 1 µs45
I
CC3 tRC = tRC ( MIN .) 45 mA 3
ICC4 tRC = 1 µs40
Sta ndb y c urr ent ISB1 CE = VIH 3mA
I
SB2 CE = VCC - 0.2 V 100 µA
Input capacitance CIN f = 1 MHz
TA = 25°C10 pF
Out put ca pac ita nce COUT 10 pF
NOTES:
1. OE/OE1= V IL, CE/OE/OE1= V IH
2. VIN = V IH or VIL, CE = VIL, outputs open
3. VIN = (V CC - 0.2 V) or 0. 2 V, CE = 0.2 V, outputs o pen
LH532000B CMOS 2 M MROM
4
AC CHARACTERIS TICS (VCC = 5 V ±10%, TA = 0 to +70°C)
PARAMETER SYMBOL 120 ns 150 ns UNIT NOTE
MIN. MAX. MIN. MAX.
Rea d c yc le t ime tRC 120 150 ns
Add res s a cc ess ti me tAA 120 150 ns
Chi p e nab le acc es s ti me tACE 120 150 ns
Out put en abl e d ela y t ime tOE 55 70 ns
Out put ho ld time tOH 510ns
CE to out put in Hig h-Z tCHZ 55 70 ns 1
OE to out put in Hig h-Z tOHZ 55 70 ns
NOTE:
1. T his is t he time r equired for th e output to become high-impedance.
AC TEST CONDITIONS
PARAMETER RATING
Input voltage amplitude 0.6 V to 2.4 V
Input rise/fall time 10 ns
Input reference level 1.5 V
Output reference level 0.8 V and 2.2 V
Output load condition 1TTL +100 pF
CAUTION
To s tabi li z e the pow e r suppl y, i t is recommended that a high-frequency byp ass capaci tor be connecte d betwe en
the VCC pin and the GND pi n.
t
OE
t
AA
(D
0
- D
15
)
t
OHZ
t
CHZ
532000B-3
t
RC
t
ACE
CE
t
OH
DATA VALID
(NOTE 1)
D
0
- D
7
OE/OE
1
OE/OE
1
(A
0
- A
16
)
A-
1
- A
16
1. Data becomes valid after t
AA
, t
ACE
, and t
OE
from address
input, chip enable or output enable, respectively have been met.
2. Applied to byte mode. Signals in parentheses apply to word mode.
NOTES:
(NOTE 1)
(NOTE 2)
(NOTE 2)
Figure 4. Timi ng Diagram
CMOS 2M MROM LH532000B
5
PACKAGE DIAGRAMS
13.45 [0.530]
12.95 [0.510]
0.51 [0.020] MIN.
5.40 [0.213]
4.80 [0.189]
3.55 [0.140]
2.95 [0.116]
2.54 [0.100]
TYP. 0.60 [0.024]
0.40 [0.016]
0.30 [0.012]
0.20 [0.008]
DETAIL
DIMENSIONS IN MM [INCHES]
52.30 [2.059]
51.70 [2.035]
0° TO 15°
MAXIMUM LIMIT
MINIMUM LIMIT
4.55 [0.179]
3.95 [0.156] 15.24 [0.600]
TYP.
40DIP (DIP040-P-0600)
120
2140
40DIP
40-pi n, 600- mil DIP
DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT
MINIMUM LIMIT
40SOP (SOP040-P-0525)
14.50 [0.571]
13.70 [0.539]
11.50 [0.453]
11.10 [0.437] 12.50 [0.492]
26.50 [1.043]
26.10 [1.028]
0.15 [0.006]
1.275 [0.050]
0.20 [0.008]
0.00 [0.000]
1.275 [0.050]
2.90 [0.114]
2.50 [0.098]
0.20 [0.008]
0.10 [0.004]
0.50 [0.020]
0.30 [0.012]
1.27 [0.050]
TYP.
40 21
201
1.40 [0.055]
1.40 [0.055]
40SOP
40-pin, 525-mil SOP
LH532000B CMOS 2 M MROM
6
D 40-pin, 600-mil DIP (DIP040-P-0600)
N 40-pin, 525-mil SOP (SOP040-P-0525)
T 48-pin, 12 x 18 mm
2
TSOP (Type I) (TSOP048-P-1218)
TR 48-pin, 12 x 18 mm
2
TSOP (Type I) Reverse bend (TSOP048-P-1218)
LH532000B
Device Type X
Package
532000B-4
Example: LH532000BD (CMOS 2M (256K x 8 or 128K x 16) Mask Programmable ROM, 40-pin, 600-mil DIP)
CMOS 2M (256K x 8 or 128K x 16) Mask Programmable ROM
ORDERING INFORMATION
DIMENSIONS IN MM [INCHES] MAXIMUM LIMIT
MINIMUM LIMIT
48TSOP (TSOP048-P-1218)
18.40 [0.724]
17.60 [0.693]
16.60 [0.654]
16.20 [0.638] 17.00 [0.669]
12.20 [0.480]
11.80 [0.465] 0.15 [0.006]
0.425 [0.017]
0.20 [0.008]
0.00 [0.000]
1.20 [0.047]
MAX.
1.10 [0.043]
0.90 [0.035]
0.20 [0.008]
0.10 [0.004]
0.30 [0.012]
0.10 [0.004]
48 25
241
0.425 [0.017]
48TSOP
0.50 [0.020]
TYP.
48-pin, 12 × 18 mm2 TSOP (Type I )
CMOS 2M MROM LH532000B
7
