IDT7187S IDT7187L CMOS Static RAM 64K (64K x 1-Bit) Description Features The IDT7187 is a 65,536-bit high-speed static RAM organized as 64K x 1. It is fabricated using IDT's high-performance, high-reliability CMOS technology. Access times as fast as 25ns are available. Both the standard (S) and low-power (L) versions of the IDT7187 provide two standby modes--ISB and ISB1. ISB provides low-power operation; ISB1 provides ultra-low-power operation. The low-power (L) version also provides the capability for data retention using battery backup. When using a 2V battery, the circuit typically consumes only 30W. Ease of system design is achieved by the IDT7187 with full asynchronous operation, along with matching access and cycle times. The device is packaged in an industry standard 22-pin, 300 mil ceramic DIP. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. High speed (equal access and cycle time) - Military: 25/35/45/55/70/85ns (max.) Low power consumption Battery backup operation--2V data retention (L version only) JEDEC standard high-density 22-pin ceramic DIP packaging Produced with advanced CMOS high-performance technology Separate data input and output Input and output directly TTL-compatible Military product compliant to MIL-STD-883, Class B Functional Block Diagram A A VCC A A GND 65,536-BIT MEMORY ARRAY ROW SELECT A A A CS DATAIN DATA OUT COLUMN I/O WE A A A A A A A 2986 drw 01 FEBRUARY 2001 1 (c)2000 Integrated Device Technology, Inc. DSC-2986/09 IDT7187S/L CMOS Static RAM 64K (64K x 1-Bit) Military Temperature Range Pin Configuration Absolute Maximum Ratings(1) A0 A1 A2 A3 A4 A5 A6 A7 1 22 2 21 3 20 4 19 DATAOUT WE GND 5 D22-1 VCC A15 A14 A13 A12 A11 A10 A9 A8 DATAIN CS 18 6 17 7 16 8 15 9 14 10 13 11 12 Symbol Rating Value VTERM Terminal Voltage with Respect to GND -0.5 to +7.0 V Operating Temperature -55 to +125 o C TBIAS Temperature Under Bias -65 to +135 o C TSTG Storage Temperature -65 to +150 o C TA PT Power Dissipation 1.0 W IOUT DC Output Current 50 mA 2986 tbl 03 NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. , 2986 drw 02 DIP Top View Capacitance (TA = +25C, f = 1.0MHz) Parameter(1) Symbol Pin Descriptions CIN Input Capacitance COUT Output Capacitance Max. Unit V IN = 0V 8 pF VOUT = 0V 8 pF NOTE: 1. This parameter is determined by device characterization, but is not production tested. Description A0 - A15 Address Inputs CS Chip Select WE Write Enable VCC Power Symbol DATAIN Data Input VCC Supply Voltage DATAOUT Data Output GND Ground GND Ground Recommended DC Operations Conditions VIH 2986 tbl 01 VIL Parameter Input High Voltage Input Low Voltage Min. Typ. Max. Unit 4.5 5.0 5.5 V 0 0 0 V 2.2 ____ 6.0 V ____ 0.8 V (1) -0.5 2986 tbl 05 NOTE: 1. VIL (min.) = -3.0V for pulse width less than 20ns, once per cycle. Truth Table(1) CS WE Output Power Standby H X High-Z Standby Read L H DOUT Active Write L L High-Z Active NOTE: 1. H = VIH, L = VIL, X = don't care. Conditions 2986 tbl 04 Name Mode Unit Recommended Operating Temperature and Supply Voltage 2986 tbl 02 Grade Temperature GND Vcc Military -55OC to +125OC 0V 5V 10% 2986 tbl 06 2 IDT7187S/L CMOS Static RAM 64K (64K x 1-Bit) Military Temperature Range DC Electrical Characteristics (VCC = 5.0V 10%) IDT7187S Symbol Parameter Test Conditions IDT7187L Min. Max. Min. Max. Unit |ILI| Input Leakage Current V CC = Max., VIN = GND to VCC ____ 10 ____ 5 A |ILO| Output Leakage Current V CC = Max., CS = VIH, VOUT = GND to V CC ____ 10 ____ 5 A VOL Output Low Voltage IOL = 10mA, VCC = Min. ____ 0.5 ____ 0.5 V IOL = 8mA, VCC = Min. ____ 0.4 ____ 0.4 2.4 ____ 2.4 ____ VOH Output High Voltage IOH = -4mA, VCC = Min. V 2986 tbl 07 DC Electrical Characteristics(1) (VCC = 5V 10%, VLC = 0.2V, VHC = VCC - 0.2V) Symbol ICC1 ICC2 ISB ISB1 Power 7187S25 7187L25 7187S35 7187L35 7187S45 7187L45 7187S55 7187L55 7187S70 7187L70 7187S85 7187L85 Unit Operating Power Supply Current CS = VIL, Outputs Open VCC = Max., f = 0(2) S 105 105 105 105 105 105 mA L 85 85 85 85 85 85 Dynamic Operating Current CS = VIL, Outputs Open VCC = Max., f = fMAX(2) S 130 120 120 120 120 120 L 110 100 95 90 90 90 Standby Power Supply Current (TTL Level) CS > VIH, Outputs Open VCC = Max., f = fMAX(2) S 55 50 50 50 50 50 L 50 40 35 30 28 28 Full Standby Power Supply Current (CMOS Level) CS > VHC, VCC = Max., VIN < VLC or VIN > VHC, f = 0(2) S 20 20 20 20 20 20 L 1.5 1.5 1.5 1.5 1.5 1.5 Parameter NOTES: 1. All values are maximum guaranteed values. 2. At f = f MAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change. 6.42 3 mA mA mA 2986 tbl 08 IDT7187S/L CMOS Static RAM 64K (64K x 1-Bit) Military Temperature Range Data Retention Characteristics (L Version Only) (VHC = VCC - 0.2V, VLC = 0.2V) Typ.(1) VCC @ Symbol Parameter V DR VCC for Data Retention ICCDR Data Retention Current tCDR (3) (3) tR Operation Recovery Time IILII(3) Input Leakage Current Test Condition Min. 2.0V 3.0V 2.0V 3.0V Unit ____ 2.0 ____ ____ ____ ____ V CS > VHC VIN > VHC or < VLC Chip Deselect to Data Retention Tim Max. V CC @ ____ 10 15 600 900 A 0 ____ ____ ____ ____ ns ____ ____ ____ ____ ns ____ ____ 2 2 A (2) tRC ____ 2986 tbl 09 NOTES: 1. TA = +25C. 2. tRC = Read Cycle Time. 3. This parameter is guaranteed, but not tested. Low VCC Data Retention Waveform DATA RETENTION MODE VCC 4.5V 4.5V VDR 2V tCDR CS tR VIH VIH VDR 2986 drw 04 AC Test Conditions Input Pulse Levels GND to 3.0V Input Rise/Fall Times 5ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 2986 tbl 10 5V 5V 480 480 DATA OUT DATA OUT 255 255 30pF* 2986 drw 05 5pF* , , 2986 drw 06 Figure 1. AC Test Load Figure 2. AC Test Load (for tHZ, tLZ, tWZ and tOW ) *Includes scope and jig capacitances 4 IDT7187S/L CMOS Static RAM 64K (64K x 1-Bit) Military Temperature Range AC Electrical Characteristics (VCC = 5.0V 10%) 7187S25 7187L25 Symbol Parameter 7187S35/45 7187L35/45 7187S55 7187L55 7187S70 7187L70 7187S85 7187L85 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Read Cycle tRC Read Cycle Time 25 ____ 35/45 ____ 55 ____ 70 ____ 85 ____ ns tAA Address Access Time ____ 25 ____ 35/45 ____ 55 ____ 70 ____ 85 ns Chip Select Access Time ____ 25 ____ 35/45 ____ 55 ____ 70 ____ 85 ns 5 ____ 5 ____ 5 ____ 5 ____ ns ____ ns tACS tOH Output Hold from Address Change 5 ____ tLZ(1) Output Select to Output in Low-Z 5 ____ 5 ____ 5 ____ 5 ____ 5 tHZ(1) Chip Desele ct to Output in High-Z ____ 12 ____ 17/20 ____ 30 ____ 30 ____ 40 ns 0 ____ 0 ____ 0 ____ 0 ____ 0 ____ ns ____ 20 ____ 30/35 ____ 35 ____ 35 ____ 40 ns (1) Chip Sele ct to Power Up Time (1) Chip Deselect to Power Down Time tPU tPD 2986 tbl 11 NOTE: 1. This parameter guaranteed but not tested. Timing Waveform of Read Cycle No. 1(1,2) tRC (5) ADDRESS t AA t OH DATAOUT PREVIOUS DATA VALID DATA VALID 2986 drw 07 Timing Waveform of Read Cycle No. 2(1,3) tRC (5) CS t HZ(4) t ACS t LZ (4) t PU VCC SUPPLY CURRENT HIGH IMPEDANCE DATA VALID DATAOUT t PD ICC I SB 2986 drw 08 NOTES: 1. WE is HIGH for Read cycle. 2. CS is LOW for Read cycle. 3. Address valid prior to or coincident with CS transition LOW. 4. Transition is measured 200mV from steady state voltage with specified loading in Figure 2. 5. All Read cycle timings are referenced from the last valid address to the first transitioning address. 6.42 5 IDT7187S/L CMOS Static RAM 64K (64K x 1-Bit) Military Temperature Range AC Electrical Characteristics (VCC = 5.0V 10%) 7187S25 7187L25 Symbol Parameter 7187S35/45 7187L35/45 7187S55 7187L55 7187S70 7187L70 7187S85 7187L85 Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit Write Cycle tWC Write Cycle Time 25 ____ 35/45 ____ 55 ____ 70 ____ 85 ____ ns tCW Chip Select to End-of-Write 20 ____ 25/40 ____ 50 ____ 55 ____ 65 ____ ns 20 ____ 25/40 ____ 50 ____ 55 ____ 65 ____ ns 0 ____ 0 ____ 0 ____ 0 ____ ns Address Valid to End-of-Write tAW tAS Address Set-up Time 0 ____ tWP Write Pulse Width 20 ____ 20/25 ____ 35 ____ 40 ____ 45 ____ ns tWR Write Recovery Time 0 ____ 0 ____ 0 ____ 0 ____ 0 ____ ns 15/25 ____ 25 ____ 30 ____ 35 ____ ns ____ ns ns tDW Data Valid to End-of-Write 15 ____ tDH Data Hold Time 5 ____ 5 ____ 5 ____ 5 ____ 5 tWZ(1) Write Enab le to Output in High-Z ____ 12 ____ 15/30 ____ 30 ____ 30 ____ 40 0 ____ 0 ____ 0 ____ 0 ____ 0 ____ (1) tOW Output Active from End-of-Write ns 2986 tbl 12 NOTE: 1. This parameter guaranteed but not tested. Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,3,4) tWC ADDRESS tAW CS t WR t WP t AS WE tWZ (5) tOW (5) DATAOUT tDW tDH VALID DATA DATAIN 2986 drw 09 NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 5. Transition is measured 200mV from steady state with a 5pF load (including scope and jig). 6 IDT7187S/L CMOS Static RAM 64K (64K x 1-Bit) Military Temperature Range Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,4) tWC ADDRESS tAW CS t AS ttWR(3) tCW WE t DW tDH VALID DATA DATA IN 2986 drw 10 NOTES: 1. WE or CS must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE. 3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle. 4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state. 5. Transition is measured 200mV from steady state with a 5pF load (including scope and jig). Ordering Information IDT7187 Device Type X XX X X Power Speed Package Process/ Temperature Range B Military (-55C to +125C) Compliant to MIL-STD-883, Class B , D 25 35 45 55 70 85 S L 300 mil Ceramic DIP (D22-1) Speed in nanoseconds Standard Power Low Power 2986 drw 11 6.42 7 IDT7187S/L CMOS Static RAM 64K (64K x 1-Bit) Military Temperature Range Datasheet Document History 11/xx/99 Pp. 1, 2, 8 Pp. 3, 4 Pg. 8 08/09/00 02/01/01 Updated to new format Revised package offerings Removed commercial temperature data Added Datasheet Document History Not recommended for new designs Removed "Not recommended for new designs" CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com The IDT logo is a registered trademark of Integrated Device Technology, Inc. 8 for Tech Support: ipchelp@idt.com 800-345-7015