FEBRUARY 2001
DSC-2986/09
1
©2000 Integrated Device Technology, Inc.
Features
◆◆
◆◆
◆High speed (equal access and cycle time)
– Military: 25/35/45/55/70/85ns (max.)
◆◆
◆◆
◆Low power consumption
◆◆
◆◆
◆Battery backup operation—2V data retention
(L version only)
◆◆
◆◆
◆JEDEC standard high-density 22-pin ceramic
DIP packaging
◆◆
◆◆
◆Produced with advanced CMOS high-performance
technology
◆◆
◆◆
◆Separate data input and output
◆◆
◆◆
◆Input and output directly TTL-compatible
◆◆
◆◆
◆Military product compliant to MIL-STD-883, Class B
Description
The IDT7187 is a 65,536-bit high-speed static RAM organized as 64K
x 1. It is fabricated using IDT’s high-performance, high-reliability CMOS
technology. Access times as fast as 25ns are available.
Both the standard (S) and low-power (L) versions of the IDT7187
provide two standby modes—ISB and ISB1. ISB provides low-power
operation; ISB1 provides ultra-low-power operation. The low-power (L)
version also provides the capability for data retention using battery
backup. When using a 2V battery, the circuit typically consumes only
30µW.
Ease of system design is achieved by the IDT7187 with full
asynchronous operation, along with matching access and cycle times.
The device is packaged in an industry standard 22-pin, 300 mil ceramic
DIP.
Military grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demanding the highest level of performance
and reliability.
Functional Block Diagram
ROW
SELECT 65,536-BIT
MEMORY ARRAY
COLUMN I/O
2986 drw 01
WE
CS
V
CC
GND
DATA
OUT
A
A
A
A
A
A
A
AAAAAAA
DATA
IN
CMOS Static RAM
64K (64K x 1-Bit) IDT7187S
IDT7187L
2
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit) Military Temperature Range
Pin Configuration
Capacitance (TA = +25°C, f = 1.0MHz)
Recommended DC Operations
Conditions
Recommended Operating
Temperature and Supply Voltage
Absolute Maximum Ratings(1)
2986 drw 02
5
6
7
8
9
10
11
1
2
3
4
22
21
20
19
18
17
D22-1
A0
A1
A2
A3
A4
A5
A6
A7
VCC
A15
A13
A12
16
15
GND CS
14
A14
WE
DATAOUT
A11
13
12
A10
A9
A8
DATAIN
,
DIP
Top View
Truth Table(1)
Pin Descriptions
NOTE:
1. H = VIH, L = VIL, X = don't care.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Name Description
A
0
- A
15
Address Inputs
CS Chi p Se le c t
WE Write Enable
V
CC
Power
DATA
IN
Data Inp ut
DATA
OUT
Data Outp ut
GND Ground
2986 tb l 01
Mode CS WE Output Power
Standby H X High-Z Standby
Read L H D
OUT
Active
Write L L High-Z Active
2986 tb l 02
Symbol Rating Value Unit
V
TERM
Terminal Voltage with Respect to GND -0.5 to +7.0 V
T
A
Op e rating Te m p e rature -55 to +125
o
C
T
BIAS
Te mp erature Under Bias -65 to +135
o
C
T
STG
Storage Temperature -65 to +150
o
C
P
T
Po we r Di ss ip atio n 1. 0 W
I
OUT
DC Outp ut Curre nt 50 mA
2986 tbl 03
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
Symbol Parameter
(1)
Conditions Max. Unit
C
IN
Inp ut Cap ac itance V
IN
= 0V 8 pF
C
OUT
Outp ut Cap acitanc e V
OUT
= 0V 8 pF
2986 tbl 04
NOTE:
1. VIL (min.) = –3.0V for pulse width less than 20ns, once per cycle.
Symbol Parameter Min. Typ. Max. Unit
V
CC
Supp ly Vo ltag e 4.5 5.0 5. 5 V
GND Ground 0 0 0 V
V
IH
Inp ut High Voltag e 2.2
____
6.0 V
V
IL
Inp ut Low Voltag e -0.5
(1)
____
0.8 V
2986 tbl 05
Grade Temperature GND Vcc
Military -55
O
C to +125
O
C0V 5V ± 10%
2986 tb l 06
6.42
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit) Military Temperature Range
3
DC Electrical Characteristics
(VCC = 5.0V ± 10%)
Symbol Parameter Test Conditions
IDT7187S IDT7187L
UnitMin. Max. Min. Max.
|I
LI
| Inp ut Le akag e Current V
CC
= Max., V
IN
=
GND to V
CC
____
10
____
5µA
|I
LO
| Outp ut Le akage Curre nt V
CC
= Max., CS = V
IH
, V
OUT
= GND to V
CC
____
10
____
5µA
V
OL
Outp ut Lo w Voltag e I
OL
= 10mA, V
CC
= Min.
____
0.5
____
0.5 V
I
OL
= 8mA, V
CC
= Min.
____
0.4
____
0.4
V
OH
Outp ut High Vo ltag e I
OH
= -4mA, V
CC
= Min. 2.4
____
2.4
____
V
2986 t bl 07
DC Electrical Characteristics(1)
(VCC = 5V ± 10%, VLC = 0.2V, VHC = VCC - 0.2V)
NOTES:
1. All values are maximum guaranteed values.
2. At f = f MAX address and data inputs are cycling at the maximum frequency of read cycles of 1/tRC. f = 0 means no input lines change.
Symbol Parameter Power 7187S25
7187L25 7187S35
7187L35 7187S45
7187L45 7187S55
7187L55 7187S70
7187L70 7187S85
7187L85 Unit
I
CC1
Operating Power
Supply Current
CS = V
IL
, Outputs Open
V
CC
= Max., f
=
0
(2)
S 105 105 105 105 105 105 mA
L858585858585
I
CC2
Dy nam ic Op e rating Current
CS = V
IL
, Outputs Open
V
CC
= Max., f = f
MAX
(2)
S 130 120 120 120 120 120 mA
L11010095909090
I
SB
Standby Power Supply
Curre nt (TTL Le ve l)
CS > V
IH
, Outp uts Ope n
V
CC
= Max., f = f
MAX
(2)
S555050505050
mA
L504035302828
I
SB1
Full Stand by Power
Sup p ly Curre nt (CMOS Lev e l)
CS > V
HC
, V
CC
= Max., V
IN
< V
LC
or V
IN
> V
HC
, f = 0
(2)
S202020202020
mA
L 1.5 1.5 1.5 1.5 1.5 1.5
2986 tbl 08
4
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit) Military Temperature Range
Data Retention Characteristics
(L Version Only) (VHC = VCC - 0.2V, VLC = 0.2V)
AC Test Conditions
Figure 1. AC Test Load Figure 2. AC Test Load
(for tHZ, tLZ, tWZ and tOW)
*Includes scope and jig capacitances
Low VCC Data Retention Waveform
2986 drw 04
DATA
RETENTION
MODE
4.5V 4.5V
V
DR
≥2V
V
IH
V
IH
t
R
t
CDR
V
CC
CS V
DR
2986 drw 05
480Ω
30pF*
255Ω
DATA
OUT
5V
,
2986 drw 06
480Ω
5pF*
255Ω
DATA
OUT
5V
,
NOTES:
1. TA = +25°C.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed, but not tested.
Typ.
(1)
V
CC
@ Max.
V
CC
@
Symbol Parameter Test Condition Min. 2.0V 3.0V 2.0V 3.0V Unit
V
DR
V
CC
for D ata Rete n ti o n
____
2.0
____ ____ ____ ____
V
I
CCDR
Data Re tenti o n Curre nt
____
10 15 600 900 µA
t
CDR
(3)
Chi p De se l ec t to Data Re te ntio n Ti m CS > V
HC
V
IN
> V
HC
or <
V
LC
0
____ ____ ____ ____
ns
t
R
(3)
Op e rati o n Re c o v e ry Ti me t
RC
(2)
____ ____ ____ ____
ns
I
I
LI
I
(3)
Inp ut Le akag e Current
____ ____ ____
22µA
2986 tbl 09
Input Pulse Levels
Input Rise/Fall Times
Inp ut Timing Re fe rence Le ve ls
Output Reference Levels
AC Te st Load
GND to 3. 0V
5ns
1.5V
1.5V
See Figures 1 and 2
2986 tb l 10
6.42
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit) Military Temperature Range
5
AC Electrical Characteristics (VCC = 5.0V ± 10%)
NOTE:
1. This parameter guaranteed but not tested.
Symbol Parameter
7187S25
7187L25 7187S35/45
7187L35/45 7187S55
7187L55 7187S70
7187L70 7187S85
7187L85
Unit
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
Read Cycl e
t
RC
Re ad Cyc le Time 25
____
35/45
____
55
____
70
____
85
____
ns
t
AA
Address Access Time
____
25
____
35/45
____
55
____
70
____
85 ns
t
ACS
Chip Select Access Time
____
25
____
35/45
____
55
____
70
____
85 ns
t
OH
Output Hold from Address Change 5
____
5
____
5
____
5
____
5
____
ns
t
LZ
(1)
Ou tput Sele ct to O utput in Low- Z 5
____
5
____
5
____
5
____
5
____
ns
t
HZ
(1)
Chi p Deselect to Output i n High - Z
____
12
____
17/20
____
30
____
30
____
40 ns
t
PU
(1)
Chi p S e lec t to P o we r Up Time 0
____
0
____
0
____
0
____
0
____
ns
t
PD
(1)
Chi p De s e le c t to Po we r Do wn Tim e
____
20
____
30/35
____
35
____
35
____
40 ns
2986 tbl 11
Timing Waveform of Read Cycle No. 1(1,2)
Timing Waveform of Read Cycle No. 2(1,3)
NOTES:
1. WE is HIGH for Read cycle.
2. CS is LOW for Read cycle.
3. Address valid prior to or coincident with CS transition LOW.
4. Transition is measured ±200mV from steady state voltage with specified loading in Figure 2.
5. All Read cycle timings are referenced from the last valid address to the first transitioning address.
2986 drw 07
ADDRESS
DATA
t
RC
t
AA
OUT
t
OH
PREVIOUS DATA VALID DATA VALID
(5)
2986 drw 0
8
DATA
OUT
CS
t
ACS
(4)
t
LZ
(4)
HZ
t
t
PD
t
PU
I
CC
I
SB
SUPPLY
CURRENT
V
CC
t
RC (5)
HIGH
IMPEDANCE
DATA VALID
6
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit) Military Temperature Range
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,3,4)
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
5. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig).
CS
2986 drw 09
t
AW
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
WP
t
DH
DATA
OUT
t
WZ
t
OW
t
AS
(5)
VALID DATA
(5)
AC Electrical Characteristics (VCC = 5.0V ± 10%)
NOTE:
1. This parameter guaranteed but not tested.
7187S25
7187L25 7187S35/45
7187L35/45 7187S55
7187L55 7187S70
7187L70 7187S85
7187L85
Symbol Parameter Min.Max.Min.Max.Min.Max.Min.Max.Min.Max.Unit
Wri te Cycl e
t
WC
Write Cycle Time 25
____
35/45
____
55
____
70
____
85
____
ns
t
CW
Chip S el ect to End -of-Write 20
____
25/40
____
50
____
55
____
65
____
ns
t
AW
Address Valid to End-of-Write 20
____
25/40
____
50
____
55
____
65
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 20
____
20/25
____
35
____
40
____
45
____
ns
t
WR
Write Rec o ve ry Time 0
____
0
____
0
____
0
____
0
____
ns
t
DW
Data Valid to E nd -o f-Wri te 15
____
15/25
____
25
____
30
____
35
____
ns
t
DH
Data Ho l d Time 5
____
5
____
5
____
5
____
5
____
ns
t
WZ
(1)
Write Enable to Outp ut in Hig h-Z
____
12
____
15/30
____
30
____
30
____
40 ns
t
OW
(1)
Output Active from End-of-Write 0
____
0
____
0
____
0
____
0
____
ns
2986 tb l 12
6.42
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit) Military Temperature Range
7
NOTES:
1. WE or CS must be HIGH during all address transitions.
2. A write occurs during the overlap (tWP) of a LOW CS and a LOW WE.
3. tWR is measured from the earlier of CS or WE going HIGH to the end of the write cycle.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in the high-impedance state.
5. Transition is measured ±200mV from steady state with a 5pF load (including scope and jig).
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,2,4)
t
WR
CS
2986 drw 10
t
AW
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
CW
t
DH
AS
tt
VALID DATA
(3)
Ordering Information
X
Power
X
X
Speed
X
Package
X
Process/
Temperature
Range
BMilitary (–55°Cto+125°C)
Compliant to MIL-STD-883, Class B
D 300 mil Ceramic DIP (D22-1)
25
35
45
55
70
85
S
LStandard Power
Low Power
I
D
7
1
8
7
Speed in nanoseconds
2986 drw 11
Device
Type
,
8
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit) Military Temperature Range
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
11/xx/99 Updated to new format
Pp. 1, 2, 8 Revised package offerings
Pp. 3, 4 Removed commercial temperature data
Pg. 8 Added Datasheet Document History
08/09/00 Not recommended for new designs
02/01/01 Removed "Not recommended for new designs"
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or ipchelp@idt.com
San Jose, CA 95138 408-284-8200 800-345-7015
fax: 408-284-2775
www.idt.com