OPA3695
OPA3695
1
FEATURES DESCRIPTION
APPLICATIONS
-5V
+5V
MONITOROUTPUT
-
+
604W
604W75W
75W
INPUT
-
+
604W
604W
75W
-
+
604W
604W
75W
A
B
C
75W
75W
OPA3695
0.1 Fm
0.1mF
RED
GREEN
BLUE
0.1mF
75W
75W
75W
75W
75W
75W
ADC/
DECODER
TVP7002
RED
GREEN
BLUE
R G B
OPA3695
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............................................................................................................................................... SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008
Triple, Ultra-Wideband, Current-FeedbackOPERATIONAL AMPLIFIER with Disable
2
•900MHz BANDWIDTH, GAIN = +2V/V
The OPA3695 is a triple, very high bandwidth,current-feedback op amp that combines an•450MHz BANDWIDTH, GAIN = +8V/V
exceptional 4300V/ µs slew rate and a very high•WIDE OUTPUT VOLTAGE SWING: ± 4V
900MHz bandwidth (G = +2V/V) to provide an•ULTRA-HIGH SLEW RATE: 4300V/ µs
amplifier that is ideal for the most demanding video•3RD-ORDER INTERCEPT: > 35dBm (f < 40MHz) applications. The device versatility is enhanced with alow 1.8nV/ √Hz input voltage noise and an output•LOW 1.8nV/ √Hz VOLTAGE NOISE
stage that can swing within 1V from the supply rail to•± 120mA OUTPUT CURRENT DRIVE
deliver a high dynamic range signal, making it•12.9mA/Ch SUPPLY CURRENT ( ± 5V)
well-suited for analog-to-digital converter (ADC)front-ends or digital-to-analog converter (DAC) output•LOW 0.1mA/Ch DISABLE CURRENT
buffering. Optimized for high gain operation, the•3.5V to 12V SINGLE-SUPPLY OPERATION
OPA3695 is also well-suited for buffering surface•± 1.75V to ± 6V SPLIT-SUPPLY OPERATION
acoustic wave (SAW) filters in an intermediatefrequency (IF) system.
The low 12.9mA/channel supply current is precisely•BROADBAND VIDEO LINE DRIVERS
trimmed at +25 ° C. This trim, along with a low•VERY WIDEBAND ADC DRIVERS
temperature drift, gives low system power overtemperature. System power may be further reduced•HIGH BANDWIDTH INSTRUMENTATION
using the Disable control pin. Leaving this pin open,AMPLIFIERS
or holding it high, gives normal operation. If pulled•HIGH-SPEED IMAGING
low, the OPA3695 supply current drops to•ACTIVE FILTERS
100 µA/channel. This power-saving feature, along with•ARB WAVEFORM OUTPUT DRIVERS
exceptional single +5V operation, makes theOPA3695 a good fit for low-power applications thatrequire very high performance. The OPA3695 isavailable in an SSOP-16 package.
OPA3695 RELATED PRODUCTS
SINGLES DUALS TRIPLES
OPA695 OPA2695 OPA3695OPA691 OPA2691 OPA3691OPA692 THS3202 OPA3692OPA693 —OPA3693OPA694 OPA2694 —
Figure 1. Typical RGB Input/Output BufferApplication
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
ABSOLUTE MAXIMUM RATINGS
(1)
PARAMETER INFORMATION
1
2
3
4
5
6
7
8 9
10
11
12
13
14
15
16
-INA
-INB
-INC
-VS
+VS
+VS
-VS
+INA
DISB
DISA
DISC
+INB
+INC
OUTC
OUTB
OUTA
OPA3695
SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008 ...............................................................................................................................................
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be moresusceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
SPECIFIEDPACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT MEDIA,PRODUCT PACKAGE DESIGNATOR RANGE MARKING NUMBER QUANTITY
OPA3695IDBQ Rails, 75OPA3695 SSOP-16 DBQ – 40 ° C to +85 ° C OPA3695
OPA3695IDBQR Tape and Reel, 3000
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TIweb site at www.ti.com .
Over operating free-air temperature range (unless otherwise noted).
OPA3695 UNIT
Power supply ± 6.5 V
DC
Internal power dissipation See Thermal AnalysisDifferential input voltage ± 1.2 VInput common-mode voltage range ± V
S
Storage temperature range: DBQ – 65 to +125 ° CLead temperature (soldering, 10s) +300 ° CJunction temperature (T
J
) +125 ° CHuman body model (HBM) 1500 VESD rating Charge device model (CDM) 1000 VMachine model (MM) 100 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods maydegrade device reliability. These are stress ratings only, and functional operation of the device at these and any other conditions beyondthose specified is not supported.
SSOP-16
(TOP VIEW)
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ELECTRICAL CHARACTERISTICS: V
S
= ± 5V
OPA3695
www.ti.com
............................................................................................................................................... SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008
Boldface limits are tested at +25 ° C.At R
F
= 402 Ω, R
L
= 100 Ω, and G = +8, unless otherwise noted.
OPA3695
TYP MIN/MAX OVER TEMPERATURE
0 ° C to – 40 ° C to MIN/ TESTPARAMETER CONDITIONS +25 ° C +25 ° C
(2)
70 ° C
(3)
+85 ° C
(3)
UNITS MAX LEVEL
(1)
AC PERFORMANCE (see Figure 1 )
Small-signal bandwidth (V
O
= 0.5V
PP
) G = +1, R
F
= 909 Ω1000 MHz typ C
G = +2, R
F
= 604 Ω900 MHz typ C
G = +8, R
F
= 402 Ω450 400 MHz min B
G = +16, R
F
= 249 Ω340 MHz typ C
Bandwidth for 0.2dB gain flatness G = +2, V
O
= 0.5V
PP
, R
F
= 604 Ω320 MHz min B
Peaking at a gain of +1 R
F
= 523 Ω, V
O
= 0.5V
PP
4.6 5.4 dB max B
Large-signal bandwidth G = +2, V
O
= 2V
PP
600 MHz typ C
G = +8, V
O
= 4V
PP
450 MHz typ C
Slew rate G = +2, V
O
= 2V step 2400 V/ µs typ C
G = – 8, V
O
= 4V step 4300 3700 V/ µs min B
G = +8, V
O
= 4V step 2900 2600 V/ µs min B
Rise-and-fall time G = +2, V
O
= 4V step 1.0 ns typ C
G = +8, V
O
= 0.5V step 0.8 ns typ C
G = +8, V
O
= 4V step 1.0 ns typ C
Settling time to 0.02% G = +8, V
O
= 2V step 16 ns typ C
Settling time to 0.1% G = +8, V
O
= 2V step 10 ns typ C
Harmonic distortion G = +8, f = 10MHz, V
O
= 2V
PP
2nd harmonic R
L
= 100 Ω– 65 – 62 dBc max B
R
L
≥500 Ω– 78 – 76 dBc max B
3rd harmonic R
L
= 100 Ω– 86 – 84 dBc max B
R
L
≥500 Ω– 86 – 82 dBc max B
2nd harmonic G = +2, f = 10MHz, R
L
= 100 Ω– 74 dBc typ C
3rd harmonic G = +2, f = 10MHz, R
L
= 100 Ω– 74 dBc typ C
Input voltage noise f > 1MHz 1.8 2 nV/ √Hz max B
Noninverting input current noise f > 1MHz 18 19 pA/ √Hz max B
Inverting input current noise f > 1MHz 22 24 pA/ √Hz max B
G = +2, NTSC, V
O
= 1.4V
PP
,Differential gain 0.04 % typ CR
L
= 150 Ω
G = +2, NTSC, V
O
= 1.4V
PP
,Differential phase 0.007 degrees typ CR
L
= 150 Ω
All hostile, G = +8, f = 10MHz,Crosstalk – 55 dB typ CV
O
= 2V
PP
DC PERFORMANCE
(4)
Open-loop transimpedance gain (Z
OL
) V
O
= 0V, R
L
= 100 Ω85 45 43 41 k Ωmin A
Input offset voltage V
CM
= 0V ± 0.3 ± 3.5 ± 4.0 ± 4.5 mV max A
Average offset voltage drift V
CM
= 0V ± 10 ± 15 µV/ ° C max B
Noninverting input bias current V
CM
= 0V +13 ± 30 ± 37 ± 41 µA max A
Average noninverting input bias current drift V
CM
= 0V 150 180 nA/ ° C max B
Inverting input bias current V
CM
= 0V ± 20 ± 60 ± 66 ± 70 µA max A
Average inverting input bias current drift V
CM
= 0V ± 120 ± 160 nA/ ° C max B
INPUT
Common-mode input voltage range (CMIR)
(5)
± 3.3 ± 3.1 ± 3.0 ± 3.0 V min A
Common-mode rejection ratio (CMRR) V
CM
= 0V 56 51 50 50 dB min A
Noninverting input impedance 280 || 1.2 k Ω|| pF typ C
Inverting input resistance (R
I
) Open-loop 33 Ωtyp C
(1) Test levels: (A) 100% tested at +25 ° C. Over temperature limits set by characterization and simulation. (B) Limits set by characterizationand simulation. (C) Typical value only for information.(2) Junction temperature = ambient for +25 ° C specifications.(3) Junction temperature = ambient at low temperature limits; junction temperature = ambient +48 ° C at high temperature limit for overtemperature specifications.(4) Current is considered positive out of pin.(5) Tested < 3dB below minimum specified CMRR at ± CMIR limits.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 3
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OPA3695
SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008 ...............................................................................................................................................
www.ti.com
ELECTRICAL CHARACTERISTICS: V
S
= ± 5V (continued)Boldface limits are tested at +25 ° C.At R
F
= 402 Ω, R
L
= 100 Ω, and G = +8, unless otherwise noted.
OPA3695
TYP MIN/MAX OVER TEMPERATURE
0 ° C to – 40 ° C to MIN/ TESTPARAMETER CONDITIONS +25 ° C +25 ° C
(2)
70 ° C
(3)
+85 ° C
(3)
UNITS MAX LEVEL
(1)
OUTPUT
Voltage output swing No load ± 4.0 ± 3.9 ± 3.8 ± 3.8 V min A
100 Ωload ± 3.9 ± 3.7 ± 3.7 ± 3.6 V min A
Current output, sourcing V
O
= 0V +120 +90 +80 +70 mA min A
Current output, sinking V
O
= 0V – 120 – 90 – 80 – 70 mA min A
Closed-loop output impedance G = +2, f = 10MHz 0.3 Ωtyp C
DISABLE (Disabled LOW)
Power-down supply current (+V
S
) Per channel, V
DIS
= 0V – 100 – 170 – 187 – 194 µA max A
Disable time V
IN
= ± 0.25V
DC
1µs typ C
Enable time V
IN
= ± 0.25V
DC
25 ns typ C
Off isolation G = +8, 10MHz 77 dB typ C
Output capacitance in disable 4 pF typ C
Turn-on glitch G = +2, R
L
= 150 Ω, V
IN
= 0V ± 100 mV typ C
Turn-off glitch G = +2, R
L
= 150 Ω, V
IN
= 0V ± 20 mV typ C
Enable voltage 3.3 3.5 3.6 3.7 V min A
Disable voltage 1.8 1.7 1.6 1.5 V max A
Control pin input bias current ( DIS) V
DIS
= 0V 75 130 143 150 µA max A
POWER SUPPLY
Specified operating voltage ± 5 V typ C
Maximum operating voltage range ± 6 V max A
Minimum operating voltage range ± 1.75 ± 1.8 ± 1.9 V min B
Maximum quiescent current Per channel, V
S
= ± 5V 12.9 13.4 13.8 14.2 mA max A
Minimum quiescent current Per channel, V
S
= ± 5V 12.9 12.1 11.4 10.6 mA min A
Power-supply rejection ratio ( – PSRR) Input-referred 55 51 48 48 dB min A
TEMPERATURE RANGE
Specification: IDBQ – 40 to +85 ° C typ C
Thermal resistance, θ
JA
Junction-to-ambient
DBQ SSOP-16 80 ° C/W typ C
4Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA3695
ELECTRICAL CHARACTERISTICS: V
S
= +5V
OPA3695
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............................................................................................................................................... SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008
Boldface limits are tested at +25 ° C.At R
F
= 348 Ω, R
L
= 100 Ωto 2.5V, and G = +8, unless otherwise noted.
OPA3695
TYP MIN/MAX OVER TEMPERATURE
0 ° C to – 40 ° C to MIN/ TESTPARAMETER CONDITIONS +25 ° C +25 ° C
(2)
70 ° C
(3)
+85 ° C
(3)
UNITS MAX LEVEL
(1)
AC PERFORMANCE (see Figure 3 )
Small-signal bandwidth (V
O
= 0.5V
PP
) G = +1, R
F
= 750 Ω850 MHz typ C
G = +2, R
F
= 487 Ω725 MHz typ C
G = +8, R
F
= 348 Ω395 380 MHz typ B
G = +16, R
F
= 162 Ω275 MHz typ C
Bandwidth for 0.2dB gain flatness G = +2, V
O
< 0.5V
PP
, R
F
= 487 Ω230 180 MHz min B
Peaking at a gain of +1 R
F
= 511 Ω, V
O
< 0.5V
PP
1.0 2.0 dB max B
Large-signal bandwidth G = +2, V
O
= 2V
PP
440 MHz typ C
G = +8, V
O
= 2V
PP
330 MHz typ C
Slew rate G = +2, V
O
= 2V step 1700 V/ µs typ C
G = +8, V
O
= 2V step 1700 1300 V/ µs min B
Rise-and-fall time G = +2, V
O
= 2V step 1.0 ns typ C
G = +8, V
O
= 0.5V step 1.0 ns typ C
G = +8, V
O
= 2V step 1.0 ns typ C
Settling time to 0.02% G = +8, V
O
= 2V step 16 ns typ C
Settling time to 0.1% G = +8, V
O
= 2V step 10 ns typ C
Harmonic distortion G = +8, f = 10MHz, V
O
= 2V
PP
2nd harmonic R
L
= 100 Ωto 2.5V – 62 – 58 dBc max B
R
L
≥500 Ωto 2.5V – 70 – 66 dBc max B
3rd harmonic R
L
= 100 Ωto 2.5V – 66 – 64 dBc max B
R
L
≥500 Ωto 2.5V – 65 – 63 dBc max B
2nd harmonic G = +2, f = 10MHz, R
L
= 100 Ω– 68 dBc typ C
3rd harmonic G = +2, f = 10MHz, R
L
= 100 Ω– 68 dBc typ C
Input voltage noise f > 1MHz 1.8 2 nV/ √Hz max B
Noninverting input current noise f > 1MHz 18 19 pA/ √Hz max B
Inverting input current noise f > 1MHz 22 24 pA/ √Hz max B
DC PERFORMANCE
(4)
Open-loop transimpedance gain (Z
OL
) V
O
= 2.5V, R
L
= 100 Ωto 2.5V 70 40 38 36 k Ωmin A
Input offset voltage V
CM
= 2.5V ± 0.3 ± 3.5 ± 4.0 ± 4.5 mV max A
Average offset voltage drift V
CM
= 2.5V ± 10 ± 15 µV/ ° C max B
Noninverting input bias current V
CM
= 2.5V ± 5 ± 40 ± 45 ± 50 µA max A
Average noninverting input bias current drift V
CM
= 2.5V ± 110 ± 170 nA/ ° C max B
Inverting input bias current V
CM
= 2.5V ± 5 ± 60 ± 70 ± 75 µA max A
Average inverting input bias current drift V
CM
= 2.5V ± 120 ± 160 nA/ ° C max B
INPUT
Least positive input voltage
(5)
1.7 1.8 1.9 1.9 V max A
Most positive input voltage
(5)
3.3 3.2 3.1 3.1 V min A
Common-mode rejection ratio (CMRR) V
CM
= 2.5V 54 51 50 50 dB min A
Noninverting input impedance 280 || 1.2 k Ω|| pF typ C
Inverting input resistance (R
I
) Open-loop 37 Ωtyp C
(1) Test levels: (A) 100% tested at +25 ° C. Over temperature limits set by characterization and simulation. (B) Limits set by characterizationand simulation. (C) Typical value only for information.(2) Junction temperature = ambient for +25 ° C specifications.(3) Junction temperature = ambient at low temperature limits; junction temperature = ambient +21 ° C at high temperature limit for overtemperature specifications.(4) Current is considered positive out of pin.(5) Tested < 3dB below minimum specified CMRR at ± CMIR limits.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Link(s): OPA3695
OPA3695
SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008 ...............................................................................................................................................
www.ti.com
ELECTRICAL CHARACTERISTICS: V
S
= +5V (continued)Boldface limits are tested at +25 ° C.At R
F
= 348 Ω, R
L
= 100 Ωto 2.5V, and G = +8, unless otherwise noted.
OPA3695
TYP MIN/MAX OVER TEMPERATURE
0 ° C to – 40 ° C to MIN/ TESTPARAMETER CONDITIONS +25 ° C +25 ° C
(2)
70 ° C
(3)
+85 ° C
(3)
UNITS MAX LEVEL
(1)
OUTPUT
Most positive output voltage No load 4.2 4.0 3.9 3.8 V min A
R
L
= 100 Ωload to 2.5V 4.0 3.9 3.8 3.7 V min A
Least positive output voltage No load 0.9 1.0 1.1 1.2 V max A
R
L
= 100 Ωload to 2.5V 1.0 1.1 1.2 1.3 V max A
Current output, sourcing V
O
= 2.5V +90 +70 +67 +66 mA min A
Current output, sinking V
O
= 2.5V – 90 – 70 – 67 – 66 mA min A
Closed-loop output impedance G = +2, f = 100kHz 0.05 Ωtyp C
DISABLE (Disabled LOW)
Power-down supply current (+V
S
) Per channel, V
DIS
= 0V – 100 – 160 – 177 – 180 µA max C
Disable time 1 µs typ C
Enable time 25 ns typ C
Off isolation G = +8, 10MHz 70 dB typ C
Output capacitance in disable 4 pF typ C
Turn-on glitch G = +2, R
L
= 150 Ω, V
IN
= 2.5V ± 100 mV typ C
Turn-off glitch G = +2, R
L
= 150 Ω, V
IN
= 2.5V ± 20 mV typ C
Enable voltage 3.3 3.5 3.6 3.7 V min A
Disable voltage 1.8 1.7 1.6 1.5 V max A
Control pin input bias current ( DIS) V
DIS
= 0V 75 130 143 149 µA max C
POWER SUPPLY
Specified single-supply operating voltage 5 V typ C
Maximum single-supply operating voltage range 12 V max A
Minimum operating voltage range 3.5 3.6 3.8 V min B
Maximum quiescent current Per channel, V
S
= +5V 11.4 12.1 12.6 13.0 mA max A
Minimum quiescent current Per channel, V
S
= +5V 11.4 10.6 9.1 8.8 mA min A
Power-supply rejection ratio ( – PSRR) Input-referred 56 dB typ C
TEMPERATURE RANGE
Specification: IDBQ – 40 to +85 ° C typ C
Thermal resistance, θ
JA
Junction-to-ambient
DBQ SSOP-16 80 ° C/W typ C
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TYPICAL CHARACTERISTICS: V
S
= ± 5V
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
NormalizedGain(dB)
Frequency(Hz)
1M 2G10M 100M 1G
V = 5V±
V =0.5V
R =100W
S
O PP
LOAD
G=+1,R =511W
F
G=+16,R =249W
F
G=+8,R =402W
F
G=+2,R =511W
F
G=+4,R =511W
F
2
1
0
-1
-2
-3
-4
-5
-6
Frequency(Hz)
1M 1G
NormalizedGain(dB)
100M
V = 5V±
G=+2V/V
R =511
R =100
W
W
S
F
LOAD V =7V
O PP
V =4V
O PP
V =2V
O PP
V =1V
O PP
1
0
-1
-2
-3
-4
Frequency(Hz)
1M 1G
NormalizedGain(dB)
100M
V =±5V
G=+8V/V
R =402
R =100
W
W
S
F
LOAD
V =1V
O PP
V =2V
O PP
V =4V
O PP
V =7V
O PP
600
400
200
0
-200
-400
-600
Time(ns)
0 11
OutputVoltage(V)
1 2 3 4 5 6 7 8 9 10
V =±5V
G=+8V/V
R =402
R =100
W
W
S
F
LOAD
2.5
2.0
1.5
1.0
0.5
0
-0.5
-1.0
-1.5
-2.0
-2.5
Time(ns)
0 11
OutputVoltage(V)
1 2 3 4 5 6 7 8 9 10
V =±5V
G=+8V/V
R =402
R =100
W
W
S
F
LOAD
-60
-65
-70
-75
-80
-85
-90
-95
LoadResistance( )W
1 1k
HarmonicDistortion(dBc)
100
3rdHarmonic
2ndHarmonic
V = 5V±
G=+8V/V
R =402
V =2V
W
S
F
OUT PP
OPA3695
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............................................................................................................................................... SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008
At R
F
= 402 Ω, R
L
= 100 Ω, and G = +8, unless otherwise noted.
NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE GAIN OF +2, LARGE-SIGNAL FREQUENCY RESPONSE
Figure 2. Figure 3.
GAIN OF +8, LARGE-SIGNAL FREQUENCY RESPONSE NONINVERTING SMALL-SIGNAL PULSE RESPONSE
Figure 4. Figure 5.
NONINVERTING LARGE-SIGNAL PULSE RESPONSE 10MHz HARMONIC DISTORTION vs LOAD RESISTANCE
Figure 6. Figure 7.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 7
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-40
-50
-60
-70
-80
-90
-100
Frequency(Hz)
100k 100M
HarmonicDistortion(dBc)
1M 10M
2ndHarmonic
3rdHarmonic
V =±5V
G=+8V/V
R =402
R =100
V =2V
W
W
S
F
LOAD
OUT PP
-60
-65
-70
-75
-80
-85
-90
SupplyVoltage(±V )
S
2.5 6.0
HarmonicDistortion(dBc)
3.0 3.5 4.0 4.5 5.0 5.5
G=+8V/V
R =402
R =100
V =2V
W
W
F
LOAD
OUT PP
3rdHarmonic
2ndHarmonic
-60
-65
-70
-75
-80
-85
-90
Noninverting(V/V)
1 15
HarmonicDistortion(dBc)
3 5 7 9 11 13
V = 5V±
R =100
V =2V
W
S
LOAD
OUT PP
3rdHarmonic
2ndHarmonic
-60
-65
-70
-75
-80
-85
LoadResistance( )W
10 1k
HarmonicDistortion(dBc)
100
3rdHarmonic
2ndHarmonic
V =±5V
G=+2V/V
R =511
V =2V
W
S
F
OUT PP
-60
-65
-70
-75
-80
-85
-90
SupplyVoltage(±V )
S
2.5 6.0
HarmonicDistortion(dBc)
3.0 3.5 4.0 4.5 5.0 5.5
G=+2V/V
R =511
R =100
V =2V
W
W
F
LOAD
OUT PP
3rdHarmonic
2ndHarmonic
OPA3695
SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008 ...............................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS: V
S
= ± 5V (continued)At R
F
= 402 Ω, R
L
= 100 Ω, and G = +8, unless otherwise noted.
10MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE HARMONIC DISTORTION vs FREQUENCY
Figure 8. Figure 9.
10MHz HARMONIC DISTORTION vs OUTPUT VOLTAGE 10MHz HARMONIC DISTORTION vs NONINVERTING GAIN
Figure 10. Figure 11.
10MHz HARMONIC DISTORTION vs LOAD RESISTANCE 10MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE
Figure 12. Figure 13.
8Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA3695
-50
-60
-70
-80
-90
-100
Frequency(Hz)
100k 100M
HarmonicDistortion(dBc)
1M 10M
V =±5V
G=+2V/V
R =511
R =100
V =2V
W
W
S
F
LOAD
OUT PP
2ndHarmonic
3rdHarmonic
-60
-65
-70
-75
-80
-85
-90
Inverting(V/V)
-1-15
HarmonicDistortion(dBc)
-3-5-7-9-11 -13
V = 5V±
R =100
V =2V
W
S
LOAD
OUT PP
3rdHarmonic
2ndHarmonic
40
35
30
25
20
15
Frequency(MHz)
20 240
OutputIntercept(+dBm)
40 60 80 100 120 140
V = 5V±
R =100
V =2V
W
S
LOAD
OUT PP
Noninverting
Gain=+8V/V
R =402W
F
Inverting
Gain= 8V/V
R =442
-
W
F
160 180 200 220
-40
-50
-60
-70
-80
-90
-100
Frequency(Hz)
1M 1G
DisableFeedthrough(dB)
10M 100M
Forward
Reverse
V =±5V
G=+8V/V
R =402
R =100
W
W
S
F
LOAD
5
4
3
2
1
0
-1
-2
-3
-4
-5
V(V)
O
-250 -200 -150 -100 -50 0 25020015010050
I (mA)
O
1WInternalPowerBoundary
Single-Channel
1WInternal
PowerBoundary
Single-Channel
100 LoadLineW
50 LoadLineW
20 LoadLineW
OPA3695
www.ti.com
............................................................................................................................................... SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008
TYPICAL CHARACTERISTICS: V
S
= ± 5V (continued)At R
F
= 402 Ω, R
L
= 100 Ω, and G = +8, unless otherwise noted.
HARMONIC DISTORTION vs FREQUENCY 10MHz HARMONIC DISTORTION vs OUTPUT VOLTAGE
Figure 14. Figure 15.
10MHz HARMONIC DISTORTION vs INVERTING GAIN TWO-TONE, 3RD-ORDER INTERMODULATION INTERCEPT
Figure 16. Figure 17.
OUTPUT VOLTAGE AND CURRENT LIMITATIONS DISABLE FEEDTHROUGH vs FREQUENCY
Figure 18. Figure 19.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 9
Product Folder Link(s): OPA3695
-20
-30
-40
-50
-60
-70
-80
Frequency(Hz)
1M 1G
Crosstalk(dB)
10M 100M
ChannelB
ChannelA
V =±5V
G=+8V/V
R =402
R =100
All-HostileCrosstalk
W
W
S
OUT PP
F
LOAD
V =2V
ChannelC
0.02
0.01
0
-0.01
-0.02
-0.03
-0.05
NumberofParallelVideoLoads
1 4
DifferentialGain/DifferentialPhase(%/ )°
2 3
V = 5V
G=+2V/V
±
R =511W
S
F
-dP +dP
-0.04
-dG
+dG
7
6
5
4
3
2
-1
Time( s)m
0 10
Voltage(V)
1 2 3 4 5 6 7 8 9
V =±5V
G=+8V/V
R =402
R =100
W
W
S
IN DC
F
LOAD
V =0.25V
1
0
DisablePinVoltage
OutputVoltage
21
18
15
12
9
Frequency(Hz)
10M 1G
Output(dB)
100M
C =22pF,R =30.3W
L S
C =10pF
R =43.4W
L
S
V =±5V
G=+8V/V
R =402
V =0.5V
W
W
S
F
LOAD
OUT PP
R =1k
C =47pF,R =20.8W
L S
C =100pF,R =14.9W
L S
OPA3695
SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008 ...............................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS: V
S
= ± 5V (continued)At R
F
= 402 Ω, R
L
= 100 Ω, and G = +8, unless otherwise noted.
DIFFERENTIAL GAIN AND PHASE vsCROSSTALK vs FREQUENCY NUMBER OF PARALLEL VIDEO LOADS
Figure 20. Figure 21.
DISABLE/ENABLE RESPONSE FREQUENCY RESPONSE vs CAPACITIVE LOAD
Figure 22. Figure 23.
10 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA3695
TYPICAL CHARACTERISTICS: V
S
= +5V
3
2
1
0
-1
-2
-3
-4
-5
-6
Frequency(Hz)
1M 1G10M
NormalizedGain(dB)
100M
V =5V
V =0.5V
R =100W
S
O PP
LOAD
G=+1V/V,R =487W
F
G=+16V/V,R =160W
F
G=+8V/V,R =348W
F
G=+2V/V,R =487W
F
G=+4V/V,R =453W
F
4.0
3.5
3.0
2.5
2.0
1.5
1.0
Time(ns)
0 11
OutputVoltage(V)
1 2 3 4 5 6 7 8 9 10
V =5V
G=+8V/V
R =348
R =100
W
W
S
F
LOAD
-40
-50
-60
-70
-80
-90
Frequency(Hz)
100k 100M
HarmonicDistortion(dBc)
1M 10M
2ndHarmonic
3rdHarmonic
V =5V
G=+8V/V
R =348
R =100
V =2V
W
W
S
F
LOAD
OUT PP
-50
-55
-60
-65
-70
-75
-80
LoadResistance( )W
1 1k
HarmonicDistortion(dBc)
100
3rdHarmonic
2ndHarmonic
V =5V
G=+8V/V
R =348
V =2V
W
S
F
OUT PP
-40
-50
-60
-70
-80
-90
Frequency(MHz)
0.1 100
HarmonicDistortion(dBc)
1 10
V =5V
G=+2V/V
R =487
R =100
V =2V
W
W
S
F
LOAD
OUT PP
2ndHarmonic
3rdHarmonic
OPA3695
www.ti.com
............................................................................................................................................... SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008
At R
F
= 348 Ω, R
L
= 100 Ωto 2.5V, and G = +8, unless otherwise noted.
NONINVERTING SMALL-SIGNAL FREQUENCY RESPONSE NONINVERTING LARGE-SIGNAL PULSE RESPONSE
Figure 24. Figure 25.
HARMONIC DISTORTION vs FREQUENCY 10MHz HARMONIC DISTORTION vs OUTPUT VOLTAGE
Figure 26. Figure 27.
10MHz HARMONIC DISTORTION vs LOAD RESISTANCE HARMONIC DISTORTION vs FREQUENCY
Figure 28. Figure 29.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Link(s): OPA3695
-60
-65
-70
-75
-80
LoadResistance( )W
10 1k
HarmonicDistortion(dBc)
100
3rdHarmonic
2ndHarmonic
V =5V
G=+2V/V
R =487
V =2V
W
S
F
OUT PP
40
35
30
25
20
15
Frequency(MHz)
20 240
OutputIntercept(+dBm)
40 60 80 100 120 140
V =5V
R =100
V =2V
W
S
LOAD
OUT PP
Noninverting
Gain=+8V/V
R =348W
F
Inverting
Gain= 8V/V
R =422
-
W
F
160 180 200 220
100
90
80
70
60
0
CapacitiveLoad(pF)
1 1000
SeriesResistance,R ()
W
S
10 100
V =±5Vor5V
G=+8V/V
R =511W
S
F
60
60
60
60
60
21
18
15
12
9
Frequency(Hz)
10M 1G
Output(dB)
100M
C =22pF,R =32W
L S
C =10pF
R =41.5W
L
S
V =5V
G=+8V/V
R =348
V =0.5V
W
W
S
F
LOAD
OUT PP
R =1k
C =47pF,R =21.3W
L S
C =100pF,R =14.7W
L S
OPA3695
SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008 ...............................................................................................................................................
www.ti.com
TYPICAL CHARACTERISTICS: V
S
= +5V (continued)At R
F
= 348 Ω, R
L
= 100 Ωto 2.5V, and G = +8, unless otherwise noted.
10MHz HARMONIC DISTORTION vs OUTPUT VOLTAGE 10MHz HARMONIC DISTORTION vs LOAD RESISTANCE
Figure 30. Figure 31.
TWO-TONE, 3RD-ORDER INTERMODULATION INTERCEPT RECOMMENDED R
S
vs CAPACITIVE LOAD
Figure 32. Figure 33.
FREQUENCY RESPONSE vs CAPACITIVE LOAD
Figure 34.
12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA3695
APPLICATION INFORMATION
WIDEBAND BUFFER OPERATION
1/3
OPA3695
+5V
-5V
50 LoadW
50W50W
50 SourceW
RG
RF
+
6.8 Fm0.1 Fm
+
6.8 Fm0.1 Fm
VI
VO
DIS
OPA3695
www.ti.com
............................................................................................................................................... SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008
The OPA3695 gives the exceptional ac performanceof a wideband current-feedback op amp with a highlylinear output stage. Requiring only 12.9mA/channelsupply current, the OPA3695 achieves a 900MHzsmall-signal bandwidth (G = +2V/V); the high slewrate capability of up to 4300V/ µs supports a 600MHz2V
PP
large signal into a 100 Ωload. The low outputheadroom of 1V from either supply in a veryhigh-speed amplifier gives very good single +5Voperation. The OPA3695 delivers a 2V
PP
swing withgreater than 400MHz bandwidth operating on a single+5V supply. The primary advantage of acurrent-feedback video buffer (as opposed to aslew-enhanced, low-gain, stable voltage-feedbackimplementation) is a higher slew rate with lowerquiescent power and output noise.
Figure 35. DC-Coupled, Noninverting,Figure 35 shows the dc-coupled, noninverting, dual
Bipolar-Supply, Specification and Test Circuitpower-supply circuit configuration used as the basisfor the ± 5V Electrical Characteristics table andTypical Characteristics curves. For test purposes, the Figure 36 illustrates the dc-coupled, invertinginput impedance is set to 50 Ωwith a resistor to configuration used as the basis of the Invertingground; the output impedance is set to 50 Ωwith a Typical Characteristic curves. Inverting operationseries output resistor. Voltage swings reported in the offers several performance benefits. Since there is nospecifications are taken directly at the input and common-mode signal across the input stage, the slewoutput pins while load powers (dBm) are defined at a rate for inverting operation is higher and the distortionmatched 50 Ωload. For the circuit of Figure 35 , the performance is slightly improved. An additional inputtotal effective amplifier loading is 100 Ω|| (R
F
+ R
G
) . resistor, R
M
, is included in Figure 36 to set the inputFor example, with a gain of +2V/V with R
F
and R
G
impedance equal to 50 Ω. The parallel combination ofequal to 604 Ω, the equivalent amplifier loading is R
M
and R
G
sets the input impedance. Both the100 Ω|| 1208 Ω= 92.3 Ω. The disable control line noninverting and inverting applications of Figure 35( DIS) is typically left open to ensure normal amplifier and Figure 36 benefit from optimizing the feedbackoperation. Note that while most of the information resistor (R
F
) value for bandwidth (see the discussionpresented in this data sheet was characterized with in the Gain Setting section). The typical design100 Ωloading, performance with a standard video sequence is to select the R
F
value for bestloading of 150 Ωhas negligible impact on bandwidth, set R
G
for the gain, and then set R
M
forperformance. Any changes in performance are the desired input impedance. As the gain increasestypically improved over 100 Ωloading because of for the inverting configuration, a point is reachedlower output current demands. where R
G
equals 50 Ωand R
M
is removed; thus, theinput match is set by R
G
only. With R
G
fixed toachieve an input match to 50 Ω, R
F
is simplyincreased to increase gain. This approach, however,quickly reduces the achievable bandwidth at suchhigh gains. For gains greater than 10V/V,noninverting operation is recommended to maintainbroader bandwidth.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Link(s): OPA3695
1/3
OPA3695
+5V
DIS
50W
VO
RF
RG
RM
+
6.8 Fm0.1 Fm
50 LoadW
-5V
+
6.8 Fm0.1 Fm
50 SourceW
VI
1/3
OPA3695
+5V
+VS
DIS
V /2
S
604W
100WVO
VI
604W
RG
49.9W
RF
348W
0.1 Fm
0.1 Fm
+
6.8 Fm0.1 Fm
50 SourceW
60.4W
SINGLE-SUPPLY OPERATION
OPA3695
SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008 ...............................................................................................................................................
www.ti.com
simple resistive divider from the +5V supply (two604 Ωresistors). The input signal is then ac-coupledinto this midpoint voltage bias. The input voltage canswing to within 1.6V of either supply pin, giving a1.8V
PP
input signal range centered between thesupply pins. The input impedance matching resistor(60.4 Ω) used for testing is adjusted to give a 50 Ωinput match when the parallel combination of thebiasing divider network is included. The gain resistor(R
G
) is ac-coupled, giving the circuit a dc gain of+1V/V, which puts the input dc bias voltage (2.5V) onthe output as well. Again, on a single +5V supply, theoutput voltage can swing to within 1V of either supplypin while delivering ± 90mA output current. Ademanding 100 Ωload to a midpoint bias is used inthis characterization circuit. The new output stageused in the OPA3695 can deliver large bipolar outputFigure 36. DC-Coupled, Inverting, Bipolar-Supply,
current into this midpoint load with minimal crossoverSpecification and Test Circuit
distortion, as illustrated by the +5V supply,third-harmonic distortion plots.Notice that in this configuration (shown in Figure 36 ),the noninverting input is tied directly to ground.Because the internal design for the OPA3695 iscurrent-feedback, trying to achieve improved dcaccuracy by including a resistor on the noninvertinginput to ground is ineffective. Using a direct short toground on the noninverting input reduces both thecontribution of the dc bias current and the noisecurrent to the output error. While the external R
M
isused here to match with the 50 Ωsource from the testequipment, the input impedance in this configurationis limited to the R
G
resistor. Removing R
M
does notstrongly impact the dc operating point because theshort on the noninverting input of Figure 36 providesthe dc operating voltage. This application of theOPA3695 provides a very broadband, high-outputsignal inverter.
Figure 37. AC-Coupled, G = +8V/V, Single-SupplySpecification and Test CircuitThe OPA3695 may be used over a single-supplyrange of +3.5V to +12V. Though not a rail-to-rail
While the circuit of Figure 37 shows +5Voutput design, the OPA3695 requires minimal input
single-supply operation, this same circuit may beand output voltage headroom compared to other
used for single supplies that range as high as +12Vvery-wideband video buffer amplifiers. The key
nominal. The noninverting input bias resistors arerequirement of broadband single-supply operation is
relatively low in Figure 37 to minimize output dc offsetto maintain input and output signal swings within the
as a result of noninverting input bias current. Atuseable voltage ranges at both the input and the
higher signal-supply voltages, these resistors shouldoutput.
be increased in order to limit the added supplycurrent drawn through this path.The circuit of Figure 37 shows the single-supplyac-coupled, gain of +8V/V, video buffer circuit usedas the basis for the Electrical Characteristics tableand Typical Characteristics curves. The circuit ofFigure 37 establishes an input midpoint bias using a
14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA3695
1/3
OPA3695
+5V
-5V
50W
50W
22pF
226W100W
0W
Source
RG
604W
RF
604W
22pF
VI
VO
1/3
OPA3695
+5V
+VS
DIS
V /2
S
604W
100WVO
VI
604W
RG
499W
RF
499W
0.1 Fm
0.1 Fm
+
6.8 Fm0.1 Fm
50 SourceW
60.4W
HIGH-FREQUENCY ACTIVE FILTERS
OPA3695
www.ti.com
............................................................................................................................................... SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008
Figure 38 shows the ac-coupled, G = +2V/V,single-supply specification and test circuit. Onceagain, the noninverting input is dc-biased atmidsupply to put that same V
S
/2 at the output pin.
Figure 39. Line Driver with 40MHz Low-PassActive Filter
This type of filter depends on a low output impedancefrom the amplifier through very high frequencies tocontinue to provide an increasing attenuation withfrequency. As the amplifier output impedance risesFigure 38. AC-Coupled, G = +2V/V, Single-Supply
with frequency, any input signal or noise starts toSpecification and Test Circuit
feed directly through to the output via the feedbackcapacitor. Because the OPA3695 used in Figure 39has a 900MHz bandwidth, the active filter continuesto roll-off through frequencies that exceed 200MHz.The extremely wide bandwidth of the OPA3695
Figure 40 shows the frequency response for the filterallows an extensive range of active filter topologies to
of Figure 39 , where the desired 40MHz cutoff isbe implemented with minimal amplifier bandwidth
achieved and a 40dB/dec roll-off is held through veryinteraction in the filter shape. While Sallen-Key filters
high frequencies.work very well with current-feedback amplifiers, theuse of multiple feedback (MFB) filters is notrecommended because an MFB filter places acapacitor in the feedback path which in turneliminates compensation and results in an oscillator.In general, given a desired filter ω
O
, the amplifiershould have a minimum of 10X ω
O
to minimize filterinteraction with the amplifier frequency response.Figure 39 illustrates an example gain of +2 line driverusing the OPA3695 that incorporates a 40MHzlow-pass Butterworth response with only a fewexternal components. The filter resistor values havebeen adjusted slightly here from an ideal filteranalysis to account for parasitic effects.
Figure 40. 40MHz Low-Pass Active FilterResponse
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): OPA3695
HIGH-SPEED INSTRUMENTATION MULTIPLEXED CONVERTER DRIVER
1/3
OPA3695
1/3
OPA3695
1/3
OPA3695
604W604W
604W
604W604W
301W301W
604W
V2
VOUT
V1
1/3
OPA3695
R
604
F
W
100W
V1
1/3
OPA3695
100W
V2
1/3
OPA3695
100W
V3
Selection
Logic
ADS828
10-Bit
75MSPS
0.1 Fm
0.1 Fm
4.99kW0.1 Fm
4.99kW0.1 Fm
100pF
REFT
+3.5V
REFB
+1.5V
+In
-In
CM
+5V
R
604
G
W
R
511
F
W
R
169
G
W
R
402
F
W
R
57.6
GW
OPA3695
SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008 ...............................................................................................................................................
www.ti.com
AMPLIFIER
The converter driver in Figure 42 multiplexes amongFigure 41 shows an instrumentation amplifier circuit the three input signals with gains of +2V/V, +4V/V,based on the OPA3695. Because all three amplifiers and +8V/V. The OPA3695 enable and disable timesare on the same silicon die, the offset matching support multiplexing among video signals. Thebetween inputs makes this configuration an attractive make-before-break disable characteristic of theinput stage for this application. The OPA3695 ensures that the output is always underdifferential-to-single-ended gain for this circuit is control. To avoid large switching glitches, it is best to2V/V. The inputs are high-impedance, with only 1.2pF switch when the signal on the amplifier inputs areto ground at each input. The loads on the OPA3695 very close to each other.outputs are equal for the best harmonic distortion
The voltage difference appearing between thepossible.
inverting node and the noninverting node should notexceed ± 1.2V. This difference can occur when theindividual amplifier is disabled and a voltage isapplied at the summing node of the three amplifiers.The resulting inverting node voltage of the disabledamplifier is easily calculated by using simple resistorvoltage divider methods. In general, as the gain of theamplifier increases, the less impact this issue has onthe system because of the increased R
F
/R
G
ratio.
The output resistors isolate the outputs from eachother when switching between channels. Thefeedback network of the disabled channels forms partof the load seen by the enabled amplifier, attenuatingthe signal slightly.Figure 41. High-Speed Instrumentation Amplifier
Figure 42. Multiplexed Converter Driver
16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA3695
DESIGN-IN TOOLS OUTPUT CURRENT AND VOLTAGE
DEMONSTRATION BOARDS
OPERATING SUGGESTIONS
GAIN SETTING
OPA3695
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............................................................................................................................................... SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008
The OPA3695 provides output voltage and currentcapabilities that can easily support multiple videoloads and/or 100 Ωloads with very low distortion.A printed circuit board (PCB) is available to assist in
Under no-load conditions at +25 ° C, the output voltagethe initial evaluation of circuit performance using the
typically swings to 1V of either supply rail. Into a 15 ΩOPA3695. The fixture is offered free of charge as an
load (the minimum tested load), it is tested to deliverunpopulated PCB, delivered with a user's guide. The
± 120mA.summary information for this fixture is shown in
The specifications described above, though familiar inTable 1 .
the industry, consider voltage and current limitsseparately. In many applications, it is the voltage ×Table 1. Demonstration Fixture
current, or V-I product, which is more relevant toORDERING LITERATURE
circuit operation. Refer to the Output Voltage andPRODUCT PACKAGE NUMBER NUMBER
Current Limitations plot (Figure 18 ) in the TypicalOPA3695IDBQ,
SSOP-16 DEM-OPA-SSOP-3C SBOU047noninverting
Characteristics . The X- and Y-axes of this graphshow the zero-voltage output current limit and theOPA3695IDBQ,
SSOP-16 DEM-OPA-SSOP-3D SBOU046inverting
zero-current output voltage limit, respectively. Thefour quadrants give a more detailed view of theThe demonstration fixture can be requested at the
OPA3695 output drive capabilities, noting that theTexas Instruments web site (www.ti.com ) through the
graph is bounded by a Safe Operating Area of 1WOPA3695 product folder .
maximum internal power dissipation. Superimposingresistor load lines onto the plot shows that theOPA3695 can drive ± 3.4V into 20 Ωor ± 3.7V into 50 Ωwithout exceeding either the output capabilities or the1W dissipation limit. A 100 Ωload line (the standardtest-circuit load) shows full ± 3.8V output swingSimilar to other current-feedback amplifiers, the
capability, as shown in the Typical Characteristics .OPA3695 compensation is dictated by the feedback
The minimum specified output voltage and currentresistor — R
F
. As the resistance increases, more
specifications over temperature are set by worst-casecompensation is added to the amplifier. It is important
simulations at the cold temperature extreme. Only atto realize that increasing the resistance too far is not
cold startup do the output current and voltagerecommended because this increase causes a zero
decrease to the numbers shown in theto form on the inverting input as a result of stray
over-temperature min/max specifications. As thecapacitance. In general, R
F
should not exceed 1.5k Ω
output transistors deliver power, the junctionto 2k Ω, or else stability is a concern. Table 2 shows
temperatures increase, which decreases the V
BE
sthe recommended feedback values for common gain
(increasing the available output voltage swing) andsettings. These values are a good starting point; fine
increases the current gains (increasing the availabletuning of the resistor value(s) should be done to
output current). In steady-state operation, theaccount for individual PCB designs and other factors.
available output voltage and current are alwaysgreater than that shown in the over-temperatureTable 2. Recommended Feedback Resistor — R
F
characteristics since the output stage junction± 5V OR 10V ± 2.5V OR 5V
temperatures are higher than the minimum specifiedGAIN (V/V) SUPPLY SUPPLY
operating ambient.+1 909 Ω750 Ω
To maintain maximum output stage linearity, no+2, – 1 604 Ω499 Ω
output short-circuit protection is provided. This+4 511 Ω453 Ω
configuration is not normally a problem, because+8 402 Ω348 Ω
most applications include a series matching resistorat the output that limits the internal power dissipation+16 249 Ω162 Ω
if the output side of this resistor is shorted to ground.However, shorting the output pin directly to anadjacent positive power-supply pin, in most cases,destroys the amplifier. If additional protection to apower-supply short is required, consider a smallseries resistor in the power-supply leads. Underheavy output loads, this resistor reduces the availableoutput voltage swing. A 5 Ωseries resistor in eachsupply lead, for example, limits the internal power
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
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DISTORTION PERFORMANCE
DRIVING CAPACITIVE LOADS
OPA3695
SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008 ...............................................................................................................................................
www.ti.com
dissipation to < 1W for an output short whiledecreasing the available output voltage swing only
The OPA3695 provides good distortion performance0.5V, for up to 100mA desired load currents. Always
into a 100 Ωload on ± 5V supplies. Relative toplace the 0.1 µF power-supply decoupling capacitors
alternative solutions, the OPA3695 holds much lowerafter these supply-current limiting resistors directly on
distortion at higher frequencies (> 20MHz) thanthe device supply pins.
alternative solutions. Generally, until the fundamentalsignal reaches very high-frequency or power levels,the second harmonic dominates the distortion with anegligible third-harmonic component. Focusing thenOne of the most demanding, and yet very common,
on the second harmonic, increasing the loadload conditions for an op amp is capacitive loading.
impedance improves distortion directly. RememberOften, the capacitive load is the input of an ADC,
that the total load includes the feedback network — inincluding additional external capacitance, which may
the noninverting configuration (see Figure 35 ), thisbe recommended to improve ADC linearity. A
value is the sum of R
F
+ R
G
, while in the invertinghigh-speed, high open-loop gain amplifier such as the
configuration it is only R
F
(see Figure 36 ). Also,OPA3695 can be very susceptible to decreased
providing an additional supply decoupling capacitorstability and may give closed-loop response peaking
(0.01 µF) between the supply pins (for bipolarwhen a capacitive load is placed directly on the
operation) improves the second-order distortionoutput pin. When the amplifier open-loop output
slightly (3dB to 6dB).resistance is considered, this capacitive loadintroduces an additional pole in the signal path,
The OPA3695 has very low third-order harmonicresulting in a feedback path zero that can decrease
distortion — especially with high gains. This featurethe phase margin. Several external solutions to this
also produces a high two-tone, third-orderproblem have been suggested. When the primary
intermodulation intercept. Two graphs for thisconsiderations are frequency response flatness,
intercept are given in the in the Typicalpulse response fidelity, and/or distortion, the simplest
Characteristics; one for ± 5V and one for +5V. Theand most effective solution is to isolate the capacitive
curves shown in each graph is defined at the 50 Ωload from the feedback loop by inserting a series
load when driven through a 50 Ωmatching resistor, toisolation resistor between the amplifier output and the
allow direct comparisons to RF MMIC devices.capacitive load. The isolation acts to reduce thephase lag from the capacitive load pole, thus The intercept is used to predict the intermodulationincreasing the phase margin and improving stability. spurious levels for two closely-spaced frequencies. Ifthe two test frequencies (f
1
and f
2
) are specified inThe Typical Characteristics show a Recommended
terms of average and delta frequency, f
O
= (f
1
+ f
2
)/2R
S
vs Capacitive Load curve (Figure 33 ) to help the
and Δf = |f
2
– f
1
|/2, then the two, 3rd-order, close-indesigner pick a value to give < 0.5dB peaking to the
spurious tones appear at f
O
± 3 × Δf. The differenceload. The resulting frequency response curves show
between two equal test tone power levels and thesea 0.5dB peaked response for several selected
intermodulation spurious power levels is given bycapacitive loads and recommended R
S
combinations.
ΔdBc = 2 × (IM
3
– P
O
), where IM
3
is the intercepttaken from the Typical Characteristics and P
O
is theParasitic capacitive loads greater than 2pF can begin
power level in dBm at the 50 Ωload for one of the twoto degrade the performance of the OPA3695. Long
closely-spaced test frequencies. For instance, atPCB traces, unmatched cables, and connections to
40MHz, the OPA3695 at a gain of +8V/V has another amplifier inputs can easily exceed this value.
intercept of 35dBm at a matched 50 Ωload. If the fullAlways consider this effect carefully and add the
envelope of the two frequencies must be 2V
PP
at thisrecommended series resistor as close as possible to
load, this requires each tone to be 4dBm (1V
PP
). Thethe OPA3695 output pin (see the Board Layout
third-order intermodulation spurious tones is then 2 ×Guidelines section).
(35 – 4) = 62dBc below the test tone power levelThe criterion for setting this R
S
resistor is a maximum
( – 79dBm).bandwidth, flat frequency response at the load( < 0.5dB peaking). For the OPA3695 operating at again of +2V/V, the frequency response at the outputpin is flat to begin with, allowing relatively smallvalues of R
S
to be used for low capacitive loads.
18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA3695
NOISE PERFORMANCE DC ACCURACY AND OFFSET CONTROL
= (NG V ) (I R /2 NG) (I R )± ´ OS BN S BI F
± ´ ´ ± ´
± ´ ± m ´ W ´ ± m ´ W
± ± ±
±
= (2 3.5mV) (30 A 25 2) (60 A 604 )
= 7mV 1.5mV 36.2mV
= 44.7mV
VOS
4kT
RG
RG
RF
RS
1/3
OPA3695
IBI
EO
IBN
4kT=1.6E 20J-
at290 K°
ERS
ENI
4kTRS
4kTRF
DISABLE OPERATION
E =
OE +(I R ) +4kTR
NI BN S S
2 2 NG +(I R ) +4kTR NG
BI F F
2 2
E =
NE +(I R ) +4kTR
NI BN S S +
2 2 4kTRF
NG
I R
BI F
NG
2
+
OPA3695
www.ti.com
............................................................................................................................................... SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008
The OPA3695 offers an excellent balance between A current-feedback op amp such as the OPA3695voltage and current noise terms to achieve a low provides exceptional bandwidth and slew rate, givingoutput noise under a variety of operating conditions. fast pulse settling but only moderate dc accuracy.The input noise voltage (1.8nV/ √Hz) is very low for a The Electrical Characteristics show an input offsetunity-gain stable amplifier. This low input voltage voltage comparable to high-speed voltage-feedbacknoise was achieved at the price of higher amplifiers. However, the two input bias currents arenoninverting input current noise (18pA/ √Hz). As long somewhat higher and are unmatched. Whereas biasas the ac source impedance looking out of the current cancellation techniques are very effective withnoninverting input is less than 100 Ω, this current most voltage-feedback op amps, they do notnoise does not contribute significantly to the total generally reduce the output dc offset for widebandoutput noise. The op amp input voltage noise and the current-feedback op amps. Because the two inputtwo input current noise terms combine to give low bias currents are unrelated in both magnitude andoutput noise using the OPA3695. Figure 43 shows polarity, matching the source impedance looking outthe op amp noise analysis model with all of the noise of each input to reduce the error contributions to theterms included. In this model, all noise terms are output is ineffective. Evaluating the configuration oftaken to be noise voltage or current density terms in Figure 35 using a gain of +2V/V, using worst-caseeither nV/ √Hz or pA/ √Hz. +25 ° C input offset voltage, and the two input biascurrents, gives a worst-case output offset range equalto:
where NG = noninverting signal gain.
Minimizing the resistance seen by the noninvertinginput also minimizes the output dc error. Forimproved dc precision in a wideband low-gainamplifier, consider the OPA842 where a bipolar inputis acceptable (low source resistance) or the OPA656where a JFET input is required.Figure 43. Op Amp Noise Model
The total output spot noise voltage can be computed
The OPA3695 provides an optional disable featureas the square root of the sum of all squared output
that can be used to reduce system power. If the V
DISnoise voltage contributors. Equation 1 shows the
control pin is left unconnected, the OPA3695general form for the output noise voltage using the
operates normally. This shutdown is intended only asterms shown in Figure 43 .
a power-savings feature. Forward path isolation whendisabled is very good for small signals whenconfigured for low gains. However, large-signalisolation is not ensured because of the ± 1.2V(1)
limitation between the inverting node and theDividing this expression through by noise gain (NG =
noninverting node. Failure to properly account for this1 + R
F
/R
G
) gives the equivalent input-referred spot
voltage may cause undesirable responses in thenoise voltage at the noninverting input, as shown in
output signal when multiplexed. Configuring theEquation 2 .
amplifier for high gains helps minimize this impact,but it is not ensured; proper analysis should be doneby the designer.
(2)
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s): OPA3695
THERMAL ANALYSIS
25kW
110kW
15kW
IS
Control
-VS
+VS
VDIS
Q1
P =10V 42.6mA+3 5 /(4 (100 ||1.2k ))=629mW´ W
D´ ´ W
2
MaximumT =+85 C+(0.629W 80 C/W)=135 C°
J´ ° °
OPA3695
SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008 ...............................................................................................................................................
www.ti.com
Turn-on time is very quick from the shutdowncondition (typically < 25ns). Turn-off time strongly
The OPA3695 does not require heatsinking or airflowdepends on the selected gain configuration and load,
in most applications. Maximum desired junctionbut is typically 1 µs for the circuit of Figure 35 . To shut
temperature sets the maximum allowed internaldown, the control pin must be asserted low. This logic
power dissipation as described here. In no casecontrol is referenced to the positive supply, as the
should the maximum junction temperature be allowedsimplified circuit of Figure 44 shows.
to exceed +150 ° C.
Operating junction temperature (T
J
) is given by T
A
+P
D
×θ
JA
. The total internal power dissipation (P
D
) isthe sum of quiescent power (P
DQ
) and additionalpower dissipated in the output stage (P
DL
) to deliverload power. Quiescent power is simply the specifiedno-load supply current times the total supply voltageacross the part. P
DL
depends on the required outputsignal and load but would, for a grounded resistiveload, be at a maximum when the output is fixed at avoltage equal to 1/2 either supply voltage (for equalbipolar supplies). Under this worst-case condition,P
DL
= V
S
2
/(4 × R
L
) where R
L
includes feedbacknetwork loading. This value is the absolute highestpower that can be dissipated for a given R
L
. All actualapplications dissipate less power in the output stage.
Note that it is the power in the output stage and notinto the load that determines internal powerFigure 44. Simplified Disable Control Circuit
dissipation.
In normal operation, base current to Q1 is provided As a worst-case example, compute the maximum T
Jthrough the 110k Ωresistor while the emitter current using an OPA3695IDBQ (SSOP-16 package) in thethrough the 15k Ωresistor sets up a voltage drop that circuit of Figure 35 operating at the maximumis inadequate to turn on the two diodes in the Q1 specified ambient temperature of +85 ° C and driving aemitter. As V
DIS
is pulled low, additional current is grounded 100 Ωload at V
S
/2. Maximum internalpulled through the 15k Ωresistor, eventually turning power is:on these two diodes ( ≈80 µA). At this point, anyfurther current pulled out of V
DIS
goes through thosediodes, holding the emitter-base voltage of Q1 atapproximately 0V. This sequence shuts off thecollector current out of Q1, turning the amplifier off.
Actual applications operate at a lower junctionThe supply current in the shutdown mode is only that
temperature than the +135 ° C computed above. Thisrequired to operate the circuit of Figure 44 .
condition is because the RMS voltage of the outputThe shutdown feature for the OPA3695 is a
signals vary, along with the fact that part of thepositive-supply-referenced, current-controlled
quiescent current is steered to the output, thusinterface. Open-collector (or drain) interfaces are
reducing the 10V × 42.6mA dominant term. Computemost effective, as long as the controlling logic can
the actual output stage power to get an accuratesustain the resulting voltage (in the open mode) that
estimate of maximum junction temperature, or useappears at the V
DIS
pin. That voltage is one diode
the results shown here as an absolute worst casebelow the positive supply voltage applied to the
maximum scenario.OPA3695. For voltage output logic interfaces, theon/off voltage levels described in the ElectricalCharacteristics apply only for a +5V positive supplyon the OPA3695. An open-drain interface isrecommended for shutdown operation using a higherpositive supply for the OPA3695 and/or logic familieswith inadequate high-level voltage swings.
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Product Folder Link(s): OPA3695
BOARD LAYOUT GUIDELINES
OPA3695
www.ti.com
............................................................................................................................................... SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008
feedback resistor, rather than a direct short, isrequired for the unity-gain follower application. AAchieving optimum performance with a
current-feedback op amp requires a feedbackhigh-frequency amplifier such as the OPA3695
resistor — even in the unity-gain followerrequires careful attention to PCB layout parasitics and
configuration — to control stability. Good axial metalexternal component types. Recommendations that
film or surface-mount resistors have approximatelyoptimize OPA3695 performance include:
0.2pF in shunt with the resistor. For resistor valuesgreater than 2.0k Ω, this parasitic capacitance cana) Minimize parasitic capacitance to any ac ground
add a pole and/or zero below 400MHz that can affectfor all of the signal I/O pins. Parasitic capacitance on
circuit operation. Keep resistor values as low asthe output can cause instability; on the noninverting
possible consistent with load driving considerations.input, it can react with the source impedance tocause unintentional bandlimiting. To reduce
d) Connections to other wideband devices on theunwanted capacitance, create a window around the
PCB may be made with short direct traces or throughsignal I/O pins in all of the ground and power planes
onboard transmission lines. For short connections,around those pins. Otherwise, ground and power
consider the trace and the input to the next device asplanes should be unbroken elsewhere on the board.
a lumped capacitive load. Relatively wide traces(50mils to 100mils, or 1,27mm to 2,54mm) should beb) Minimize the distance ( < 0.25 ” or 6,35mm) from
used, preferably with ground and power planesthe power-supply pins to high-frequency 0.1 µF
opened up around them. Estimate the total capacitivedecoupling capacitors. At the device pins, the ground
load and set R
S
from the plot of Recommended R
S
vsand power-plane layout should not be in close
Capacitive Load (Figure 33 ). Low parasitic capacitiveproximity to the signal I/O pins. Avoid narrow power
loads ( < 4pF) may not need an R
S
because theand ground traces to minimize inductance between
OPA3695 is nominally compensated to operate with athe pins and the decoupling capacitors. The
2pF parasitic load. If a long trace is required, and thepower-supply connections should always be
6dB signal loss intrinsic to a doubly-terminateddecoupled with these capacitors. Larger (2.2 µF to
transmission line is acceptable, implement a matched6.8 µF) decoupling capacitors, effective at lower
impedance transmission line using microstrip orfrequency, should also be used on the supply pins.
stripline techniques (consult an ECL design handbookThese capacitors may be placed somewhat farther
for microstrip and stripline layout techniques). A 50 Ωfrom the device and may be shared among several
environment is normally not necessary on board, anddevices in the same area of the PCB.
in fact, a higher impedance environment improvesc) Careful selection and placement of external
distortion, as shown in the distortion versus loadcomponents preserve the high-frequency
plots. With a characteristic board trace impedanceperformance of the OPA3695. Use resistors that
defined based on board material and tracehave low reactance at high frequencies.
dimensions, a matching series resistor into the traceSurface-mount resistors work best and allow a tighter
from the output of the OPA3695 is used, as well as aoverall layout. Metal film and carbon composition
terminating shunt resistor at the input of theaxially-leaded resistors can also provide good
destination device. Remember also that thehigh-frequency performance. Again, keep the leads
terminating impedance is the parallel combination ofand PCB trace length as short as possible. Never use
the shunt resistor and the input impedance of thewirewound type resistors in a high-frequency
destination device; this total effective impedanceapplication. The output pin and inverting input pin are
should be set to match the trace impedance. If thethe most sensitive to parasitic capacitance; therefore,
6dB attenuation of a doubly-terminated transmissionalways position the series output resistor, if any, as
line is unacceptable, a long trace can beclose as possible to the output pin. Other network
series-terminated at the source end only. Treat thecomponents, such as noninverting input termination
trace as a capacitive load in this case and set theresistors, should also be placed close to the package.
series resistor value as illustrated in the plot ofWhere double-side component mounting is allowed,
Figure 33 . This configuration does not preserve signalplace the feedback resistor directly under the
integrity as well as a doubly-terminated line. If thepackage on the other side of the board between the
input impedance of the destination device is low,output and inverting input pins. The frequency
there will be some signal attenuation as a result ofresponse is primarily determined by the feedback
the voltage divider formed by the series output intoresistor value, as described previously. Increasing its
the terminating impedance.value reduces the bandwidth, while decreasing itgives a more peaked frequency response. The 604 Ωfeedback resistor (used in the typical performancespecifications at a gain of +2V/V on ± 5V supplies) isa good starting point for design. Note that a 909 Ω
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): OPA3695
External
Pin
+VCC
-VCC
Internal
Circuitry
INPUT AND ESD PROTECTION
OPA3695
SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008 ...............................................................................................................................................
www.ti.com
e) Socketing a high-speed part such as theOPA3695 is not recommended. The additional leadlength and pin-to-pin capacitance introduced by thesocket can create an extremely troublesome parasiticnetwork, which can make it almost impossible toachieve a smooth, stable frequency response. Bestresults are obtained by soldering the OPA3695directly onto the board.
Figure 45. Internal ESD Protection
The OPA3695 is built using a very high-speed
These diodes provide moderate protection to inputcomplementary bipolar process. The internal junction
overdrive voltages above the supplies as well. Thebreakdown voltages are relatively low for these very
protection diodes can typically support 30mAsmall geometry devices. These breakdowns are
continuous current. Where higher currents arereflected in the Absolute Maximum Ratings table. All
possible (for example, in systems with ± 15V supplydevice pins are protected with internal ESD protection
parts driving into the OPA3695), current limitingdiodes to the power supplies, as shown in Figure 45 .
series resistors may be added on the noninvertinginput. Keep this resistor value as low as possible;high values degrade both noise performance andfrequency response.
22 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA3695
EVALUATION MODULE
OPA3695
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............................................................................................................................................... SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008
impedance, but it is not required. Attention to theTo evaluate the OPA3695, an evaluation module
voltage appearing at each disable pin is required to(EVM) is available. This EVM allows for testing the
ensure proper operation of this feature. The voltageOPA3695 in many different systems. Inputs and
at the disable pin is shown in the Electricaloutputs include SMA connectors commonly found in
Characteristics section of this data sheet.high-frequency systems along with 50 Ωcharacteristicimpedance traces. Because the traces are very short, This EVM is designed to be primarily used with splitchanging the input and output terminations resistors supplies from ± 2.5V up to ± 6V. This EVM can befrom 49.9 Ωto 75 Ωhas essentially no impact when used with a 5V single-supply up to 12V, but careevaluating video signals. Several unpopulated must be taken to account for the input terminationcomponent pads are found on the EVM to allow for resistor connections to ground. Adiitionally, the 100uFdifferent input and output configurations as dictated bypass capcitors C1 and C2 are rate at 10V. If singleby the user. supply is used with more than 10V applied, thesecapacitors should be changed to accomodate theBy default, all channels of the EVM are configured for
increased supply voltage. The OPA3695 allowablea noninverting gain of +2V/V. If inverting configuration
input range is defined in the Electrical Characteristicsor differential input configuration is desired, then
section of this datasheet and must be adhered to forsimply replacing R1, R4, and R7 with desired
proper operation. Also note that the gain settingresistors allows these configurations to be set up
resistors are also connected to ground. Thus, any dcquite easily. Also, the feedback and gain resistors
offset is increased proportionally by the gain. Ascan be easily replaced to allow for any gain desired.
such, using the EVM as a split supply isrecommended even if the final use is single-supply.Note that even though the default gain of the
Example: if the final usage is to be 12V single-supply,OPA3695 is +2V/V, or 6dB, the output 49.9 Ωsource
then using ± 6V supplies simplifies the dc referencetermination resistors (R13, R14, and R15) and the
voltage to mid-rail — or an equivalent 6V for auser-applied 50 Ωend-termination resistance
single-supply configuration.commonly found in test systems makes the overallsystem gain appear as 0dB.
Figure 46 shows the OPA3695EVM schematic.Figure 47 to Figure 50 illustrate the four layers of theEach channel's disable control is independently
EVM PCB, incorporating standard high-speed layoutconfigured. By default, the use of jumpers JP1, JP2,
practices. Table 3 lists the Bill of Materials for theand JP3 allows for a quick and easy method to
EVM as supplied from Texas Instruments.evaluate the disable function of the OPA3695.However, if this control must be externally controlled,then using the SMA connectors J10, J11, and J12 isrecommended. The termination resistors R19, R20,and R21 should to be changed to match the source
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Link(s): OPA3695
+
+
OPA3695
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www.ti.com
Figure 46. OPA3695D EVM Schematic
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Product Folder Link(s): OPA3695
OPA3695
www.ti.com
............................................................................................................................................... SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008
Figure 47. OPA3695D EVM PCB: Top Layer
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Product Folder Link(s): OPA3695
OPA3695
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www.ti.com
Figure 48. OPA3695D EVM PCB: Layer 2
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Product Folder Link(s): OPA3695
OPA3695
www.ti.com
............................................................................................................................................... SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008
Figure 49. OPA3695D EVM PCB: Layer 3
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Link(s): OPA3695
OPA3695
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Figure 50. OPA3695D EVM PCB: Bottom Layer
28 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA3695
OPA3695EVM Bill of Materials
OPA3695
www.ti.com
............................................................................................................................................... SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008
Table 3. OPA3695D EVM
MANUFACTURER DISTRIBUTORITEM REF DES QTY DESCRIPTION SMD SIZE PART NUMBER PART NUMBER
1 FB1, FB2 2 Bead, Ferrite, 3A, 80 Ω1206 (Steward) HI1206N800R-00 (Digi-Key) 240-1010-1-ND
Capacitor, 100 µF, Tantalum, 10V, 10%,2 C1, C2 2 C (AVX) TPSC107K010R0100 (Digi-Key) 478-1765-1-NDLow-ESR
3 C6, C10 2 Open 0603
4 C3 – C5, C7 – C9 6 Capacitor, 0.1 µF, Ceramic, 16V, X7R 0603 (AVX) 0603YC104KAT2A (Digi-Key) 478-1239-1-ND
(Garrett)5 R10 – R12 3 Resistor, 604 Ω, 1/16W, 1% 0402 (KOA) RK73H1ETTP6040F
RK73H1ETTP6040F
6 R16 – R18 3 Open 0603
(Digi-Key)7 R1, R4, R7 3 Resistor, 0 Ω, 1/10W 0603 (ROHM) MCR03EZPJ000
RHM0.0GCT-ND
R2, R5, R8, (Digi-Key)8 6 Resistor, 49.9 Ω, 1/10W, 1% 0603 (ROHM) MCR03EZPFX49R9R13 – R15 RHM49.9HCT-ND
(Digi-Key)9 R25 – R27 3 Resistor, 100 Ω, 1/10W, 1% 0603 (ROHM) MCR03EZPFX1000
RHM100HCT-ND
(Digi-Key)10 R3, R6, R9 3 Resistor, 604 Ω, 1/10W, 1% 0603 (ROHM) MCR03EZPFX6040
RHM604HCT-ND
(Digi-Key)11 R22 – R24 3 Resistor, 1k Ω, 1/10W, 1% 0603 (ROHM) MCR03EZPFX1001
RHM1.00KHCT-ND
(Digi-Key)12 R19 – R21 3 Resistor, 4.99k Ω, 1/10W, 1% 0603 (ROHM) MCR03EZPFX4991
RHM4.99KHCT-ND
13 J13 – J15 3 Jack, Banana Receptance, 0.25" dia. hole (SPC) 813 (Newark) 39N867
14 J1 – J12 12 Connector, edge, SMA PCB Jack (Johnson) 142-0701-801 (Newark) 90F2624
15 JP1 – JP3 3 Header, 0.1" CTRS, 0.025" square pins 2 possible (Sullins) PCB36SAAN (Digi-Key) S1011E-36-ND
16 JP1 – JP3 3 Shunts (Sullins) SSC02SYAN (Digi-Key) S9002-ND
17 4 Standoff, 4-40 hex, 0.625" length (Keystone) 1808 (Digi-Key) 1808K-ND
18 4 Screw, Phillips, 4-40, .250" (BF) PMS 440 0031 PH (Digi-Key) H343-ND
19 U1 1 IC, OPA3695DBQ (TI) OPA3695DBQ
20 1 Printed circuit board (TI) Edge# 6499960 Rev. A
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 29
Product Folder Link(s): OPA3695
OPA3695
SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008 ...............................................................................................................................................
www.ti.com
Revision History
Changes from Original (April 2008) to Revision A .......................................................................................................... Page
•Changed storage temperature range rating in Absolute Maximum Ratings table from – 40 ° C to +125 ° C to – 65 ° C to+125 ° C ................................................................................................................................................................................... 2•Added Evaluation Module section ....................................................................................................................................... 23
30 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s): OPA3695
OPA3695
www.ti.com
............................................................................................................................................... SBOS355A – APRIL 2008 – REVISED SEPTEMBER 2008
EVALUATION BOARD/KIT IMPORTANT NOTICE
Texas Instruments (TI) provides the enclosed product(s) under the following conditions:This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSESONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must haveelectronics training and observe good engineering practice standards. As such, the goods being provided are not intended to be completein terms of required design-, marketing-, and/or manufacturing-related protective considerations, including product safety and environmentalmeasures typically found in end products that incorporate such semiconductor components or circuit boards. This evaluation board/kit doesnot fall within the scope of the European Union directives regarding electromagnetic compatibility, restricted substances (RoHS), recycling(WEEE), FCC, CE or UL, and therefore may not meet the technical requirements of these directives or other related directives.Should this evaluation board/kit not meet the specifications indicated in the User ’ s Guide, the board/kit may be returned within 30 days fromthe date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY SELLER TO BUYERAND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OFMERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE.The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user indemnifies TI from all claimsarising from the handling or use of the goods. Due to the open construction of the product, it is the user ’ s responsibility to take any and allappropriate precautions with regard to electrostatic discharge.EXCEPT TO THE EXTENT OF THE INDEMNITY SET FORTH ABOVE, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANYINDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.TI currently deals with a variety of customers for products, and therefore our arrangement with the user is not exclusive.
TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents orservices described herein.
Please read the User ’ s Guide and, specifically, the Warnings and Restrictions notice in the User ’ s Guide prior to handling the product. Thisnotice contains important safety information about temperatures and voltages. For additional information on TI ’ s environmental and/orsafety programs, please contact the TI application engineer or visit www.ti.com/esh .No license is granted under any patent right or other intellectual property right of TI covering or relating to any machine, process, orcombination in which such TI products or services might be or are used.
FCC Warning
This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSESONLY and is not considered by TI to be a finished end-product fit for general consumer use. It generates, uses, and can radiate radiofrequency energy and has not been tested for compliance with the limits of computing devices pursuant to part 15 of FCC rules, which aredesigned to provide reasonable protection against radio frequency interference. Operation of this equipment in other environments maycause interference with radio communications, in which case the user at his own expense will be required to take whatever measures maybe required to correct this interference.
EVM WARNINGS AND RESTRICTIONS
It is important to operate this EVM within the input voltage range of ± 1.7V to ± 6.5V dual supply and the output voltage range of 0V to ± 6.5V.Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questionsconcerning the input range, please contact a TI field representative prior to connecting the input power.Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.Please consult the EVM User's Guide prior to connecting any load to the EVM output. If there is uncertainty as to the load specification,please contact a TI field representative.During normal operation, some circuit components may have case temperatures greater than +85 ° C. The EVM is designed to operateproperly with certain components above +85 ° C as long as the input and output ranges are maintained. These components include but arenot limited to linear regulators, switching transistors, pass transistors, and current sense resistors. These types of devices can be identifiedusing the EVM schematic located in the EVM User's Guide. When placing measurement probes near these devices during operation,please be aware that these devices may be very warm to the touch.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2008, Texas Instruments Incorporated
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 31
Product Folder Link(s): OPA3695
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
OPA3695IDBQ ACTIVE SSOP DBQ 16 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OP3695
OPA3695IDBQR ACTIVE SSOP DBQ 16 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 OP3695
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jun-2014
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
OPA3695IDBQR SSOP DBQ 16 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA3695IDBQR SSOP DBQ 16 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP-.244.228
-6.195.80[ ]
.069 MAX
[1.75]
14X .0250
[0.635]
16X -.012.008
-0.300.21[ ]
2X
.175
[4.45]
TYP-.010.005
-0.250.13[ ]
0- 8 -.010.004
-0.250.11[ ]
(.041 )
[1.04]
.010
[0.25]
GAGE PLANE
-.035.016
-0.880.41[ ]
A
NOTE 3
-.197.189
-5.004.81[ ]
B
NOTE 4
-.157.150
-3.983.81[ ]
SSOP - 1.75 mm max heightDBQ0016A
SHRINK SMALL-OUTLINE PACKAGE
4214846/A 03/2014
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 inch, per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MO-137, variation AB.
116
.007 [0.17] C A B
9
8
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.002 MAX
[0.05]
ALL AROUND
.002 MIN
[0.05]
ALL AROUND
(.213)
[5.4]
14X (.0250 )
[0.635]
16X (.063)
[1.6]
16X (.016 )
[0.41]
SSOP - 1.75 mm max heightDBQ0016A
SHRINK SMALL-OUTLINE PACKAGE
4214846/A 03/2014
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
OPENING
SOLDER MASK METAL
SOLDER MASK
DEFINED
LAND PATTERN EXAMPLE
SCALE:8X
SYMM
1
89
16
SEE
DETAILS
www.ti.com
EXAMPLE STENCIL DESIGN
16X (.063)
[1.6]
16X (.016 )
[0.41]
14X (.0250 )
[0.635]
(.213)
[5.4]
SSOP - 1.75 mm max heightDBQ0016A
SHRINK SMALL-OUTLINE PACKAGE
4214846/A 03/2014
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.127 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
89
16
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