This document contains information on a product under development at Advanced Micro Devices, Inc. The information is intended
to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication #: 20068 Rev. A Amendment: /0
Issue Date: May 1997
Am29240 EH, Am29245 EH, and
Am29243 EH
Enhanced High-Performance RISC Microcontrollers
5/2/97
PRELIMINARY
DISTINCTIVE CHARACTERISTICS
All three microcontrollers in the Am29240EH micro-
controller series have the following characteristics:
Completely integrated system for embedded
applications
Full 32-bit architecture
4-Kbyte, two-way set-associative instruction
cache
4-Gbyte virtual address space, 304-Mbyte
physical space implemented
Glueless system interfaces with on-chip wait
state control
36 VAX MIPS (million instructions per second)
sustained at 25 MHz
Four banks of ROM, each separately
programmable for 8-, 16-, or 32-bit interface
Four banks of DRAM
Single-cycle ROM burst-mode and DRAM
page-mode access
DRAM timing is software-programmable for 3/1
or 2/1 initial/burst access cycles
6-port peripheral interface adapter
16-line programmable I/O port
Bidirectional parallel port controller
Interrupt controller
Fully pipelined integer unit
Three-address instruction architecture
192 general purpose registers
Traceable Cache technology instruction and
data cache tracing
IEEE Std 1149.1-1990 (JTAG) compliant
Standard Test Access Port and
Boundary Scan Architecture
Binary compatibility with all 29K family
microprocessors and microcontrollers
CMOS technology/TTL compatible
208-pin Plastic Quad Flat Pack (PQFP) package
3.3-V power supply with 5-V-tolerant I/O
Am29240EH Microcontroller
The Am29240EH microcontroller has the following addi-
tional features:
2-Kbyte, two-way set-associative data cache
Single-cycle 32-bit multiplier for faster integer
math; two-cycle Multiply Accumulate (MAC)
function
16-entry on-chip Memory Management Unit
(MMU) with one Translation Look-Aside Buffer
4-channel double-buffered DMA controller with
queued reload
Two serial ports (UARTs)
Bidirectional bit serializer/deserializer
20- and 25-MHz operating frequencies
Am29243EH Microcontroller
The Am29243EH data microcontroller is similar to the
Am29240EH microcontroller, without the video inter-
face. It includes the following features:
2-Kbyte, two-way set-associative data cache
Single-cycle 32-bit multiplier for faster integer
math; two-cycle MAC
32-entry on-chip MMU with dual TLBs
4-channel, double-buffered DMA controller with
queued reload
Two serial ports (UARTs)
20- and 25-MHz operating frequencies
DRAM parity
Am29245EH Microcontroller
The low-cost Am29245EH microcontroller is similar to
the Am29240EH microcontroller, without the data cache
and 32-bit multiplier. It includes the following features:
16-entry on-chip MMU with one TLB
Two-channel DMA controller
One serial port (UART)
Bidirectional bit serializer/deserializer
16-MHz operating frequency
P R E L I M I N A R Y
2Am29240 EH Microcontroller Series
Am29240EH MICROCONTROLLER BLOCK DIAGRAM
Interrupts, T raps
DRAM
Space
ROM
Memory
Serial Ports
Parallel Port
Controller 4-Channel DMA
Controller
Programmable
Interrupt
DRAM Controller
Timer/Counter
I/O Port
Controller
Serializer/
Deserializer
ROM
Controller
PIA
Controller
Am29000 CPU
Peripherals
62432
PIA
Chip Selects Address
Bus Instruction/Data
Bus
4
4 6 16 6
4/4
ROM
Chip Selects
Serial
Data
Printer/Scanner
Video
I/O
611
Parallel Port
Control/Status
Lines
Dual
2K DCache
32x32 Multiply
MMU
4K ICache
4 DREQ
58
Clock/
Lines
Control
JTAG
4
STAT
MEMCLK 4 DACK
GREQ/GACK/TDMA
RAS/CAS
Am29245EH MICROCONTROLLER BLOCK DIAGRAM
Interrupts, T raps
DRAM
Space
ROM
Memory
Serial Port
Parallel Port
Controller 2-Channel DMA
Controller
Programmable
Interrupt
DRAM Controller
Timer/Counter
I/O Port
Controller
Serializer/
Deserializer
ROM
Controller
PIA
Controller
Am29000 CPU
Peripherals
62432
PIA
Chip Selects Address
Bus Instruction/Data
Bus
4
4 4 16 6
4/4
ROM
Chip Selects
Serial
Data
Printer/Scanner
Video
I/O
67
Parallel Port
Control/Status
Lines
Single
MMU
4K ICache
2 DREQ
58
Clock/
Lines
Control
JTAG
4
STAT
MEMCLK 2 DACK
GREQ/GACK/TDMA
RAS/CAS
P R E L I M I N A R Y
3
Am29240 EH Microcontroller Series
Am29243EH MICROCONTROLLER BLOCK DIAGRAM
Interrupts, T raps
DRAM
Space
ROM
Memory
Serial Ports
Parallel Port
Controller 4-Channel DMA
Controller
Programmable
Interrupt
DRAM Controller
Timer/Counter
I/O Port
Controller
ROM
Controller
PIA
Controller
Am29000 CPU
Peripherals
62432
PIA
Chip Selects Address
Bus Instruction/Data
Bus
4
5 6 16 6
4/4
ROM
Chip Selects
Serial
Data I/O
611
Parallel Port
Control/Status
Lines
Dual
2K DCache
32x32 Multiply
MMU
4K ICache
4 DREQ
8
Clock/
Lines
Control
4
STAT
MEMCLK 4 DACK
GREQ/GACK/TDMA
36
32
RAS/CAS
5
JTAG
DRAM Parity
CUSTOMER SERVICE
AMD’s customer service network includes U.S. offices,
international offices, and a customer training center . Ex-
pert technical assistance is available from AMD’s world-
wide staff of field application engineers and support staff.
For answers to technical questions, AMD provides a
toll-free number for direct access to our corporate ap-
plications hotline. Also available is the AMD World Wide
Web home page and FTP site, which provides the latest
29K family product information.
Corporate Applications Hotline
(800) 222-9323, option 5 toll-free for U.S.
44-(0) 1276-803-299 U.K. and Europe hotline
Engineering Support
lpd.support@amd.com e-mail
World Wide Web Home Page and FTP Site
To access the AMD home page on the web, go to:
http:/www.amd.com. Questions, requests, and input
concerning AMD’s WWW pages can be sent via e-mail
to webmaster@amd.com.
To download documents and software, ftp to
ftp.amd.com and log on as anonymous using your e-mail
address as a password. Or, with your web browser, go to
ftp://ftp.amd.com.
Documentation and Literature
A simple phone call gets you free 29K family informa-
tion such as data sheets, user ’s manuals, application
notes, the Fusion29K Partner Solutions Catalog, and
other literature. Internationally , contact your local AMD
sales office for complete 29K family literature.
Literature Ordering
(800) 222-9323, option 3 toll-free for U.S.
(512) 602-5651 direct dial worldwide
(800) 222-9323, option 2 AMD Facts-On-Demand
fax information service
toll-free for U.S., Canada
RELATED DOCUMENTS
The
Am29240EH, Am29245EH, and Am29243EH
RISC Microcontrollers User’s Manual
(order #17741)
describes the technical features, programming inter-
face, on-chip peripherals, register set, and instruction
set for the Am29240EH microcontroller series.
Programming the 29K RISC Family
(order #19243) in-
cludes comprehensive information about the 29K family
for the software developer.
P R E L I M I N A R Y
4Am29240 EH Microcontroller Series
GENERAL DESCRIPTION
The Am29240EH microcontroller series is an enhanced
bus-compatible extension of the Am29200 RISC mi-
crocontroller family, with two to four times the perfor-
mance. The Am29240EH microcontroller series
includes the Am29240EH microcontroller, the low-cost
Am29245EH microcontroller, and the Am29243EH data
microcontroller. The on-chip caches, MMU, faster inte-
ger math, and extended DMA addressing capability of
the Am29240EH microcontroller series allow the em-
bedded systems designer to provide increasing levels of
performance and software compatibility throughout a
range of products (see Table 1 on page 6).
Based on a low-voltage CMOS-technology design,
these devices offer a complete set of system peripherals
and interfaces commonly used in embedded applica-
tions. Compared to CISC processors, the Am29240EH
microcontroller series offers better performance, more
efficient use of low-cost memories, lower system cost,
and complete design flexibility for the designer. Coupled
with hardware and software development tools from the
AMD Fusion29K partners, the Am29240EH microcon-
troller series provides the embedded product designer
with the cost and performance edge required by today’s
marketplace.
For a complete description of the technical features, on-
chip peripherals, programming interface, register set,
and instruction set, please refer to the
Am29240EH,
Am29245EH, and Am29243EH RISC Microcontrollers
User’s Manual
(order #17741).
Am29240EH Microcontroller
For general-purpose embedded applications, such as
mass-storage controllers, communications, digital sig-
nal processing, networking, industrial control, pen-
based systems, and multimedia, the Am29240EH
microcontroller provides a high-performance solution
with a low total-system cost. The memory interface of
the Am29240EH microcontroller provides even faster
direct memory access than the Am29200 microcontrol-
ler. This performance improvement minimizes the effect
of memory latency, allowing designers to use low-cost
memory with simpler memory designs. On-chip instruc-
tion and data caches provide even better performance
for time-critical code.
Other on-chip functions include: a ROM controller,
DRAM controller, peripheral interface adapter control-
ler , DMA controller, programmable I/O port, parallel port
controller, serial ports, and an interrupt controller.
Am29245EH Microcontroller
The low-cost Am29245EH microcontroller is designed
for embedded applications in which cost and space
constraints, along with increased performance require-
ments, are primary considerations.
The Am29245EH microcontroller also provides an easy
upgrade path for Am29200, Am29202, and
Am29205 microcontroller-based products.
Am29243EH Microcontroller
With DRAM parity support and a full MMU, the
Am29243EH data microcontroller is recommended for
communications applications that require high-speed
data movement and fast protocol processing in a fault-
tolerant environment.
Both the Am29243EH and Am29240EH microcontrol-
lers support fly-by DMA at 100 Mbytes/s for LANs and
switching applications, and a two-cycle Multiply Accu-
mulate function for DSP applications. The low power re-
quirements make either microcontroller a good choice
for field-deployed devices.
Development Support Products
The Fusion29K Program of Partnerships for Application
Solutions provides the user with a vast array of products
designed to meet critical time-to-market needs. Prod-
ucts/solutions available from the AMD Fusion29K part-
ners include the following:
Optimizing compilers for common high-level
languages
Assembler and utility packages
Source- and assembly-level software debuggers
Target-resident development monitors
Simulators
Execution boards
Hardware development tools
Silicon products
Board-level products
Laser-printer solutions
Multiuser, kernel, and real-time operating systems
Graphics solutions
Networking and communication solutions
Manufacturing support
Custom software consulting, support, and training
P R E L I M I N A R Y
5
Am29240 EH Microcontroller Series
ORDERING INFORMATION
Standard Products
AMDr standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
Am29240EH –25 C
TEMPERATURE RANGE
C = Commercial (TC = 0°C to +85°C)
PACKAGE TYPE
K = 208-Lead Plastic Quad Flat Pack (PQR 208)
SPEED OPTION
DEVICE NUMBER/DESCRIPTION
Am29240EH Enhanced RISC Microcontroller
Am29245EH Enhanced RISC Microcontroller
Am29243EH Enhanced RISC Data Microcontroller
Valid Combinations
Valid Combinations lists configurations
planned to be supported in volume. Consult
the local AMD sales office to confirm
availability of specific valid combinations, to
check on newly released combinations, and
to obtain additional data on AMD standard
military grade products.
Valid Combinations
–25 = 25 MHz
–20 = 20 MHz
–16 = 16 MHz
K\W
PROCESSING
\W = Trimmed and Formed
Am29240EH–20 KC\W
Am29243EH–20
Am29245EH–16 KC\W
Am29240EH–25
KC\W
Am29243EH–25
RELATED AMD PRODUCTS
29K Family Devices
Product Description
Am29000R32-bit RISC microprocessor
Am29005Low-cost 32-bit RISC microprocessor with no MMU and no branch target cache
Am2903032-bit RISC microprocessor with 8-Kbyte instruction cache
Am2903532-bit RISC microprocessor with 4-Kbyte instruction cache
Am2904032-bit RISC microprocessor with 8-Kbyte instruction cache and 4-Kbyte data cache
Am2905032-bit RISC microprocessor with on-chip floating point
Am2920032-bit RISC microcontroller
Am29202Low-cost 32-bit RISC microcontroller with IEEE-1284-compliant parallel interface
Am29205Low-cost 32-bit RISC microcontroller
P R E L I M I N A R Y
6Am29240 EH Microcontroller Series
Table 1. Product Comparison—Am29200 Microcontroller Family
FEATURE Am29205
Controller Am29202
Controller Am29200
Controller Am29245EH
Controller Am29240EH
Controller Am29243EH
Controller
Instruction Cache — — — 4 Kbytes 4 Kbytes 4 Kbytes
Data Cache — — — — 2 Kbytes 2 Kbytes
Cache Associativity — — — 2-way 2-way 2-way
Integer Multiplier Software Software Software Software 32 x 32-bit 32 x 32-bit
Memory Management
Unit (MMU) — — — 1 TLB
16 Entry 1 TLB
16 Entry 2 TLBs
32 Entry
Data Bus Width
Internal
External 32 bits
16 bits 32 bits
32 bits 32 bits
32 bits 32 bits
32 bits 32 bits
32 bits 32 bits
32 bits
ROM Interface
Banks
Width
ROM Size (Max/Bank)
Boot-Up ROM Width
Burst-Mode Access
3
8, 16 bits
4 Mbytes
16 bits
Not Supported
4
8, 16, 32 bits
4 Mbytes
8, 16, 32 bits
Not Supported
4
8, 16, 32 bits
16 Mbytes
8, 16, 32 bits
Supported
4
8, 16, 32 bits
16 Mbytes
8, 16, 32 bits
Supported
4
8, 16, 32 bits
16 Mbytes
8, 16, 32 bits
Supported
4
8, 16, 32 bits
16 Mbytes
8, 16, 32 bits
Supported
DRAM Interface
Banks
Width
Size: 32-Bit Mode
Size: 16-Bit Mode
Video DRAM
Access Cycles
Initial/Burst
DRAM Parity
4
16 bits only
—
8 Mbytes/bank
Not Supported
3/2
No
4
16, 32 bits
16 Mbytes/bank
8 Mbytes/bank
Not Supported
3/2
No
4
16, 32 bits
16 Mbytes/bank
8 Mbytes/bank
Supported
3/2
No
4
32 bits
16 Mbytes/bank
Not supported
Supported
2/1 or 3/1
No
4
32 bits
16 Mbytes/bank
Not supported
Supported
2/1 or 3/1
No
4
32 bits
16 Mbytes/bank
Not supported
Not Supported
2/1 or 3/1
Yes
On-Chip DMA
Width (ext. peripherals)
Total Number of Channels
Externally Controlled
External Master Access
External Master Burst
External Terminate Signal
8, 16 bits
2
1
No
No
No
8, 16, 32 bits
2
1
No
No
No
8, 16, 32 bits
2
2
Yes
No
Yes
8, 16, 32 bits
2
2
Yes
Yes
Yes
8, 16, 32 bits
4
4
Yes
Yes
Yes
8, 16, 32 bits
4
4
Yes
Yes
Yes
Low-Voltage Operation No No No Yes Yes Yes
Peripheral Interface
Adapter (PIA)
PIA Ports
Data Width
Min. Cycles Access
2
8, 16 bits
3
2
8, 16, 32 bits
3
6
8, 16, 32 bits
3
6
8, 16, 32 bits
1
6
8, 16, 32 bits
1
6
8, 16, 32 bits
1
Programmable I/O Port
(PIO)
Signals
Signals programmable
for interrupt generation
8
8
12
8
16
8
16
8
16
8
16
8
Serial Ports
Ports
DSR/DTR 1 Port
PIO signals 1 Port
PIO signals 1 Port
Supported 1 Port
Supported 2 Ports
1 Port Supported 2 Ports
1 Port Supported
Interrupt Controller
External Interrupt Pins
External T rap and Warn
Pins
2
0
2
0
4
3
4
3
4
3
4
3
Parallel Port Controller
32-Bit T ransfer
IEEE-1284 Interface
Yes
No
No
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
Yes
Yes
No
JTAG Debug Support No Yes Yes Yes Yes Yes
Serializer/Deserializer Yes Yes Yes Yes Yes No
Pin Count and Package 100 PQFP 132 PQFP 168 PQFP 208 PQFP 208 PQFP 208 PQFP
Operating Voltage
VCC
I/O Tolerance 5 V
5 V 5 V
5 V 5 V
5 V 3.3 V
5 V 3.3 V
5 V 3.3 V
5 V
Processor Clock Rate 12, 16 MHz 12, 16, 20 MHz 16, 20 MHz 16 MHz 20, 25 MHz 20, 25 MHz
P R E L I M I N A R Y
7
Am29240 EH Microcontroller Series
KEY FEATURES AND BENEFITS
The Am29240EH microcontroller series extends the line
of RISC microcontrollers based on 29K family architec-
ture, providing performance upgrades to the Am29205
and Am29200 microcontrollers. The RISC microcontrol-
ler product line allows users to benefit from the very high
performance of the 29K family architecture, while also
capitalizing on the very low system cost made possible
by integrating processor and peripherals.
The Am29240EH microcontroller series expands the
price/performance range of systems that can be built
with the 29K family. The Am29240EH microcontroller
series is fully software compatible with the Am29000,
Am29005, Am29030, Am29035, Am29040, and
Am29050 microprocessors, as well as the Am29200
and Am29205 microcontrollers. It can be used in exist-
ing 29K family microcontroller applications without soft-
ware modifications.
On-Chip Caches
The Am29240EH microcontroller series incorporates a
4-Kbyte, two-way instruction cache that supplies most
processor instructions without wait states at the proces-
sor frequency. For best performance, the instruction
cache supports critical-word-first reloading with fetch-
through, so that the processor receives the required
instruction and the pipeline restarts with minimum delay.
The instruction cache has a valid bit per word to mini-
mize the reload overhead. All cache array elements are
visible to software for testing and preload.
The Am29240EH and Am29243EH microcontrollers in-
corporate a 2-Kbyte, two-way set-associative data
cache. The data cache appears in the execute stage of
the processor pipeline, so that loaded data is available
immediately to the next instruction. This provides the
maximum performance for loads without requiring load
scheduling. This minimizes the time the processor waits
on external data as well as minimizing the reload time.
The data cache uses a write-through policy with a two-
entry write buffer. Byte, half-word, and word reads and
writes are supported. All cache array elements are vis-
ible to software for testing and preload.
Single-Cycle Multiplier
The Am29240EH and Am29243EH microcontrollers
incorporate a full combinatorial multiplier that accepts
two 32-bit input operands and produces a 32-bit result
in a single cycle. The multiplier can produce a 64-bit re-
sult in two cycles. The multiplier permits maximum per-
formance without requiring instruction scheduling,
since the latency of the multiply is the same as the la-
tency of other integer operations. High-performance
multiplication benefits imaging, signal processing, and
state modeling applications.
Complete Set of Common Peripherals
The Am29240EH microcontroller series minimizes sys-
tem cost by incorporating a complete set of system facili-
ties commonly found in embedded applications,
eliminating the cost of additional components. The on-
chip functions include: a ROM controller, a DRAM con-
troller, a peripheral interface adapter , a DMA controller,
a programmable I/O port, a parallel port, up to two serial
ports, and an interrupt controller. A video interface is
also included in the Am29240EH and Am29245EH mi-
crocontrollers for printer, scanner, and other imaging ap-
plications. These facilities allow many simple systems to
be built using only the Am29240EH microcontroller se-
ries, external ROM, and/or DRAM memory.
ROM Controller
The ROM controller supports four individual banks of
ROM or other static memory, each with its own timing
characteristics. Each ROM bank may be a different size
and may be either 8, 16, or 32 bits wide. The ROM banks
can appear as a contiguous memory area of up to 64
Mbytes in size. The ROM controller also supports byte,
half-word, and word writes to the ROM memory space
for devices such as flash EPROMs and SRAMs.
DRAM Controller
The DRAM controller supports four separate banks of
dynamic memory. Each bank may be a different size and
must be 32 bits wide. The DRAM banks can appear as a
contiguous memory area of up to 64 Mbytes in size. The
DRAM controller supports two- or three-cycle accesses
(programmable by software), with single-cycle page-
mode and burst-mode accesses. Burst accesses are
supported at two initial, one burst, or three initial, one
burst.
Peripheral Interface Adapter
The Peripheral Interface Adapter (PIA) permits glueless
interfacing to as many as six external peripheral chips.
The PIA allows for additional system features imple-
mented by external peripheral chips.
DMA Controller
The DMA controller provides up to four channels for
transferring data between the DRAM and internal or ex-
ternal peripherals.
Fly-by DMA transfers data directly between an external
peripheral and DRAM or ROM, permitting very high data
bandwidth. The peripheral must support the timing of
the memory (DRAM or ROM). The transfer occurs at the
rate of one 32-bit word per cycle, if DRAM page-mode
accesses or ROM burst-mode or single-cycle accesses
are enabled.
For page-mode DRAM, the TDMA signal is asserted on
the rising edge following the last access. For an initial
access, TDMA is asserted simultaneously with DACKx.
DMA wait states and peripheral wait states are ignored
P R E L I M I N A R Y
8Am29240 EH Microcontroller Series
during fly-by transfers. A higher fly-by DMA transfer can
interrupt a lower fly-by transfer.
Refresh does not pre-empt a fly-by transfer. A DMA
transfer continues until either DREQx is deasserted, the
transfer is interrupted by a higher priority DMA, or the
Count Terminate Enable (CTE) bit is set. No refreshes
will occur until the fly-by transfer is completed, so fly-by
transfers must be less than one refresh interval in
length. The DREQx signal must be configured as level-
sensitive in the DRAM Control Register.
Parity checking and generation cannot be performed
during a fly-by transfer. Note also that zero-wait-state
ROM cannot be used with fly-by DMA.
I/O Port
The I/O port permits direct access to 16 individually pro-
grammable external input/output signals. Eight of these
signals can be configured to cause interrupts.
Parallel Port
The parallel port implements a bidirectional IBM PC-
compatible parallel interface to a host processor.
Serial Port
The serial port implements up to two full-duplex UARTs.
Serializer/Deserializer
The serializer/deserializer (video interface) on the
Am29240EH and Am29245EH microcontrollers permits
direct connection to a number of laser-marking engines,
video displays, or raster input devices such as scanners.
Interrupt Controller
The interrupt controller generates and reports the status
of interrupts caused by on-chip peripherals.
Wide Range of Price/Performance Points
To reduce design costs and time-to-market, the product
designer can use the Am29200 microcontroller family
and one basic system design as the foundation for an
entire product line. From this design, numerous imple-
mentations of the product at various levels of price and
performance may be derived with minimum time, effort,
and cost.
The Am29240EH RISC microcontroller series supports
this capability through various combinations of on-chip
caches, programmable memory widths, programmable
wait states, burst-mode and page-mode access sup-
port, bus compatibility , and 29K family software compat-
ibility . A system can be upgraded using various memory
architectures without hardware and software redesign.
The ROM controller accommodates memories that are
either 8, 16, or 32 bits wide, and the DRAM controller ac-
commodates dynamic memories that are 32 bits wide.
This unique feature provides a flexible interface to low-
cost memory, as well as a convenient, flexible upgrade
path. For example, a system can start with a 16-bit ROM
memory design and can subsequently improve perfor-
mance by migrating to a 32-bit ROM memory design.
One particular advantage is the ability to add memory in
half-megabyte increments. This provides significant
cost savings for applications that do not require larger
memory upgrades.
The Am29200, Am29202, Am29205, Am29240,
Am29245, and Am29243EH microcontrollers allow us-
ers to address an extremely wide range of cost perfor-
mance points, with higher performance and lower cost
than existing designs based on CISC microprocessors.
Glueless System Interfaces
The Am29240EH microcontroller series also minimizes
system cost by providing a glueless attachment to exter-
nal ROMs, DRAMs, and other peripheral components.
Processor outputs have edge-rate control that allows
them to drive a wide range of load capacitances with low
noise and ringing. This eliminates the cost of external
logic and buffering.
Bus and Software Compatibility
Compatibility within a processor family is critical for
achieving a rational, easy upgrade path. Processors in
the Am29240EH microcontroller series are all members
of a bus-compatible family of RISC microcontrollers. All
members of this family—the Am29205, Am29202,
Am29200, Am29240, Am29245, and Am29243EH mi-
crocontrollers—allow improvements in price, perfor-
mance, and system capabilities without requiring that
users redesign their system hardware or software. Bus
compatibility ensures a convenient upgrade path for fu-
ture systems.
The Am29240EH microcontroller series is available in a
208-pin plastic quad flat-pack (PQFP) package. The
Am29240EH microcontroller series is signal-compatible
with the Am29200 and the Am29205 microcontrollers.
Moreover, the Am29240EH microcontroller series is
binary compatible with existing RISC microcontrollers
and other members of the 29K family (the Am29000,
Am29005, Am29030, Am29035, Am29040, and
Am29050 microprocessors, as well as the Am29200,
Am29202, and Am29205 microcontrollers). The
Am29240EH microcontroller series provides a migra-
tion path to low-cost, high-performance, highly inte-
grated systems from other 29K family members,
without requiring expensive rewrites of application
software.
Debugging and Testing
The Am29240EH microcontroller series provides de-
bugging and testing features at both the software and
hardware levels.
P R E L I M I N A R Y
9
Am29240 EH Microcontroller Series
Software debugging is facilitated by the instruction
trace facility and instruction breakpoints. Instruction
tracing is accomplished by forcing the processor to trap
after each instruction has been executed. Instruction
breakpoints are implemented by the HALT instruction
or by a software trap.
The processor provides several additional features to
assist system debugging and testing:
The Test/Development Interface is composed of a
group of pins that indicate the state of the processor
and control the operation of the processor.
A Traceable Cache feature permits a hardware-
development system to track accesses to the on-
chip caches, permitting a high level of visibility into
processor operation.
An IEEE Std 1149.1-1990 (JTAG) compliant Stan-
dard T est Access Port and Boundary-Scan Architec-
ture. The Test Access Port provides a scan interface
for testing processor and system hardware in a pro-
duction environment, and contains extensions that
allow a hardware-development system to control
and observe the processor without interposing hard-
ware between the processor and system.
PERFORMANCE OVERVIEW
The Am29240EH microcontroller series offers a signifi-
cant margin of performance over CISC microprocessors
in existing embedded designs, since the majority of pro-
cessor features were defined for the maximum achiev-
able performance at very low cost. This section
describes the features of the Am29240EH microcontrol-
ler series from the point of view of system performance.
Instruction Timing
The Am29240EH microcontroller series uses an arith-
metic/logic unit, a field shift unit, and a prioritizer to
execute most instructions. Each of these is organized to
operate on 32-bit operands and provide a 32-bit result.
All operations are performed in a single cycle.
The performance degradation of load and store opera-
tions is minimized in the Am29240EH microcontroller
series by overlapping them with instruction execution,
by taking advantage of pipelining, by an on-chip data
cache, and by organizing the flow of external data into
the processor so that the impact of external accesses is
minimized.
Pipelining
Instruction operations are overlapped with instruction
fetch, instruction decode and operand fetch, instruction
execution, and result write-back to the Register File.
Pipeline forwarding logic detects pipeline dependencies
and routes data as required, avoiding delays that might
arise from these dependencies. Pipeline interlocks are
implemented by processor hardware. Except for a few
special cases, it is not necessary to rearrange programs
to avoid pipeline dependencies, although this is some-
times desirable for performance.
On-Chip Instruction and Data Caches
On-chip instruction and data caches satisfy most proces-
sor fetches without wait states. The caches are pipelined
for best performance. The reload policies minimize the
amount of time spent waiting for reload, while optimizing
the benefit of locality of reference.
Burst-Mode and Page-Mode Memories
The Am29240EH microcontroller series directly sup-
ports burst-mode memories. The burst-mode memory
supplies instructions at the maximum bandwidth, with-
out the complexity of an external cache or the perfor-
mance degradation due to cache misses.
The processor can also use the page-mode capability of
common DRAMs to improve the access time in cases
where page-mode accesses can be used.
Instruction Set Overview
All 29K family members employ a three-address instruc-
tion set architecture. The compiler or assembly-lan-
guage programmer is given complete freedom to
allocate register usage. There are 192 general-purpose
registers, allowing the retention of intermediate calcula-
tions and avoiding needless data destruction. Instruc-
tion operands may be contained in any of the
general-purpose registers, and the results may be
stored into any of the general-purpose registers.
The Am29240EH microcontroller series instruction set
contains 117 instructions that are divided into nine
classes. These classes are integer arithmetic, compare,
logical, shift, data movement, constant, floating point,
branch, and miscellaneous. The floating-point instruc-
tions are not executed directly , but are emulated by trap
handlers.
All directly implemented instructions are capable of
executing in one processor cycle, with the exception of
interrupt returns, loads, and stores.
Data Formats
The Am29240EH microcontroller series defines a word
as 32 bits of data, a half-word as 16 bits, and a byte as 8
bits. The hardware provides direct support for word-
integer (signed and unsigned), word-logical, word-Bool-
ean, half-word integer (signed and unsigned), and char-
acter data (signed and unsigned).
Word-Boolean data is based on the value contained in
the most significant bit of the word. The values TRUE
and FALSE are represented by the most significant bit
values 1 and 0, respectively.
Other data formats, such as character strings, are sup-
ported by instruction sequences. Floating-point formats
P R E L I M I N A R Y
10 Am29240 EH Microcontroller Series
(single and double precision) are defined for the proces-
sor; however, there is no direct hardware support for
these formats in the Am29240EH microcontroller series.
Protection
The Am29240EH microcontroller series offers two mutu-
ally exclusive modes of execution—the User and Super-
visor modes—that restrict or permit accesses to certain
processor registers and external storage locations.
The register file may be configured to restrict accesses
to Supervisor-mode programs on a bank-by-bank basis.
Memory Management Unit
The Am29240EH microcontroller series provides a
memory-management unit (MMU) for translating virtual
addresses into physical addresses. The page size for
translation ranges from 1 Kbyte to 16 Mbytes in powers
of 4. The Am29245EH and Am29240EH microcontrol-
lers each have a single, 16-entry TLB. The Am29243EH
microcontroller has dual 16-entry TLBs, each capable of
mapping pages of different size.
Interrupts and Traps
When the microcontroller takes an interrupt or trap, it
does not automatically save its current state information
in memory. This lightweight interrupt and trap facility
greatly improves the performance of temporary inter-
ruptions such as simple operating-system calls that re-
quire no saving of state information.
In cases where the processor state must be saved, the
saving and restoring of state information is under the con-
trol of software. The methods and data structures used to
handle interrupts—and the amount of state saved—may
be tailored to the needs of a particular system.
Interrupts and traps are dispatched through a 256-entry
vector table that directs the processor to a routine that
handles a given interrupt or trap. The vector table may
be relocated in memory by the modification of a proces-
sor register. There may be multiple vector tables in the
system, though only one is active at any given time.
The vector table is a table of pointers to the interrupt and
trap handlers, and requires only 1 Kbyte of memory. The
processor performs a vector fetch every time an inter-
rupt or trap is taken. The vector fetch requires at least
three cycles, in addition to the number of cycles required
for the basic memory access.
PIN DESCRIPTIONS
A23–A0
Address Bus (output, synchronous)
The Address Bus supplies the byte address for all ac-
cesses, except for DRAM accesses. For DRAM ac-
cesses, multiplexed row and column addresses are
provided on A14–A1. A2–A0 are also used to provide a
clock to an optional burst-mode EPROM.
BOOTW
Boot ROM Width (input, asynchronous)
This input configures the width of ROM Bank 0, so the
ROM can be accessed before the ROM configuration
has been set by the system initialization software. The
BOOTW signal is sampled during and after a processor
reset. If BOOTW is High before and after reset (tied
High), the boot ROM is 32 bits wide. If BOOTW is Low
before and after reset (tied Low), the boot ROM is 16 bits
wide. If BOOTW is Low before reset and High after reset
(tied to RESET), the boot ROM is 8 bits wide. This signal
has special hardening against metastable states, allow-
ing it to be driven with a slow-rise-time signal and permit-
ting it to be tied to RESET.
BURST
Burst-Mode Access (output, synchronous)
This signal is asserted to perform sequential accesses
from a burst-mode device.
CAS3–CAS0
Column Address Strobes, Byte 3–0
(output, synchronous)
A High-to-Low transition on these signals causes the
DRAM selected by RAS3–RAS0 to latch the column ad-
dress and complete the access. To support byte and
half-word writes, column address strobes are provided
for individual DRAM bytes. CAS3 is the column address
strobe for the DRAMs, in all banks, attached to
ID31–ID24. CAS2 is for the DRAMs attached to
ID23–ID16, and so on. These signals are also used in
other special DRAM cycles.
CNTL1–CNTL0
CPU Control
(input, asynchronous, internal pull-ups)
These inputs specify the processor mode: Load Test
Instruction, Step, Halt, or Normal.
DACKD–DACKA
DMA Acknowledge D through A
(output, synchronous)
These signals acknowledge an external transfer on a
DMA channel. DMA acknowledgments are not dedi-
cated to a particular DMA channel—each channel spec-
ifies which acknowledge line, if any , it is using. Only one
P R E L I M I N A R Y
11
Am29240 EH Microcontroller Series
channel at a time can use either DACKD, DACKC,
DACKB, or DACKA, and the same channel uses the re-
spective DREQD–DREQA signal for transfer requests.
DMA transfers can occur to and from internal peripher-
als independent of these acknowledgments. The
DACKD and DACKC signals are supported on the
Am29240EH and Am29243EH microcontrollers only.
DREQD–DREQA
DMA Request D through A
(input, asynchronous, pull-up resistors)
These inputs request an external transfer on a DMA
channel. DMA requests are not dedicated to a particular
channel—each channel specifies which request line, if
any , it is using. Only one channel at a time can use either
DREQD, DREQC, DREQB, or DREQA. This channel ac-
knowledges a transfer using the respective DACKD–
DACKA signal. These requests are individually program-
mable to be either level- or edge-sensitive for either po-
larity of level or edge. DMA transfers can occur to and
from internal peripherals independent of these requests.
The DMA request/acknowledge pairs DREQA/DACKA
and DREQB/DACKB correspond to the Am29200 micro-
controller signals DREQ0/DACK0 and DREQ1/DACK1,
respectively. The pin placement reflects this correspon-
dence, and a processor reset dedicates these request/
acknowledge pairs to DMA channels 0 and 1,
respectively. This permits backward-compatible up-
grade to an Am29200 microcontroller . The DREQD and
DREQC signals are supported on the Am29240EH and
Am29243EH microcontrollers only.
DSRA
Data Set Ready, Port A (output, synchronous)
This indicates to the host that the serial port is ready to
transmit or receive data on Serial Port A.
DTRA
Data Terminal Ready, Port A
(input, asynchronous)
This indicates to the processor that the host is ready to
transmit or receive data on Serial Port A.
GACK
External Memory Grant Acknowledge
(output, synchronous)
This signal indicates to an external device that it has
been granted an access to the processor’s ROM or
DRAM, and that the device should provide an address.
The processor can be placed into a slave configuration
that allows tracing of a master processor. In this configu-
ration, GACK is used to indicate that the processor pipe-
line was held during the previous processor cycle.
GREQ
External Memory Grant Request
(input, synchronous, pull-up resistor)
This signal is used by an external device to request an
access to the processor ’s ROM or DRAM. To perform
this access, the external device supplies an address to
the ROM controller or DRAM controller.
To support a hardware-development system, GREQ
should be either tied High or held at a high-impedance
state during a processor reset.
ID31–ID0
Instruction/Data Bus (bidirectional, synchronous)
The Instruction/Data Bus (ID Bus) transfers instructions
to, and data to and from the processor.
IDP3–IDP0
Instruction/Data Parity
(bidirectional, synchronous)
If parity checking is enabled by the PCE bit of the
DRAM Control Register, IDP3–IDP0 are parity bits for
the ID Bus during DRAM accesses. IDP3 is the parity
bit for ID31–ID24, IDP2 is the parity bit for ID23–ID16,
and so on. If parity is enabled, the processor drives
IDP3–IDP0 with valid parity during DRAM writes, and
expects IDP3–IDP0 to be driven with valid parity during
DRAM reads. These signals are supported on the
Am29243EH microcontroller only.
INCLK
Input Clock (input)
This is an oscillator input at twice the system operating
frequency.
INTR3–INTR0
Interrupt Requests 3–0
(input, asynchronous, internal pull-up resistors)
These inputs generate prioritized interrupt requests.
The interrupt caused by INTR0 has the highest priority,
and the interrupt caused by INTR3 has the lowest prior-
ity. The interrupt requests are masked in prioritized or-
der by the Interrupt Mask field in the Current Processor
Status Register and are disabled by the DA and DI bits of
the Current Processor Status Register. These signals
have special hardening against metastable states, al-
lowing them to be driven with slow-transition-time
signals.
LSYNC
Line Synchronization (input, asynchronous)
This signal indicates the start of a raster line. This signal
is supported on the Am29240EH and Am29245EH mi-
crocontrollers only.
P R E L I M I N A R Y
12 Am29240 EH Microcontroller Series
MEMCLK
Memory Clock (output)
MEMCLK is an output clock only. It operates at the sys-
tem operating frequency , which is half of the INCLK fre-
quency. Most processor inputs and outputs are
synchronous to MEMCLK. Note that MEMCLK as an in-
put is not supported on the Am29240EH microcontroller
series.
MEMDRV
MEMCLK Drive Enable
(input, internal pull-up resistor)
The MEMDRV signal is reserved on the Am29240EH
microcontroller series. This pin should be either tied
High or left unconnected.
PACK
Parallel Port Acknowledge (output, synchronous)
This signal is used by the processor to acknowledge a
transfer from the host or to indicate to the host that data
has been placed on the port.
PAUTOFD
Parallel Port Autofeed (input, asynchronous)
This signal is used by the host to indicate how line feeds
should be performed or is used to indicate that the host
is busy and cannot accept a data transfer.
PBUSY
Parallel Port Busy (output, synchronous)
This indicates to the host that the Parallel Port is busy
and cannot accept a data transfer.
PIACS5–PIACS0
Peripheral Chip Selects, Regions 5–0
(output, synchronous)
These signals are used to select individual peripheral
devices. DMA channels may be programmed to use
dedicated chip selects during an external peripheral
access.
PIAOE
Peripheral Output Enable (output, synchronous)
This signal enables the selected peripheral device to
drive the ID bus.
PIAWE
Peripheral Write Enable (output, synchronous)
This signal causes data on the ID bus to be written into
the selected peripheral.
PIO15–PIO0
Programmable Input/Output
(input/output, asynchronous)
These signals are available for direct software control
and inspection. PIO15–PIO8 may be individually pro-
grammed to cause processor interrupts. These signals
have special hardening against metastable states, al-
lowing them to be driven with slow-transition-time
signals.
The PIO signals are sampled during a processor reset.
After reset, the sampled value is held in the PIO Input
Register. This sampled value is supplied the first time
this register is read, unless the read is preceded by write
to the PIO Input Register or by a read or write of any oth-
er PIO register. This may be used to indicate system
configuration information to the processor during a
reset.
POE
Parallel Port Output Enable (output, synchronous)
This signal enables an external data buffer containing
data from the host to drive the ID Bus.
PSTROBE
Parallel Port Strobe (input, asynchronous)
This signal is used by the host to indicate that data is on
the Parallel Port or to acknowledge a transfer from the
processor.
PSYNC
Page Synchronization (input/output, asynchronous)
This signal indicates the beginning of a raster page. This
signal is supported on the Am29240EH and
Am29245EH microcontrollers only.
PWE
Parallel Port Write Enable (output, synchronous)
This signal writes a buffer with data on the ID Bus. Then,
the buffer drives data to the host.
R/W
Read/Write (output, synchronous)
During an external ROM, DRAM, DMA, or PIA access,
this signal indicates the direction of transfer: High for a
read and Low for a write.
RAS3–RAS0
Row Address Strobe, Banks 3–0
(output, synchronous)
A High-to-Low transition on one of these signals causes
a DRAM in the corresponding bank to latch the row ad-
dress and begin an access. RAS3 starts an access in
DRAM Bank 3, and so on. These signals also are used in
other special DRAM cycles.
P R E L I M I N A R Y
13
Am29240 EH Microcontroller Series
RESET
Reset (input, asynchronous)
This input places the processor in the Reset mode. This
signal has special hardening against metastable states,
allowing it to be driven with a slow-rise-time signal.
ROMCS3–ROMCS0
ROM Chip Selects, Banks 3–0 (output, synchronous)
A Low level on one of these signals selects the memory
devices in the corresponding ROM bank. ROMCS3 se-
lects devices in ROM Bank 3, etc. The timing and access
parameters of each bank are individually programmable.
ROMOE
ROM Output Enable (output, synchronous)
This signal enables the selected ROM Bank to drive the
ID bus. It is used to prevent bus contention when switch-
ing between different ROM banks or switching between
a ROM bank and another device or DRAM bank.
RSWE
ROM Space Write Enable (output, synchronous)
This signal is used to write an alterable memory in a
ROM bank (such as an SRAM or Flash EPROM).
RXDA
Receive Data, Port A (input, asynchronous)
This input is used to receive serial data to Serial Port A.
RXDB
Receive Data, Port B (input, asynchronous)
This input is used to receive data to Serial Port B. This
signal is supported on the Am29240EH and
Am29243EH microcontrollers only.
STAT2–STAT0
CPU Status (output, synchronous)
These outputs indicate information about the processor
or the current access for the purposes of hardware
debug.
TCK
Test Clock Input
(input, asynchronous, pull-up resistor)
This input is used to operate the Test Access Port. The
state of the Test Access Port must be held if this clock is
held either High or Low . This clock is internally synchro-
nized to MEMCLK for certain operations of the Test Ac-
cess Port controller, so signals internally driven and
sampled by the Test Access Port are synchronous to
processor internal clocks.
TDI
Test Data Input
(input, synchronous to TCK, pull-up resistor)
This input supplies data to the test logic from an external
source. It is sampled on the rising edge of TCK. If it is not
driven, it appears High internally.
TDMA
Terminate DMA (input/output, synchronous)
This signal is either an input or an output as controlled by
the corresponding DMA Control Register. As an input,
this signal can be asserted during an external DMA
transfer (non-fly-by) to terminate the transfer after the
current access. The TDMA input is ignored during fly-by
transfers. As an output, this signal is asserted to indicate
the final transfer of a sequence.
TDO
Test Data Output
(three-state output, synchronous to TCK)
This output supplies data from the test logic to an exter-
nal destination. It changes on the falling edge of TCK. It
is in the high-impedance state except when scanning is
in progress.
TMS
Test Mode Select
(input, synchronous to TCK, pull-up resistor)
This input is used to control the Test Access Port. If it is
not driven, it appears High internally.
TR/OE
Video DRAM Transfer/Output Enable
(output, synchronous)
This signal is used with video DRAMs to transfer data to
the video shift register. It is also used as an output en-
able in normal video DRAM read cycles. This signal is
supported on the Am29240EH and Am29245EH micro-
controllers only.
TRAP1–TRAP0
Trap Requests 1–0
(input, asynchronous, internal pull-ups)
These inputs generate prioritized trap requests. The
trap caused by TRAP0 has the highest priority. These
trap requests are disabled by the DA bit of the Current
Processor Status Register. These signals have special
hardening against metastable states, allowing them to
be driven with slow-transition-time signals.
P R E L I M I N A R Y
14 Am29240 EH Microcontroller Series
TRIST
Three-State Control
(input, asynchronous, pull-up resistor)
This input is asserted to force all processor outputs into
the high-impedance state. This signal is tied High
through an internal pull-up resistor.
TRST
Test Reset Input
(input, asynchronous, pull-up resistor)
This input asynchronously resets the Test Access Port.
If TRST is not driven, it appears High internally. TRST
must be tied to RESET, even if the Test Access Port is
not being used.
TXDA
Transmit Data, Port A (output, asynchronous)
This output is used to transmit serial data from Serial
Port A.
TXDB
Transmit Data, Port B (output, asynchronous)
This output is used to transmit data from Serial Port B.
This signal is supported on the Am29240EH and
Am29243EH microcontrollers only.
UCLK
UART Clock (input)
This is an oscillator input for generating the UART (Seri-
al Port) clock. T o generate the UART clock, the oscillator
frequency may be divided by any amount up to 65,536.
The UART clock operates at 16 times the Serial Port’s
baud rate. As an option, UCLK may be driven with
MEMCLK or INCLK. It can be driven with TTL levels.
VCLK
Video Clock (input, asynchronous)
This clock is used to synchronize the transfer of video
data. As an option, VCLK may be driven with MEMCLK
or INCLK. It can be driven with TTL levels. This signal is
supported on the Am29240EH and Am29245EH mi-
crocontrollers only.
VDAT
Video Data (input/output, synchronous to VCLK)
This is serial data to or from the video device. This signal
is supported on the Am29240EH and Am29245EH mi-
crocontrollers only.
WAIT
Add Wait States
(input, synchronous, internal pull-up)
External accesses are normally timed by the processor.
However, the WAIT signal may be asserted during a PIA,
ROM, or DMA access to extend the access indefinitely.
For external DMA accesses, the number of wait states
taken by the DRAM controller (this includes peripheral
read and write wait states during DMA transfers) is deter-
mined by the actual value in the DMAWAIT field of the
DMA Control Register or the number of wait states speci-
fied by the IOWAIT field in the PIA Control Register,
whichever is greater.
WARN
Warn (input, asynchronous, edge-sensitive,
internal pull-up)
A High-to-Low transition on this input causes a non-
maskable WARN trap to occur. This trap bypasses the
normal trap vector fetch sequence, and is useful in situa-
tions where the vector fetch may not work (e.g., when
data memory is faulty). This signal has special harden-
ing against metastable states, allowing it to be driven
with a slow-transition-time signal. WARN must be held
active for at least four system clocks for the processor to
recognize it.
WE
Write Enable (output, synchronous)
This signal is used to write the selected DRAM bank.
“Early write” cycles are used so the DRAM data inputs
and outputs can be tied to the common ID Bus.
PRODUCT ENHANCEMENTS
Programmable DRAM Timing
Through Bit 24 in the DRAM Control Register, the DRAM
controller now supports programmable DRAM timing,
for either two- or three-cycle simple accesses, with
single-cycle page-mode accesses. The new bit defined
below.
Bit 24: Programmable DRAM Timing (PDT)—A 1 in
this bit sets the DRAM timing to 2/1, for two-cycle simple
accesses and single-cycle page-mode accesses. A 0 in
this bit sets the DRAM timing to 3/1, for three-cycle sim-
ple accesses and single-cycle page-mode accesses.
FEATURES NO LONGER SUPPORTED
The following features are no longer supported on the
Am29240EH, Am29245EH, and Am29243EH micro-
controllers:
33 MHz operating frequency
Scalable Clocking technology (also known as
turbo mode or clock doubling)
16-bit DRAM memory
MEMDRV signal
MEMCLK as an input
P R E L I M I N A R Y
15
Am29240 EH Microcontroller Series
CONNECTION DIAGRAM
208-Pin PQFP
Top Side View
31
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
Am29240EH Microcontroller Series
Note:
Pin 1 is marked for orientation.
P R E L I M I N A R Y
16 Am29240 EH Microcontroller Series
PQFP PIN DESIGNATIONS (Pin Number)
ÁÁÁÁ
ÁÁÁÁ
Pin No.
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Pin Name
ÁÁÁÁÁ
ÁÁÁÁÁ
Pin No.
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Pin Name
ÁÁÁÁ
ÁÁÁÁ
Pin No.
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Pin Name
ÁÁÁÁ
ÁÁÁÁ
Pin No.
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Pin Name
ÁÁÁÁ
ÁÁÁÁ
1
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁÁ
ÁÁÁÁÁ
53
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
ÁÁÁÁ
105
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
ÁÁÁÁ
157
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
ÁÁÁÁ
2
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
MEMCLK
ÁÁÁÁÁ
ÁÁÁÁÁ
54
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCC
ÁÁÁÁ
ÁÁÁÁ
106
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCC
ÁÁÁÁ
ÁÁÁÁ
158
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCC
ÁÁÁÁ
ÁÁÁÁ
3
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
MEMDRV
ÁÁÁÁÁ
ÁÁÁÁÁ
55
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
107
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
159
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
4
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
INCLK
ÁÁÁÁÁ
ÁÁÁÁÁ
56
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
ÁÁÁÁ
108
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
ÁÁÁÁ
160
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO12
ÁÁÁÁ
ÁÁÁÁ
5
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
57
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
TXDB 3
ÁÁÁÁ
ÁÁÁÁ
109
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
A23
ÁÁÁÁ
ÁÁÁÁ
161
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO11
ÁÁÁÁ
ÁÁÁÁ
6
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁÁ
ÁÁÁÁÁ
58
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
RXDB 3
ÁÁÁÁ
ÁÁÁÁ
110
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
A22
ÁÁÁÁ
ÁÁÁÁ
162
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO10
ÁÁÁÁ
ÁÁÁÁ
7
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID31
ÁÁÁÁÁ
ÁÁÁÁÁ
59
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
DTRA
ÁÁÁÁ
ÁÁÁÁ
111
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
A21
ÁÁÁÁ
ÁÁÁÁ
163
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO9
ÁÁÁÁ
ÁÁÁÁ
8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID30
ÁÁÁÁÁ
ÁÁÁÁÁ
60
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
RXDA
ÁÁÁÁ
ÁÁÁÁ
112
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
A20
ÁÁÁÁ
ÁÁÁÁ
164
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO8
ÁÁÁÁ
ÁÁÁÁ
9
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID29
ÁÁÁÁÁ
ÁÁÁÁÁ
61
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
UCLK
ÁÁÁÁ
ÁÁÁÁ
113
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
A19
ÁÁÁÁ
ÁÁÁÁ
165
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO7
ÁÁÁÁ
10
ÁÁÁÁÁÁ
ID28
ÁÁÁÁÁ
62
ÁÁÁÁÁÁ
DSRA
ÁÁÁÁ
114
ÁÁÁÁÁÁ
A18
ÁÁÁÁ
166
ÁÁÁÁÁÁ
PIO6
ÁÁÁÁ
ÁÁÁÁ
11
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID27
ÁÁÁÁÁ
ÁÁÁÁÁ
63
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
TXDA
ÁÁÁÁ
ÁÁÁÁ
115
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
A17
ÁÁÁÁ
ÁÁÁÁ
167
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO5
ÁÁÁÁ
ÁÁÁÁ
12
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID26
ÁÁÁÁÁ
ÁÁÁÁÁ
64
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ROMCS3
ÁÁÁÁ
ÁÁÁÁ
116
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
A16
ÁÁÁÁ
ÁÁÁÁ
168
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO4
ÁÁÁÁ
ÁÁÁÁ
13
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID25
ÁÁÁÁÁ
ÁÁÁÁÁ
65
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ROMCS2
ÁÁÁÁ
ÁÁÁÁ
117
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
169
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
14
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID24
ÁÁÁÁÁ
ÁÁÁÁÁ
66
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ROMCS1
ÁÁÁÁ
ÁÁÁÁ
118
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCC
ÁÁÁÁ
ÁÁÁÁ
170
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCC
ÁÁÁÁ
ÁÁÁÁ
15
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁÁ
ÁÁÁÁÁ
67
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ROMCS0
ÁÁÁÁ
ÁÁÁÁ
119
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
A15
ÁÁÁÁ
ÁÁÁÁ
171
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO3
ÁÁÁÁ
ÁÁÁÁ
16
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
68
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCC
ÁÁÁÁ
ÁÁÁÁ
120
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
A14
ÁÁÁÁ
ÁÁÁÁ
172
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO2
ÁÁÁÁ
ÁÁÁÁ
17
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID23
ÁÁÁÁÁ
ÁÁÁÁÁ
69
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
121
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
A13
ÁÁÁÁ
ÁÁÁÁ
173
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO1
ÁÁÁÁ
ÁÁÁÁ
18
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID22
ÁÁÁÁÁ
ÁÁÁÁÁ
70
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
BURST
ÁÁÁÁ
ÁÁÁÁ
122
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
A12
ÁÁÁÁ
ÁÁÁÁ
174
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO0
ÁÁÁÁ
ÁÁÁÁ
19
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID21
ÁÁÁÁÁ
ÁÁÁÁÁ
71
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
RSWE
ÁÁÁÁ
ÁÁÁÁ
123
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
A11
ÁÁÁÁ
ÁÁÁÁ
175
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
TDO
ÁÁÁÁ
ÁÁÁÁ
20
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID20
ÁÁÁÁÁ
ÁÁÁÁÁ
72
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ROMOE
ÁÁÁÁ
ÁÁÁÁ
124
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
A10
ÁÁÁÁ
ÁÁÁÁ
176
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
STAT2
ÁÁÁÁ
21
ÁÁÁÁÁÁ
ID19
ÁÁÁÁÁ
73
ÁÁÁÁÁÁ
RAS3
ÁÁÁÁ
125
ÁÁÁÁÁÁ
A9
ÁÁÁÁ
177
ÁÁÁÁÁÁ
STAT1
ÁÁÁÁ
ÁÁÁÁ
22
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID18
ÁÁÁÁÁ
ÁÁÁÁÁ
74
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
RAS2
ÁÁÁÁ
ÁÁÁÁ
126
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
A8
ÁÁÁÁ
ÁÁÁÁ
178
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
STAT0
ÁÁÁÁ
ÁÁÁÁ
23
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID17
ÁÁÁÁÁ
ÁÁÁÁÁ
75
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
RAS1
ÁÁÁÁ
ÁÁÁÁ
127
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
179
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VDAT 2
ÁÁÁÁ
ÁÁÁÁ
24
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID16
ÁÁÁÁÁ
ÁÁÁÁÁ
76
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
RAS0
ÁÁÁÁ
ÁÁÁÁ
128
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCC
ÁÁÁÁ
ÁÁÁÁ
180
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PSYNC 2
ÁÁÁÁ
ÁÁÁÁ
25
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁÁ
ÁÁÁÁÁ
77
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
CAS3
ÁÁÁÁ
ÁÁÁÁ
129
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
A7
ÁÁÁÁ
ÁÁÁÁ
181
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
26
ÁÁÁÁÁÁ
VCC
ÁÁÁÁÁ
78
ÁÁÁÁÁÁ
CAS2
ÁÁÁÁ
130
ÁÁÁÁÁÁ
A6
ÁÁÁÁ
182
ÁÁÁÁÁÁ
VCC
ÁÁÁÁ
ÁÁÁÁ
27
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID15
ÁÁÁÁÁ
ÁÁÁÁÁ
79
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCC
ÁÁÁÁ
ÁÁÁÁ
131
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
A5
ÁÁÁÁ
ÁÁÁÁ
183
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GREQ
ÁÁÁÁ
ÁÁÁÁ
28
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID14
ÁÁÁÁÁ
ÁÁÁÁÁ
80
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
132
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
A4
ÁÁÁÁ
ÁÁÁÁ
184
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
DREQB
ÁÁÁÁ
ÁÁÁÁ
29
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID13
ÁÁÁÁÁ
ÁÁÁÁÁ
81
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
CAS1
ÁÁÁÁ
ÁÁÁÁ
133
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
A3
ÁÁÁÁ
ÁÁÁÁ
185
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
DREQA
ÁÁÁÁ
ÁÁÁÁ
30
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID12
ÁÁÁÁÁ
ÁÁÁÁÁ
82
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
CAS0
ÁÁÁÁ
ÁÁÁÁ
134
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
A2
ÁÁÁÁ
ÁÁÁÁ
186
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
TDMA
ÁÁÁÁ
ÁÁÁÁ
31
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID11
ÁÁÁÁÁ
ÁÁÁÁÁ
83
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
TR/OE
ÁÁÁÁ
ÁÁÁÁ
135
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
A1
ÁÁÁÁ
ÁÁÁÁ
187
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
TRAP0
ÁÁÁÁ
32
ÁÁÁÁÁÁ
ID10
ÁÁÁÁÁ
84
ÁÁÁÁÁÁ
WE
ÁÁÁÁ
136
ÁÁÁÁÁÁ
A0
ÁÁÁÁ
188
ÁÁÁÁÁÁ
TRAP1
ÁÁÁÁ
ÁÁÁÁ
33
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID9
ÁÁÁÁÁ
ÁÁÁÁÁ
85
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GACK
ÁÁÁÁ
ÁÁÁÁ
137
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
189
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
INTR0
ÁÁÁÁ
ÁÁÁÁ
34
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID8
ÁÁÁÁÁ
ÁÁÁÁÁ
86
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIACS5
ÁÁÁÁ
ÁÁÁÁ
138
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCC
ÁÁÁÁ
ÁÁÁÁ
190
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
INTR1
ÁÁÁÁ
ÁÁÁÁ
35
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁÁ
ÁÁÁÁÁ
87
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIACS4
ÁÁÁÁ
ÁÁÁÁ
139
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
BOOTW
ÁÁÁÁ
ÁÁÁÁ
191
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
INTR2
ÁÁÁÁ
ÁÁÁÁ
36
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
88
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIACS3
ÁÁÁÁ
ÁÁÁÁ
140
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
WAIT
ÁÁÁÁ
ÁÁÁÁ
192
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
INTR3
ÁÁÁÁ
37
ÁÁÁÁÁÁ
ID7
ÁÁÁÁÁ
89
ÁÁÁÁÁÁ
PIACS2
ÁÁÁÁ
141
ÁÁÁÁÁÁ
PAUTOFD
ÁÁÁÁ
193
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
38
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID6
ÁÁÁÁÁ
ÁÁÁÁÁ
90
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCC
ÁÁÁÁ
ÁÁÁÁ
142
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PSTROBE
ÁÁÁÁ
ÁÁÁÁ
194
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCC
ÁÁÁÁ
ÁÁÁÁ
39
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID5
ÁÁÁÁÁ
ÁÁÁÁÁ
91
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
143
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PWE
ÁÁÁÁ
ÁÁÁÁ
195
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
WARN
ÁÁÁÁ
ÁÁÁÁ
40
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID4
ÁÁÁÁÁ
ÁÁÁÁÁ
92
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIACS1
ÁÁÁÁ
ÁÁÁÁ
144
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
POE
ÁÁÁÁ
ÁÁÁÁ
196
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCLK 2
ÁÁÁÁ
ÁÁÁÁ
41
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID3
ÁÁÁÁÁ
ÁÁÁÁÁ
93
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIACS0
ÁÁÁÁ
ÁÁÁÁ
145
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PACK
ÁÁÁÁ
ÁÁÁÁ
197
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
LSYNC 2
ÁÁÁÁ
ÁÁÁÁ
42
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID2
ÁÁÁÁÁ
ÁÁÁÁÁ
94
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIAWE
ÁÁÁÁ
ÁÁÁÁ
146
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PBUSY
ÁÁÁÁ
ÁÁÁÁ
198
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
TMS
ÁÁÁÁ
43
ÁÁÁÁÁÁ
ID1
ÁÁÁÁÁ
95
ÁÁÁÁÁÁ
PIAOE
ÁÁÁÁ
147
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
199
ÁÁÁÁÁÁ
TRST
ÁÁÁÁ
ÁÁÁÁ
44
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID0
ÁÁÁÁÁ
ÁÁÁÁÁ
96
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
R/W
ÁÁÁÁ
ÁÁÁÁ
148
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCC
ÁÁÁÁ
ÁÁÁÁ
200
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
TCK
ÁÁÁÁ
ÁÁÁÁ
45
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁÁ
ÁÁÁÁÁ
97
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
DACKB
ÁÁÁÁ
ÁÁÁÁ
149
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO15
ÁÁÁÁ
ÁÁÁÁ
201
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
TDI
ÁÁÁÁ
ÁÁÁÁ
46
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
98
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
DACKA
ÁÁÁÁ
ÁÁÁÁ
150
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO14
ÁÁÁÁ
ÁÁÁÁ
202
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
RESET
ÁÁÁÁ
ÁÁÁÁ
47
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
IDP3 1, 3
ÁÁÁÁÁ
ÁÁÁÁÁ
99
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
DACKD 3
ÁÁÁÁ
ÁÁÁÁ
151
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO13
ÁÁÁÁ
ÁÁÁÁ
203
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
CNTL1
ÁÁÁÁ
48
ÁÁÁÁÁÁ
IDP2 1, 3
ÁÁÁÁÁ
100
ÁÁÁÁÁÁ
DACKC 3
ÁÁÁÁ
152
ÁÁÁÁÁÁ
DREQD 3
ÁÁÁÁ
204
ÁÁÁÁÁÁ
CNTL0
ÁÁÁÁ
ÁÁÁÁ
49
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
IDP1 1, 3
ÁÁÁÁÁ
ÁÁÁÁÁ
101
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCC
ÁÁÁÁ
ÁÁÁÁ
153
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
DREQC 3
ÁÁÁÁ
ÁÁÁÁ
205
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
TRIST
ÁÁÁÁ
ÁÁÁÁ
50
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
IDP0 1, 3
ÁÁÁÁÁ
ÁÁÁÁÁ
102
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
154
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
206
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCC
ÁÁÁÁ
ÁÁÁÁ
51
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁÁ
ÁÁÁÁÁ
103
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
ÁÁÁÁ
155
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
VCC
ÁÁÁÁ
ÁÁÁÁ
207
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
52
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁÁ
ÁÁÁÁÁ
104
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
ÁÁÁÁ
156
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
ÁÁÁÁ
208
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
Notes:
1. Defined as no-connect on Am29240EH microcontroller. 2. Defined as no-connect on Am29243EH microcontroller .
3. Defined as no-connect on Am29245EH microcontroller.
P R E L I M I N A R Y
17
Am29240 EH Microcontroller Series
PQFP PIN DESIGNATIONS (Pin Name)
ÁÁÁÁÁ
ÁÁÁÁÁ
Pin Name
ÁÁÁÁÁ
ÁÁÁÁÁ
Pin No.
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Pin Name
ÁÁÁÁ
ÁÁÁÁ
Pin No.
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Pin Name
ÁÁÁÁÁ
ÁÁÁÁÁ
Pin No.
ÁÁÁÁÁ
ÁÁÁÁÁ
Pin Name
ÁÁÁÁÁ
ÁÁÁÁÁ
Pin No.
ÁÁÁÁÁ
ÁÁÁÁÁ
A0
ÁÁÁÁÁ
ÁÁÁÁÁ
136
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
91
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
INTR0
ÁÁÁÁÁ
ÁÁÁÁÁ
189
ÁÁÁÁÁ
ÁÁÁÁÁ
RESET
ÁÁÁÁÁ
ÁÁÁÁÁ
202
ÁÁÁÁÁ
ÁÁÁÁÁ
A1
ÁÁÁÁÁ
ÁÁÁÁÁ
135
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
102
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
INTR1
ÁÁÁÁÁ
ÁÁÁÁÁ
190
ÁÁÁÁÁ
ÁÁÁÁÁ
ROMCS0
ÁÁÁÁÁ
ÁÁÁÁÁ
67
ÁÁÁÁÁ
ÁÁÁÁÁ
A2
ÁÁÁÁÁ
ÁÁÁÁÁ
134
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
107
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
INTR2
ÁÁÁÁÁ
ÁÁÁÁÁ
191
ÁÁÁÁÁ
ÁÁÁÁÁ
ROMCS1
ÁÁÁÁÁ
ÁÁÁÁÁ
66
ÁÁÁÁÁ
ÁÁÁÁÁ
A3
ÁÁÁÁÁ
ÁÁÁÁÁ
133
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
117
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
INTR3
ÁÁÁÁÁ
ÁÁÁÁÁ
192
ÁÁÁÁÁ
ÁÁÁÁÁ
ROMCS2
ÁÁÁÁÁ
ÁÁÁÁÁ
65
ÁÁÁÁÁ
ÁÁÁÁÁ
A4
ÁÁÁÁÁ
ÁÁÁÁÁ
132
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
127
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
LSYNC 2
ÁÁÁÁÁ
ÁÁÁÁÁ
197
ÁÁÁÁÁ
ÁÁÁÁÁ
ROMCS3
ÁÁÁÁÁ
ÁÁÁÁÁ
64
ÁÁÁÁÁ
ÁÁÁÁÁ
A5
ÁÁÁÁÁ
ÁÁÁÁÁ
131
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
137
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
MEMCLK
ÁÁÁÁÁ
ÁÁÁÁÁ
2
ÁÁÁÁÁ
ÁÁÁÁÁ
ROMOE
ÁÁÁÁÁ
ÁÁÁÁÁ
72
ÁÁÁÁÁ
ÁÁÁÁÁ
A6
ÁÁÁÁÁ
ÁÁÁÁÁ
130
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
147
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
MEMDRV
ÁÁÁÁÁ
ÁÁÁÁÁ
3
ÁÁÁÁÁ
ÁÁÁÁÁ
RSWE
ÁÁÁÁÁ
ÁÁÁÁÁ
71
ÁÁÁÁÁ
ÁÁÁÁÁ
A7
ÁÁÁÁÁ
ÁÁÁÁÁ
129
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
154
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PACK
ÁÁÁÁÁ
ÁÁÁÁÁ
145
ÁÁÁÁÁ
ÁÁÁÁÁ
RXDA
ÁÁÁÁÁ
ÁÁÁÁÁ
60
ÁÁÁÁÁ
ÁÁÁÁÁ
A8
ÁÁÁÁÁ
ÁÁÁÁÁ
126
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
159
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PAUTOFD
ÁÁÁÁÁ
ÁÁÁÁÁ
141
ÁÁÁÁÁ
ÁÁÁÁÁ
RXDB 3
ÁÁÁÁÁ
ÁÁÁÁÁ
58
ÁÁÁÁÁ
A9
ÁÁÁÁÁ
125
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
169
ÁÁÁÁÁÁ
PBUSY
ÁÁÁÁÁ
146
ÁÁÁÁÁ
STAT0
ÁÁÁÁÁ
178
ÁÁÁÁÁ
ÁÁÁÁÁ
A10
ÁÁÁÁÁ
ÁÁÁÁÁ
124
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
181
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIACS0
ÁÁÁÁÁ
ÁÁÁÁÁ
93
ÁÁÁÁÁ
ÁÁÁÁÁ
STAT1
ÁÁÁÁÁ
ÁÁÁÁÁ
177
ÁÁÁÁÁ
ÁÁÁÁÁ
A11
ÁÁÁÁÁ
ÁÁÁÁÁ
123
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
193
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIACS1
ÁÁÁÁÁ
ÁÁÁÁÁ
92
ÁÁÁÁÁ
ÁÁÁÁÁ
STAT2
ÁÁÁÁÁ
ÁÁÁÁÁ
176
ÁÁÁÁÁ
ÁÁÁÁÁ
A12
ÁÁÁÁÁ
ÁÁÁÁÁ
122
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
207
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIACS2
ÁÁÁÁÁ
ÁÁÁÁÁ
89
ÁÁÁÁÁ
ÁÁÁÁÁ
TCK
ÁÁÁÁÁ
ÁÁÁÁÁ
200
ÁÁÁÁÁ
ÁÁÁÁÁ
A13
ÁÁÁÁÁ
ÁÁÁÁÁ
121
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁ
ÁÁÁÁ
208
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIACS3
ÁÁÁÁÁ
ÁÁÁÁÁ
88
ÁÁÁÁÁ
ÁÁÁÁÁ
TDI
ÁÁÁÁÁ
ÁÁÁÁÁ
201
ÁÁÁÁÁ
ÁÁÁÁÁ
A14
ÁÁÁÁÁ
ÁÁÁÁÁ
120
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
GREQ
ÁÁÁÁ
ÁÁÁÁ
183
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIACS4
ÁÁÁÁÁ
ÁÁÁÁÁ
87
ÁÁÁÁÁ
ÁÁÁÁÁ
TDMA
ÁÁÁÁÁ
ÁÁÁÁÁ
186
ÁÁÁÁÁ
A15
ÁÁÁÁÁ
119
ÁÁÁÁÁÁ
ID0
ÁÁÁÁ
44
ÁÁÁÁÁÁ
PIACS5
ÁÁÁÁÁ
86
ÁÁÁÁÁ
TDO
ÁÁÁÁÁ
175
ÁÁÁÁÁ
ÁÁÁÁÁ
A16
ÁÁÁÁÁ
ÁÁÁÁÁ
116
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID1
ÁÁÁÁ
ÁÁÁÁ
43
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIAOE
ÁÁÁÁÁ
ÁÁÁÁÁ
95
ÁÁÁÁÁ
ÁÁÁÁÁ
TMS
ÁÁÁÁÁ
ÁÁÁÁÁ
198
ÁÁÁÁÁ
ÁÁÁÁÁ
A17
ÁÁÁÁÁ
ÁÁÁÁÁ
115
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID2
ÁÁÁÁ
ÁÁÁÁ
42
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIAWE
ÁÁÁÁÁ
ÁÁÁÁÁ
94
ÁÁÁÁÁ
ÁÁÁÁÁ
TR/OE
ÁÁÁÁÁ
ÁÁÁÁÁ
83
ÁÁÁÁÁ
ÁÁÁÁÁ
A18
ÁÁÁÁÁ
ÁÁÁÁÁ
114
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID3
ÁÁÁÁ
ÁÁÁÁ
41
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO0
ÁÁÁÁÁ
ÁÁÁÁÁ
174
ÁÁÁÁÁ
ÁÁÁÁÁ
TRAP0
ÁÁÁÁÁ
ÁÁÁÁÁ
187
ÁÁÁÁÁ
ÁÁÁÁÁ
A19
ÁÁÁÁÁ
ÁÁÁÁÁ
113
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID4
ÁÁÁÁ
ÁÁÁÁ
40
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO1
ÁÁÁÁÁ
ÁÁÁÁÁ
173
ÁÁÁÁÁ
ÁÁÁÁÁ
TRAP1
ÁÁÁÁÁ
ÁÁÁÁÁ
188
ÁÁÁÁÁ
ÁÁÁÁÁ
A20
ÁÁÁÁÁ
ÁÁÁÁÁ
112
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID5
ÁÁÁÁ
ÁÁÁÁ
39
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO2
ÁÁÁÁÁ
ÁÁÁÁÁ
172
ÁÁÁÁÁ
ÁÁÁÁÁ
TRIST
ÁÁÁÁÁ
ÁÁÁÁÁ
205
ÁÁÁÁÁ
ÁÁÁÁÁ
A21
ÁÁÁÁÁ
ÁÁÁÁÁ
111
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID6
ÁÁÁÁ
ÁÁÁÁ
38
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO3
ÁÁÁÁÁ
ÁÁÁÁÁ
171
ÁÁÁÁÁ
ÁÁÁÁÁ
TRST
ÁÁÁÁÁ
ÁÁÁÁÁ
199
ÁÁÁÁÁ
ÁÁÁÁÁ
A22
ÁÁÁÁÁ
ÁÁÁÁÁ
110
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID7
ÁÁÁÁ
ÁÁÁÁ
37
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO4
ÁÁÁÁÁ
ÁÁÁÁÁ
168
ÁÁÁÁÁ
ÁÁÁÁÁ
TXDA
ÁÁÁÁÁ
ÁÁÁÁÁ
63
ÁÁÁÁÁ
ÁÁÁÁÁ
A23
ÁÁÁÁÁ
ÁÁÁÁÁ
109
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID8
ÁÁÁÁ
ÁÁÁÁ
34
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO5
ÁÁÁÁÁ
ÁÁÁÁÁ
167
ÁÁÁÁÁ
ÁÁÁÁÁ
TXDB 3
ÁÁÁÁÁ
ÁÁÁÁÁ
57
ÁÁÁÁÁ
ÁÁÁÁÁ
BOOTW
ÁÁÁÁÁ
ÁÁÁÁÁ
139
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID9
ÁÁÁÁ
ÁÁÁÁ
33
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO6
ÁÁÁÁÁ
ÁÁÁÁÁ
166
ÁÁÁÁÁ
ÁÁÁÁÁ
UCLK
ÁÁÁÁÁ
ÁÁÁÁÁ
61
ÁÁÁÁÁ
ÁÁÁÁÁ
BURST
ÁÁÁÁÁ
ÁÁÁÁÁ
70
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID10
ÁÁÁÁ
ÁÁÁÁ
32
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO7
ÁÁÁÁÁ
ÁÁÁÁÁ
165
ÁÁÁÁÁ
ÁÁÁÁÁ
Reserved
ÁÁÁÁÁ
ÁÁÁÁÁ
1
ÁÁÁÁÁ
ÁÁÁÁÁ
CAS0
ÁÁÁÁÁ
ÁÁÁÁÁ
82
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID11
ÁÁÁÁ
ÁÁÁÁ
31
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO8
ÁÁÁÁÁ
ÁÁÁÁÁ
164
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
5
ÁÁÁÁÁ
ÁÁÁÁÁ
CAS1
ÁÁÁÁÁ
ÁÁÁÁÁ
81
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID12
ÁÁÁÁ
ÁÁÁÁ
30
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO9
ÁÁÁÁÁ
ÁÁÁÁÁ
163
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
16
ÁÁÁÁÁ
ÁÁÁÁÁ
CAS2
ÁÁÁÁÁ
ÁÁÁÁÁ
78
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID13
ÁÁÁÁ
ÁÁÁÁ
29
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO10
ÁÁÁÁÁ
ÁÁÁÁÁ
162
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
26
ÁÁÁÁÁ
ÁÁÁÁÁ
CAS3
ÁÁÁÁÁ
ÁÁÁÁÁ
77
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID14
ÁÁÁÁ
ÁÁÁÁ
28
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO11
ÁÁÁÁÁ
ÁÁÁÁÁ
161
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
36
ÁÁÁÁÁ
ÁÁÁÁÁ
CNTL0
ÁÁÁÁÁ
ÁÁÁÁÁ
204
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID15
ÁÁÁÁ
ÁÁÁÁ
27
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO12
ÁÁÁÁÁ
ÁÁÁÁÁ
160
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
46
ÁÁÁÁÁ
ÁÁÁÁÁ
CNTL1
ÁÁÁÁÁ
ÁÁÁÁÁ
203
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID16
ÁÁÁÁ
ÁÁÁÁ
24
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO13
ÁÁÁÁÁ
ÁÁÁÁÁ
151
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
54
ÁÁÁÁÁ
DACKA
ÁÁÁÁÁ
98
ÁÁÁÁÁÁ
ID17
ÁÁÁÁ
23
ÁÁÁÁÁÁ
PIO14
ÁÁÁÁÁ
150
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
68
ÁÁÁÁÁ
ÁÁÁÁÁ
DACKB
ÁÁÁÁÁ
ÁÁÁÁÁ
97
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID18
ÁÁÁÁ
ÁÁÁÁ
22
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PIO15
ÁÁÁÁÁ
ÁÁÁÁÁ
149
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
79
ÁÁÁÁÁ
ÁÁÁÁÁ
DACKC 3
ÁÁÁÁÁ
ÁÁÁÁÁ
100
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID19
ÁÁÁÁ
ÁÁÁÁ
21
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
POE
ÁÁÁÁÁ
ÁÁÁÁÁ
144
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
90
ÁÁÁÁÁ
ÁÁÁÁÁ
DACKD 3
ÁÁÁÁÁ
ÁÁÁÁÁ
99
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID20
ÁÁÁÁ
ÁÁÁÁ
20
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PSTROBE
ÁÁÁÁÁ
ÁÁÁÁÁ
142
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
101
ÁÁÁÁÁ
ÁÁÁÁÁ
DREQA
ÁÁÁÁÁ
ÁÁÁÁÁ
185
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID21
ÁÁÁÁ
ÁÁÁÁ
19
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PSYNC 2
ÁÁÁÁÁ
ÁÁÁÁÁ
180
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
106
ÁÁÁÁÁ
ÁÁÁÁÁ
DREQB
ÁÁÁÁÁ
ÁÁÁÁÁ
184
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID22
ÁÁÁÁ
ÁÁÁÁ
18
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
PWE
ÁÁÁÁÁ
ÁÁÁÁÁ
143
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
118
ÁÁÁÁÁ
ÁÁÁÁÁ
DREQC 3
ÁÁÁÁÁ
ÁÁÁÁÁ
153
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID23
ÁÁÁÁ
ÁÁÁÁ
17
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
R/W
ÁÁÁÁÁ
ÁÁÁÁÁ
96
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
128
ÁÁÁÁÁ
ÁÁÁÁÁ
DREQD 3
ÁÁÁÁÁ
ÁÁÁÁÁ
152
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID24
ÁÁÁÁ
ÁÁÁÁ
14
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
RAS0
ÁÁÁÁÁ
ÁÁÁÁÁ
76
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
138
ÁÁÁÁÁ
ÁÁÁÁÁ
DSRA
ÁÁÁÁÁ
ÁÁÁÁÁ
62
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID25
ÁÁÁÁ
ÁÁÁÁ
13
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
RAS1
ÁÁÁÁÁ
ÁÁÁÁÁ
75
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
148
ÁÁÁÁÁ
ÁÁÁÁÁ
DTRA
ÁÁÁÁÁ
ÁÁÁÁÁ
59
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID26
ÁÁÁÁ
ÁÁÁÁ
12
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
RAS2
ÁÁÁÁÁ
ÁÁÁÁÁ
74
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
155
ÁÁÁÁÁ
ÁÁÁÁÁ
GACK
ÁÁÁÁÁ
ÁÁÁÁÁ
85
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID27
ÁÁÁÁ
ÁÁÁÁ
11
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
RAS3
ÁÁÁÁÁ
ÁÁÁÁÁ
73
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
158
ÁÁÁÁÁ
ÁÁÁÁÁ
GND
ÁÁÁÁÁ
ÁÁÁÁÁ
6
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID28
ÁÁÁÁ
ÁÁÁÁ
10
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁÁ
ÁÁÁÁÁ
52
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
170
ÁÁÁÁÁ
ÁÁÁÁÁ
GND
ÁÁÁÁÁ
ÁÁÁÁÁ
15
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID29
ÁÁÁÁ
ÁÁÁÁ
9
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁÁ
ÁÁÁÁÁ
53
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
182
ÁÁÁÁÁ
ÁÁÁÁÁ
GND
ÁÁÁÁÁ
ÁÁÁÁÁ
25
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID30
ÁÁÁÁ
ÁÁÁÁ
8
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁÁ
ÁÁÁÁÁ
56
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
194
ÁÁÁÁÁ
ÁÁÁÁÁ
GND
ÁÁÁÁÁ
ÁÁÁÁÁ
35
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ID31
ÁÁÁÁ
ÁÁÁÁ
7
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁÁ
ÁÁÁÁÁ
103
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁÁ
ÁÁÁÁÁ
206
ÁÁÁÁÁ
ÁÁÁÁÁ
GND
ÁÁÁÁÁ
ÁÁÁÁÁ
45
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
IDP0 1, 3
ÁÁÁÁ
ÁÁÁÁ
50
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁÁ
ÁÁÁÁÁ
104
ÁÁÁÁÁ
ÁÁÁÁÁ
VCLK 2
ÁÁÁÁÁ
ÁÁÁÁÁ
196
ÁÁÁÁÁ
ÁÁÁÁÁ
GND
ÁÁÁÁÁ
ÁÁÁÁÁ
51
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
IDP1 1, 3
ÁÁÁÁ
ÁÁÁÁ
49
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁÁ
ÁÁÁÁÁ
105
ÁÁÁÁÁ
ÁÁÁÁÁ
VDAT 2
ÁÁÁÁÁ
ÁÁÁÁÁ
179
ÁÁÁÁÁ
GND
ÁÁÁÁÁ
55
ÁÁÁÁÁÁ
IDP2 1, 3
ÁÁÁÁ
48
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁÁ
108
ÁÁÁÁÁ
WAIT
ÁÁÁÁÁ
140
ÁÁÁÁÁ
ÁÁÁÁÁ
GND
ÁÁÁÁÁ
ÁÁÁÁÁ
69
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
IDP3 1, 3
ÁÁÁÁ
ÁÁÁÁ
47
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁÁ
ÁÁÁÁÁ
156
ÁÁÁÁÁ
ÁÁÁÁÁ
WARN
ÁÁÁÁÁ
ÁÁÁÁÁ
195
ÁÁÁÁÁ
ÁÁÁÁÁ
GND
ÁÁÁÁÁ
ÁÁÁÁÁ
80
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
INCLK
ÁÁÁÁ
ÁÁÁÁ
4
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Reserved
ÁÁÁÁÁ
ÁÁÁÁÁ
157
ÁÁÁÁÁ
ÁÁÁÁÁ
WE
ÁÁÁÁÁ
ÁÁÁÁÁ
84
Notes:
1. Defined as no-connect on Am29240EH microcontroller. 2. Defined as no-connect on Am29243EH microcontroller.
3. Defined as no-connect on Am29245EH microcontroller.
P R E L I M I N A R Y
18 Am29240 EH Microcontroller Series
Am29240EH MICROCONTROLLER LOGIC SYMBOL
4
2ROMCS3–ROMCS0
STAT2–STAT0
A23–A0
ID31–ID0PSYNC
INTR3–INTR0
RESET
INCLK
TRAP1–TRAP0
3
24
TDO
R/W
32
4
ROMOE
BURST
RSWE
RAS3–RAS0 4
CAS3–CAS0 4
WE
TR/OE
PIACS5–PIACS0 6
PIAOE
PIAWE
TRST
TDI
TCK
TMS
WAIT
WARN
BOOTW
DREQD–DREQA DACKD–DACKA
GACK
GREQ
PIO15–PIO0
PSTROBE
PAUTOFD PBUSY
PACK
POE
PWE
UCLK
RXDB–RXDA TXDB–TXDA
DSRA
DTRA
VCLK
LSYNC
VDAT
16
MEMCLK
2
MEMDRV
TRIST
CNTL1–CNTL0
2
2
TDMA
4
4
Am29240EH Microcontroller
P R E L I M I N A R Y
19
Am29240 EH Microcontroller Series
Am29245EH MICROCONTROLLER LOGIC SYMBOL
4
2ROMCS3–ROMCS0
STAT2–STAT0
A23–A0
ID31–ID0PSYNC
INTR3–INTR0
RESET
INCLK
TRAP1–TRAP0
3
24
TDO
R/W
32
4
ROMOE
BURST
RSWE
RAS3–RAS0 4
CAS3–CAS0 4
WE
TR/OE
PIACS5–PIACS0 6
PIAOE
PIAWE
TRST
TDI
TCK
TMS
WAIT
WARN
BOOTW
DREQB–DREQA DACKB–DACKA
GACK
GREQ
PIO15–PIO0
PSTROBE
PAUTOFD PBUSY
PACK
POE
PWE
UCLK
RXDA TXDA
DSRA
DTRA
VCLK
LSYNC
VDAT
16
MEMCLK
MEMDRV
TRIST
CNTL1–CNTL0
2
TDMA
2
2
Am29245EH Microcontroller
P R E L I M I N A R Y
20 Am29240 EH Microcontroller Series
Am29243EH MICROCONTROLLER LOGIC SYMBOL
4
2ROMCS3–ROMCS0
STAT2–STAT0
A23–A0
ID31–ID0
INTR3–INTR0
RESET
INCLK
TRAP1–TRAP0
3
24
TDO
R/W
32
4
ROMOE
BURST
RSWE
RAS3–RAS0 4
CAS3–CAS0 4
WE
TR/OE
PIACS5–PIACS0 6
PIAOE
PIAWE
TRST
TDI
TCK
TMS
WAIT
WARN
BOOTW
DREQD–DREQA DACKD–DACKA
GACK
GREQ
PIO15–PIO0
PSTROBE
PAUTOFD PBUSY
PACK
POE
PWE
UCLK
RXDB–RXDA TXDB–TXDA
DSRA
DTRA
16
MEMCLK
2
MEMDRV
TRIST
CNTL1–CNTL0
2
2
TDMA IDP3–IDP0
4
4
4
Am29243EH Microcontroller
P R E L I M I N A R Y
21
Am29240 EH Microcontroller Series
ABSOLUTE MAXIMUM RATINGS
Storage Temperature –65°C to +125°C. . . . . . . . . . . .
Voltage on any Pin
with Respect to GND –0.5 V to VCC +2.4. . . . . . . . .
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to absolute maximum rat-
ings for extended periods may affect device reliability.
OPERATING RANGES
Commercial (C) Devices
Case Temperature (TC)0°C to +85°C. . . . . . . . . . . . . .
Supply Voltage (VCC) +3 V to +3.6 V. . . . . . . . . . . . . . .
Operating ranges define those limits between which the func-
tionality of the device is guaranteed.
DC CHARACTERISTICS over COMMERCIAL Operating Ranges
Preliminary
Symbol Parameter Description Test Conditions Min Max Unit
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 2.0 VCC +2.4 V
VILINCLK INCLK Input Low Voltage –0.5 0.8 V
VIHINCLK INCLK Input High Voltage 2.4 5.5 V
VOL Output Low Voltage for
All Outputs except MEMCLK IOL = 3.2 mA 0.5 V
VOH Output High Voltage for
All Outputs except MEMCLK IOH = –400 µA 2.4 V
ILI Input Leakage Current 0.45 V ≤VIN ≤ VCC –0.45 V
Note 1 ±10 or
+10/–200 µA
ILO Output Leakage Current 0.45 V ≤VOUT ≤ VCC –0.45 V ±10 µA
ICCOP Operating Power-Supply Current with
respect to MEMCLK VCC = 3.6 V, Outputs Floating;
Holding RESET active at 25 MHz 8mA/MHz
VOLC MEMCLK Output Low Voltage IOLC = 20 mA 0.6 V
VOHC MEMCLK Output High Voltage IOHC = –20 mA 2.4 V
IOSGND MEMCLK GND Short Circuit Current VCC = 3.3 V 100 mA
IOSVCC MEMCLK VCC Short Circuit Current VCC = 3.3 V 100 mA
Notes:
1. The Low input leakage current for the inputs
CNTL1–CNTL0, INTR3–INTR0
,
TRAP1–TRAP0, DREQD–DREQA, TCK, TDI,
RESET, TRST, TMS, GREQ, WARN, MEMDRV, WAIT,
and
TRIST
is –200
µ
A. These pins have internal pull-up resistors.
CAPACITANCE
Preliminary
Symbol Parameter Description Test Conditions Min Max Unit
CIN Input Capacitance 15 pF
CINCLK INCLK Input Capacitance 15 pF
CMEMCLK MEMCLK Capacitance fC = 10 MHz 20 pF
COUT Output Capacitance 20 pF
CI/O I/O Pin Capacitance 20 pF
Note: Limits guaranteed by characterization.
P R E L I M I N A R Y
22 Am29240 EH Microcontroller Series
SWITCHING CHARACTERISTICS over COMMERCIAL Operating Ranges
Preliminary
16 MHz 20 MHz 25 MHz
No. Parameter Description Test Conditions 1Min Max Min Max Min Max Unit
1 INCLK Period (=0.5T) 30 50 25 50 20 50 ns
2INCLK High Time 10 8 6 ns
3INCLK Low Time 10 8 6 ns
4INCLK Rise Time 0 5 0 5 0 5 ns
5INCLK Fall Time 0 5 0 5 0 5 ns
6MEMCLK Delay from INCLK Note 1C, 3 1 7 1 7 1 7 ns
8MEMCLK High Time Note 1C 0.5T–3 0.5T–3 0.5T–3 ns
9 MEMCLK Low Time Note 1C 0.5T–3 0.5T–3 0.5T–3 ns
10 MEMCLK Rise Time Note 1C 1 4 1 4 1 4 ns
11 MEMCLK Fall Time Note 1C 1 4 1 4 1 4 ns
12a Synchronous Output Valid Delay from MEMCLK Rising Edge
PIO15–PIO0, STAT2–STAT0,
PIACS5–PIACS0, and
RAS3–RAS0
Note 1A 1 13 1 12 1 11 ns
CAS3–CAS0 Rising Edge/
CAS3–CAS0 Falling Edge Notes 1B, 4B 1 17/11 1 15/9 1 13/7 ns
All others Note 1B 1 12 1 11 1 10 ns
12b Synchronous Output Valid Delay from MEMCLK Falling Edge
PIO15–PIO0, STAT2–STAT0,
PIACS5–PIACS0 Note 1A 1 12 1 11 1 10 ns
RAS3–RAS0 Note 1B 1 15 1 14 1 13 ns
CAS3–CAS0 Falling Edge Notes 1B, 4B 111 1 9 1 7 ns
All others Note 1B 1 11 1 10 1 9 ns
13 Synchronous Output Disable
Delay from MEMCLK Rising
Edge
1 12 1 11 1 10 ns
14 Synchronous Input Setup Time to MEMCLK Rising Edge
ID31–ID0 and IDP3–IDP0 for
DRAM access Parity Enabled
Note 4A 18 16 15 ns
ID31–ID0 for DRAM access Parity Disabled
Note 4A 10 8 7 ns
All others 10 8 7 ns
15 Available CAS Access Time
(TCAS–TSetup)Note 4B 25 24 19 ns
16a Synchronous Input Hold Time to
MEMCLK Rising Edge Note 4A 0 0 0 ns
16b Synchronous Input Hold Time to
CAS Rising Edge Note 4B 3 3 3 ns
P R E L I M I N A R Y
23
Am29240 EH Microcontroller Series
SWITCHING CHARACTERISTICS over COMMERCIAL Operating Ranges (continued)
Preliminary
25 MHz20 MHz16 MHz
No. UnitMaxMinMaxMinMaxMinTest Conditions 1
Parameter Description
17 Asynchronous Input Pulse Width
LSYNC and PSYNC Note 5 Note 5 Note 5
All others 4T 4T 4T ns
18 UCLK Period Note 2 30 25 20 ns
VCLK Period Note 2 25 20 15 ns
19 UCLK High Time Note 2 10 8 6 ns
VCLK High Time Note 2 8 6 4 ns
20 UCLK Low Time Note 2 10 8 6 ns
VCLK Low Time Note 2 8 6 4 ns
21 UCLK Rise time Note 2 0 5 0 5 0 5 ns
VCLK Rise time Note 2 0 3 0 3 0 3 ns
22 UCLK Fall Time Note 2 0 5 0 5 0 5 ns
VCLK Fall Time Note 2 0 3 0 3 0 3 ns
23 Synchronous Output Valid Delay
from VCLK Rise and Fall Note 6 1 16 1 14 1 14 ns
24 Input Setup Time to VCLK Rise
and Fall Notes 6, 7 10 9 9 ns
25 Input Hold Time to VCLK Rise
and Fall Notes 6, 7 0 0 0 ns
26 RAS Low Time 50 50 50 ns
27 CAS Low Time 13 13 13 ns
Notes:
1. All outputs driving 80 pF, measured at V
OL
= 1.5 V and V
OH
= 1.5 V using the switching test circuit shown on page 33.
For higher capacitance loads:
A. Add 1 ns output delay per 15 pF loading above 80 pF, up to 150 pF total. The minimum delay from
PIAOE
to
PIACS
x is 0 ns if
thecapacitance loading on
PIACS
x is equal to or higher than the capacitance loading on
PIAOE
.
B. Add 1 ns output delay per 25 pF loading above 80 pF , up to 300 pF total. For 2/1 DRAM timing, in order to meet the setup time
(t
ASR
) from A23–A0 to RAS3–RAS0 for DRAM, the capacitive loading of A23–A0 must not exceed the capacitance loading of
RAS3–RAS0 by more than 150 pF.
C. Add 1 ns of output delay for MEMCLK to drive an external load of 100 pF.
2. VCLK and UCLK can be driven with TTL inputs. UCLK must be tied High if it is unused.
3. Maximum INCLK-to-MEMCLK delay can be decreased by 0.5 ns for each 10 mA increase in I
OL
up to the maximum of 20 mA,
i.e., 6 ns maximum delay at I
OL
= 20 mA.
4. ID31–ID0 and IDP3–IDP0 are sampled on the rising edge of MEMCLK for all non-DRAM accesses, simple DRAM accesses,
and the first access of a DRAM page-mode access. ID31–ID0 and IDP3–IDP0 are sampled on the rising edge of
CAS
x for all
DRAM page-mode accesses, except the first access of a DRAM page-mode access. (See Figures 1–12 on pages 25–32.)
A. Applies to ID31–ID0 and IDP3–IDP0 for simple DRAM accesses and the first access of a DRAM page-mode access.
B. Applies to ID31–ID0 and IDP3–IDP0 for DRAM page-mode accesses, except the first access of a DRAM page-mode access.
When ID31–ID0 and IDP3–IDP0 are sampled on
CAS
x, there is no additional setup time required for ID31–ID0 and
IDP3–IDP0 when the parity is enabled.
5. LSYNC and PSYNC minimum width is two bit-times. A bit-time is one period of the internal video clock, which is determined by
the CLKDIV field in the Video Control Register and VCLK.
6. Active VCLK edge depends on the CLKI bit in the Video Control Register.
7. LSYNC and PSYNC can be treated as synchronous signals by meeting the setup and hold times, though the synchronization
delay still applies.
P R E L I M I N A R Y
24 Am29240 EH Microcontroller Series
SWITCHING WAVEFORMS
16a
14
53
21
25
INCLK
MEMCLK
4
0.8 V
1.5 V
2.0 V
10 98
0.8 V
1.5 V
VCC –0.6 V 11
6
SYNCHRONOUS
OUTPUTS
SYNCHRONOUS
INPUTS
ASYNCHRONOUS
INPUTS
UCLK, VCLK
18
21 2019
0.8 V
1.5 V
2.0 V 22
VCLK-RELATIVE
OUTPUTS
VCLK-RELATIVE
INPUTS 1.5 V
Note: Video Timing may be
relative to VCLK falling edge
if CLK = 1.
13
17
23
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
Note:
During AC testing, all inputs are driven at V
IL
= 0.4 V, V
IH
= 2.4 V.
24
CASx
Note: See Note 4 on page 23.
12a
16b
1.5 V
12b
15
P R E L I M I N A R Y
25
Am29240 EH Microcontroller Series
SWITCHING WAVEFORMS (continued)
A14–A1 Column Address
16a
14
1.5 V 1.5 V
1.5 V
ID31–ID0
IDP3–IDP0
R/W
MEMCLK
WE
TR/OE
RAS3–RAS0
CAS3–CAS0
Note:
The RAS3–RAS0
signals are asserted and deasserted on the falling edge of
MEMCLK
.
Row Address
Figure 1. Simple 3/1 DRAM Read Cycle
A14–A1
ID31–ID0
IDP3–IDP0
MEMCLK
R/W
WE
TR/OE
RAS3–RAS0
CAS3–CAS0
Row Address Column Address
Data
Figure 2. Simple 3/1 DRAM Write Cycle
P R E L I M I N A R Y
26 Am29240 EH Microcontroller Series
SWITCHING WAVEFORMS (continued)
A14–A1
1.5 V
Column Address +2/4 +4/8 +6/12
MEMCLK
R/W
WE
TR/OE
RAS3–RAS0
CAS3–CAS0
Row Address
ID31–ID0
IDP3–IDP0
Note:
The RAS3–RAS0 signals are
asserted and deasserted on the falling edge of
MEMCLK
.
1.5 V
1.5 V 1.5 V
16b
15 + T/2 15 16b 15 16b 15
1.5 V 1.5 V 1.5 V 1.5 V 1.5 V
1.5 V
16b
1.5 V
Figure 3. 3/1 DRAM Page-Mode Read
Data
ID31–ID0
IDP3–IDP0
MEMCLK
WE
TR/OE
R/W
RAS3–RAS0
CAS3–CAS0
Row Address Column Address +2/4 +4/8 +6/12
A14–A1
Data Data Data
Figure 4. 3/1 DRAM Page-Mode Write
P R E L I M I N A R Y
27
Am29240 EH Microcontroller Series
SWITCHING WAVEFORMS (continued)
Row
Addr
MEMCLK
A14–A1
RAS3–RAS0
ID31–ID0
IDP3–IDP0
WE
Column Address
CAS3–CAS0
R/W
TR/OE
1.5 V
16a
14
1.5 V 1.5 V
Figure 5. Simple 2/1 DRAM Read Cycle
Row
Addr
Data
Column Address
MEMCLK
A14–A1
ID31–ID0
IDP3–IDP0
WE
CAS3–CAS0
R/W
TR/OE
RAS3–RAS0
Figure 6. Simple 2/1 DRAM Write Cycle
P R E L I M I N A R Y
28 Am29240 EH Microcontroller Series
SWITCHING WAVEFORMS (continued)
Row
Addr Column Address +2/4 +4/8 +6/12
MEMCLK
A14–A1
RAS3–RAS0
ID31–ID0
IPD3–IDP0
WE
CAS3–CAS0
R/W
TR/OE
1.5 V
1.5 V
1.5 V 1.5 V
16b
15 + T/2 15 16b 15 16b 15
1.5 V 1.5 V 1.5 V 1.5 V 1.5 V
Note: May be repeated up to 1-Kbyte address boundary.
1.5 V
16b
Figure 7. 2/1 DRAM Page-Mode Read Cycle
Note: May be repeated up to 1-Kbyte address boundary.
Data Data
Column Address +2/4 +4/8 +6/12
Data Data
Row
Addr
MEMCLK
A14–A1
RAS3–RAS0
ID31–ID0
IDP3–IDP0
WE
CAS3–CAS0
R/W
TR/OE
Figure 8. 2/1 DRAM Page-Mode Write Cycle
P R E L I M I N A R Y
29
Am29240 EH Microcontroller Series
SWITCHING WAVEFORMS (continued)
Row Addr Col
Addr Col
Addr Col
Addr
MEMCLK
A14–A1
RASx
ID31–ID0
WE
CASx
R/W
TR/OE
DREQx
DACKx
PIACSx
PIAOE
PIAWE
Row Addr
Note: May be repeated up to 1-Kbyte address
boundary.
Data Data Data
Figure 9. Fly-By DMA Reads (Read Peripheral, Write DRAM)—3/1 DRAM Accesses
P R E L I M I N A R Y
30 Am29240 EH Microcontroller Series
SWITCHING WAVEFORMS (continued)
Row Addr
Data Data Data
Col
Addr Col
Addr Col
Addr
MEMCLK
A14–A1
RASx
ID31–ID0
WE
CASx
R/W
TR/OE
DREQx
DACKx
PIACSx
PIAOE
PIAWE
Row Addr
Note: May be repeated up to 1-Kbyte address
boundary.
Figure 10. Fly-By DMA Writes (Read DRAM, Write Peripheral)—3/1 DRAM Accesses
P R E L I M I N A R Y
31
Am29240 EH Microcontroller Series
SWITCHING WAVEFORMS (continued)
Row
Addr
MEMCLK
A14–A1
RASx
ID31–ID0
WE
CASx
R/W
TR/OE
Data
DREQx
DACKx
PIACSx
PIAOE
PIAWE
Data
Col
Addr Col
Addr Row
Addr Col
Addr
Data
Note: May be repeated up to 1-Kbyte address boundary.
Figure 11. Fly-By DMA Reads (Read Peripheral, Write DRAM)—2/1 DRAM Accesses
P R E L I M I N A R Y
32 Am29240 EH Microcontroller Series
SWITCHING WAVEFORMS (continued)
Row
Addr
Data Data Data
Col
Addr Col
Addr Row
Addr Col
Addr
MEMCLK
A14–A1
RASx
ID31–ID0
WE
CASx
R/W
TR/OE
DREQx
DACKx
PIACSx
PIAOE
PIAWE
Note: May be repeated up to 1-Kbyte address boundary.
Figure 12. Fly-By DMA Writes (Read DRAM, Write Peripheral)—2/1 DRAM Accesses
P R E L I M I N A R Y
33
Am29240 EH Microcontroller Series
SWITCHING TEST CIRCUIT
V
Am29240EH Microcontroller
VL
IOL = 3.2 mA *
VREF = 1.5 V
IOH = 400 µA *
CL
VH
Pin Under Test
Note:
*All outputs except MEMCLK. MEMCLK is tested with I
OL
= 20 mA and I
OH
= –20mA.
THERMAL CHARACTERISTICS
The Am29240EH microcontroller series is specified for
operation with case temperature ranges for a commercial
temperature device. Case temperature is measured at
the top center of the PQFP package as shown in Figure
13.
ÉÉÉÉ
θJA θCA
θJC
TC
θJA =θJC +θCA
Figure 13. Thermal Resistance — °C/Watt
The various temperatures and thermal resistances can
be determined using the equations shown in Figure 14
along with information given in Table 2. (The variable
P
is power in watts.)
θJA = θJC + θCA
P=I
CCOP ⋅ freq ⋅ VCC
TJ=T
C+P⋅θ
JC
TJ=T
A+P⋅θ
JA
TC=T
J–P⋅θ
JC
TC=T
A+P⋅θ
CA
TA=T
J–P⋅θ
JA
TA=T
C–P⋅θ
CA
Figure 14. Thermal Characteristics Equations
Table 2. Thermal Characteristics (°C/Watt) Surface Mounted
Parameter °C/Watt
θJA Junction-to-Ambient 38
θJC Junction-to-Case 8
θCA Case-to-Ambient 30
P R E L I M I N A R Y
34 Am29240 EH Microcontroller Series
PHYSICAL DIMENSIONS
PQR 208, Trimmed and Formed
Plastic Quad Flat Pack
Notes:
All measurements are in millimeters unless otherwise noted.
Not to scale. For reference only.
30.40
30.80
27.90
28.10
25.50
Ref. Pin 156
Pin 208
Pin 52
Pin 104
Pin 1 I.D.
27.90
28.10
See Detail X
Seating
Plane
0.50
Basic
0.25
Min.
3.20
3.60 3.95
Max.
S
S
–A–
–D–
–B–
–A–
–C–
Top View
Side View
25.50
Ref.
30.40
30.80
P R E L I M I N A R Y
35
Am29240 EH Microcontroller Series
PQR 208 (continued)
0.20 Min. Flat Shoulder
7° Typ.
0° Min.
0.30±0.05 R
Gage
Plane 0.25
0.50
0.75
0°–7°
7° Typ.
Detail X
0.18
0.30
0.13
0.20
3.95
Max
Section S–S
0.13
0.20
0.18
0.30
Notes:
All measurements are in millimeters unless otherwise noted.
Not to scale. For reference only.
P R E L I M I N A R Y
36 Am29240 EH Microcontroller Series
PHYSICAL DIMENSIONS (continued)
Solder Land Recommendations—208-Lead PQFP
29.80 Ref.
0.50 Typ.
0.30 Typ.
1.80 Typ.
25.50 Typ.
31.60 Ref.
28.00 Typ.
Notes:
All measurements are in millimeters unless otherwise noted.
Not to scale. For reference only.
Trademarks
Copyright 1997 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, Am29000, MiniMON29K, and Fusion29K are registered trademarks; 29K, AMD Facts-On-Demand, Am29005, Am29030,
Am29035, Am29040, Am29050, Am29200, Am29202, Am29205, Am29240, Am29243, Am29245, and Traceable Cache are trademarks of Ad-
vanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
