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CY62148GN MoBL®
4-Mbit (512K × 8) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-95418 Rev. *D Revised December 21, 2017
4-Mbit (512K × 8) Static RAM
Features
■Very high speed: 45 ns
■Wide voltage range: 2.2 V to 3.6 V, 4.5 V to 5.5 V
■Ultra low standby power
❐Typical standby current: 3.5 µA
❐Maximum standby current: 8.7 µA
■Easy memory expansion with CE and OE features
■Automatic power-down when deselected
■Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■Available in Pb-free 32-pin thin small outline package (TSOP) II
and 32-pin small-outline integrated circuit (SOIC) packages
Functional Description
The CY62148GN is a high-performance CMOS static RAM
organized as 512K words by 8-bits. This device features
advanced circuit design to provide ultra low standby current. This
is ideal for providing More Battery Life™ (MoBL) in portable
applications. The device also has an automatic power-down
feature that significantly reduces power consumption when
addresses are not toggling. Placing the device in standby mode
reduces power consumption by more than 99% when deselected
(CE HIGH). The eight input and output pins (I/O0 through I/O7)
are placed in a high-impedance state when the device is
deselected (CE HIGH), Outputs are disabled (OE HIGH), or
during an active Write operation (CE LOW and WE LOW).
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)
is then written into the location specified on the address pins (A0
through A18).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under
these conditions, the contents of the memory location specified
by the address pins appear on the I/O pins.
For a complete list of related documentation, click here.
A0IO0
IO7
IO1
IO2
IO3
IO4
IO5
IO6
A1
A2
A3
A4
A5
A6
A7
A8
A9
SENSE AMPS
POWER
DOWN
CE
WE
OE
A13
A14
A15
A16
A17
ROW DECODER
COLUMN DECODER
512K x 8
ARRAY
INPUT BUFFER
A10
A11
A12
A18
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Logic Block Diagram
Document Number: 001-95418 Rev. *D Page 2 of 15
CY62148GN MoBL®
Contents
Pin Configurations ........................................................... 3
Product Portfolio .............................................................. 3
Maximum Ratings ............................................................. 4
Operating Range ...............................................................4
Electrical Characteristics .................................................4
Capacitance ......................................................................5
Thermal Resistance .......................................................... 5
AC Test Loads and Waveforms ....................................... 5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................ 6
Switching Characteristics ................................................7
Switching Waveforms ...................................................... 8
Truth Table ...................................................................... 10
Ordering Information ...................................................... 11
Ordering Code Definitions ......................................... 11
Package Diagrams .......................................................... 12
Acronyms ........................................................................ 13
Document Conventions ................................................. 13
Units of Measure ....................................................... 13
Document History Page ................................................. 14
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC® Solutions ...................................................... 15
Cypress Developer Community ................................. 15
Technical Support ..................................................... 15
Document Number: 001-95418 Rev. *D Page 3 of 15
CY62148GN MoBL®
Pin Configurations
Figure 1. 32-pin SOIC/TSOP II pinout
1
2
3
4
5
6
7
8
9
10
11
14
31
32
12
13
16
15
29
30
21
22
19
20
27
28
25
26
17
18
23
24
Top View
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
VSS
VCC
A
18
WE
OE
CE
Product Portfolio
Product Range VCC Range (V) Speed
(ns)
Power Dissipation
Operating ICC (mA) Standby ISB2 (µA)
f = 1 MHz f = fmax
Typ[1] Max Typ[1] Max Typ[1] Max
CY62148GN30 Industrial 2.2 V–3.6 V 45 – 6 – 20 3.5 8.7
CY62148GN 4.5 V–5.5 V
Note
1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
Document Number: 001-95418 Rev. *D Page 4 of 15
CY62148GN MoBL®
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Storage temperature ............................... –65 °C to + 150 °C
Ambient temperature
with power applied .................................. –55 °C to + 125 °C
Supply voltage to ground potential ......–0.5 V to Vcc + 0.5 V
DC voltage applied to outputs
in high Z state[2, 3] ................................–0.5 V to Vcc + 0.5 V
DC input voltage[2, 3] ............................–0.5 V to Vcc + 0.5 V
Output current into outputs (LOW) ............................. 20 mA
Static discharge voltage
(per MIL-STD-883, Method 3015) .......................... > 2001 V
Latch-up current .................................................... > 140 mA
Operating Range
Device Range Ambient
Temperature VCC[4]
CY62148GN Industrial –40 °C to +85 °C 2.2 V to 3.6 V,
4.5 V to 5.5 V
Electrical Characteristics
Over the operating range
Parameter Description Test Conditions 45 ns Unit
Min Typ[5] Max
VOH Output HIGH
voltage
2.2 V to 2.7 V VCC = Min, IOH = –0.1 mA 2 – – V
2.7 V to 3.6 V VCC = Min, IOH = –1.0 mA 2.4 – –
4.5 V to 5.5 V VCC = Min, IOH = –1.0 mA 2.4 – –
4.5 V to 5.5 V VCC = Min, IOH = –0.1 mA VCC – 0.5[6] ––
VOL Output LOW
voltage
2.2 V to 2.7 V VCC = Min, IOL = 0.1 mA – – 0.4 V
2.7 V to 3.6 V VCC = Min, IOL = 2.1 mA – – 0.4
4.5 V to 5.5 V VCC = Min, IOL = 2.1 mA – – 0.4
VIH Input HIGH
voltage
2.2 V to 2.7 V – 1.8 – VCC + 0.3[3] V
2.7 V to 3.6 V – 2 – VCC + 0.3[3]
4.5 V to 5.5 V – 2.2 – VCC + 0.5
VIL Input LOW
voltage
2.2 V to 2.7 V – –0.3[2] –0.6V
2.7 V to 3.6 V – –0.3[2] –0.8
4.5 V to 5.5 V – –0.5 – 0.8
IIX Input leakage current GND < VI < VCC –1 – +1 µA
IOZ Output leakage current GND < VO < VCC, output disabled –1 – +1 µA
ICC VCC operating supply current f = fmax = 1/tRC VCC = VCC(max),
IOUT = 0 mA
CMOS levels
––20mA
f = 1 MHz ––6
ISB1[7] Automatic CE power-down
current – CMOS inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = fmax (address and data only),
f = 0 (OE and WE) VCC = VCC(max)
–3.58.7µA
ISB2[7] Automatic CE power-down
current – CMOS inputs
CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V,
f = 0, VCC = VCC(max)
–3.58.7µA
Notes
2. VIL(min) = –2.0 V for pulse durations less than 20 ns.
3. VIH(max) = VCC + 0.75 V for pulse durations less than 20 ns.
4. Full device AC operation assumes a minimum of 100 µs ramp time from 0 to VCC(min) and 200 µs wait time after VCC stabilization.
5. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
6. This parameter is guaranteed by design and not tested.
7. Chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
Document Number: 001-95418 Rev. *D Page 5 of 15
CY62148GN MoBL®
Capacitance
Parameter [8] Description Test Conditions Max Unit
CIN Input capacitance TA = 25 °C, f = 1 MHz, VCC = VCC(Typ) 10 pF
COUT Output capacitance 10 pF
Thermal Resistance
Parameter [8] Description Test Conditions 32-pin SOIC
Package
32-pin TSOP II
Package Unit
JA Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch,
four-layer printed circuit board
51.79 79.03 C/W
JC Thermal resistance
(junction to case)
25.12 17.44 C/W
AC Test Loads and Waveforms
Figure 2. AC Test Loads and Waveforms[9]
3.0 V
VCC
OUTPUT
R2
30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
Rise Time = 1 V/ns Fall Time = 1 V/ns
OUTPUT V
Equivalent to: THEVENIN EQUIVALENT
ALL INPUT PULSES
RTH
R1
Parameter[8] 2.5 V 3.0 V 5.0 V Unit
R1 16667 1103 1800
R2 15385 1554 990
RTH 8000 645 639
VTH 1.20 1.75 1.77 V
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full-device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
Document Number: 001-95418 Rev. *D Page 6 of 15
CY62148GN MoBL®
Data Retention Characteristics
Over the operating range
Parameter Description Conditions Min Typ[10] Max Unit
VDR VCC for data retention 1 – – V
ICCDR[11, 12] Data retention current VCC = 1.2V, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
– – 13 µA
tCDR[13] Chip deselect to data retention
time
0––ns
tR[13, 14] Operation recovery time 45 – – ns
Data Retention Waveform
Figure 3. Data Retention Waveform
VCC(min)
VCC(min)
tCDR
VDR >1.0 V
DATA RETENTION MODE
tR
VCC
CE
Notes
10. Typical values are included for reference and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25 °C.
11. Chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
12. ICCDR is guaranteed only after device is first powered up to VCC(min) and then brought down to VDR.
13. These parameters are guaranteed by design.
14. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs.
Document Number: 001-95418 Rev. *D Page 7 of 15
CY62148GN MoBL®
Switching Characteristics
Over the operating range
Parameter [15] Description 45 ns Unit
Min Max
Read Cycle
tRC Read cycle time 45 –ns
tAA Address to data valid –45 ns
tOHA Data hold from address change 10 –ns
tACE CE LOW to data valid –45 ns
tDOE OE LOW to data valid –22 ns
tLZOE OE LOW to low Z[16] 5 – ns
tHZOE OE HIGH to high Z[16, 17] –18 ns
tLZCE CE LOW to low Z[16] 10 –ns
tHZCE CE HIGH to high Z[16, 17] –18 ns
tPU CE LOW to power-up 0 – ns
tPD CE HIGH to power-down –45 ns
Write Cycle[18, 19]
tWC Write cycle time 45 –ns
tSCE CE LOW to write end 35 –ns
tAW Address setup to write end 35 –ns
tHA Address hold from write end 0 – ns
tSA Address setup to write start 0 – ns
tPWE WE pulse width 35 –ns
tSD Data setup to write end 25 –ns
tHD Data hold from write end 0 – ns
tHZWE WE LOW to high Z[16, 17] –18 ns
tLZWE WE HIGH to low Z[16] 10 –ns
Notes
15. Test conditions for all parameters other than tri-state parameters assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of
0 to 3 V, and output loading of the specified IOL/IOH as shown in the Figure 2 on page 5.
16. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
17. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state.
18. The internal wre.ite time of the memory is defined by the overlap of WE, CE = VIL. All signals must be ACTIVE to initiate a write and any of these signals can terminate
a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write.
19. The minimum write cycle pulse width for Write Cycle No. 3 (WE controlled, OE LOW) should be equal to the sum of tSD and tHZWE.
Document Number: 001-95418 Rev. *D Page 8 of 15
CY62148GN MoBL®
Switching Waveforms
Figure 4. Read Cycle No. 1 (Address Transition Controlled) [20, 21]
Figure 5. Read Cycle No. 2 (OE Controlled) [21, 22]
Figure 6. Write Cycle No. 1 (WE Controlled, OE HIGH During Write) [23, 24]
PREVIOUS DATA VALID DATA VALID
RC
tAA
tOHA
tRC
ADDRESS
DATA OUT
50%
50%
DATA VALID
tRC
tACE
tDOE
tLZOE
tLZCE
tPU
HIGH IMPEDANCE
tHZOE
tHZCE
tPD
IMPEDANCE
ICC
ISB
HIGH
ADDRESS
CE
DATA OUT
VCC
SUPPLY
CURRENT
OE
DATA VALID
tHD
tSD
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZOE
ADDRESS
CE
WE
DATA I/O
OE
NOTE
25
Notes
20. Device is continuously selected. OE, CE = VIL.
21. WE is HIGH for read cycles.
22. Address valid before or similar to CE transition LOW.
23. Data I/O is high impedance if OE = VIH.
24. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
25. During this period, the I/Os are in output state and input signals must not be applied.
Document Number: 001-95418 Rev. *D Page 9 of 15
CY62148GN MoBL®
Figure 7. Write Cycle No. 2 (CE Controlled) [26, 27]
Figure 8. Write Cycle No. 3 (WE Controlled, OE LOW) [27, 28]
Switching Waveforms (continued)
tWC
DATA VALID
tAW
tSA
tPWE
tHA
tHD
tSD
tSCE
ADDRESS
CE
DATA I/O
WE
DATA VALID
tHD
tSD
tLZWE
tPWE
tSA
tHA
tAW
tSCE
tWC
tHZWE
ADDRESS
CE
WE
DATA I/O
NOTE
29
Notes
26. Data I/O is high impedance if OE = VIH.
27. If CE goes HIGH simultaneously with WE HIGH, the output remains in high impedance state.
28. The minimum write cycle pulse width should be equal to the sum of tSD and tHZWE.
29. During this period, the I/Os are in output state and input signals must not be applied.
Document Number: 001-95418 Rev. *D Page 10 of 15
CY62148GN MoBL®
Truth Table
CE WE OE I/O Mode Power
H [30] X X High Z Deselect/power-down Standby (ISB)
L H L Data out Read Active (ICC)
L L X Data in Write Active (ICC)
L H H High Z Selected, outputs disabled Active (ICC)
Note
30. Chip enable (CE) must be HIGH at CMOS level to meet the ISB2 / ICCDR spec. Other inputs can be left floating.
Document Number: 001-95418 Rev. *D Page 11 of 15
CY62148GN MoBL®
Ordering Information
Ordering Code Definitions
Table 1. Key features and Ordering Information
Speed
(ns) Voltage Range (V) Ordering Code Package
Diagram Package Type Operating
Range
45 2.2 V–3.6 V CY62148GN30-45ZSXI 51-85095 32-pin TSOP II (Pb-free) Industrial
CY62148GN30-45ZSXIT 51-85095 32-pin TSOP II (Pb-free), Tape and Reel
CY62148GN30-45SXI 51-85081 32-pin SOIC (Pb-free)
32-pin SOIC (Pb-free), Tape and ReelCY62148GN30-45SXIT 51-85081
4.5 V–5.5 V CY62148GN-45ZSXI 51-85095 32-pin TSOP II (Pb-free)
CY62148GN-45ZSXIT 51-85095 32-pin TSOP II (Pb-free), Tape and Reel
CY62148GN-45SXI 51-85081 32-pin SOIC (Pb-free)
CY62148GN-45SXIT 51-85081 32-pin SOIC (Pb-free), Tape and Reel
X = blank or T
blank = Bulk; T = Tape and Reel
Temperature Range: I = Industrial
Pb-free
Package Type: XX = ZS or S
ZS = 32-pin TSOP II
S = 32-pin SOIC
Speed Grade: XX = 45 ns
Voltage Range: 30 = 3 V typ; no character = 5 V typ
Process Technology: GN = 65 nm
Bus width: 8 = × 8
Density: 4 = 4-Mbit
Family Code: 621 = MoBL SRAM family
Company ID: CY = Cypress
CY XX XX
621 48GN XI
-XX X
Document Number: 001-95418 Rev. *D Page 12 of 15
CY62148GN MoBL®
Package Diagrams
Figure 9. 32-pin TSOP II (20.95 × 11.76 × 1.0 mm) ZS32 Package Outline, 51-85095
Figure 10. 32-pin SOIC (450 Mils) S32.45/SZ32.45 Package Outline, 51-85081
51-85095 *D
Document Number: 001-95418 Rev. *D Page 13 of 15
CY62148GN MoBL®
Acronyms Document Conventions
Units of Measure
Table 2. Acronyms Used in this Document
Acronym Description
CE chip enable
CMOS complementary metal oxide semiconductor
I/O input/output
OE output enable
MoBL More Battery Life
SOIC small outline integrated circuit
SRAM static random access memory
TSOP thin small outline package
WE write enable
Table 3. Units of Measure
Symbol Unit of Measure
°C Degrees Celsius
MHz megahertz
µA microamperes
µs microseconds
mA milliamperes
ns nanoseconds
ohms
%percent
pF picofarads
Vvolts
Wwatts
Document Number: 001-95418 Rev. *D Page 14 of 15
CY62148GN MoBL®
Document History Page
Document Title: CY62148GN MoBL®, 4-Mbit (512K × 8) Static RAM
Document Number: 001-95418
Revision ECN Orig. of
Change
Submission
Date
Description of Change
** 5056496 NILE 12/29/2015 New data sheet.
*A 5092456 NILE 01/19/2016 Added “2.2 V to 3.6 V” range related information in all instances across the
document.
Updated Ordering Information:
Updated part numbers.
*B 5422041 NILE 09/09/2016 Updated Electrical Characteristics:
Changed minimum value of VOH parameter corresponding to “2.7 V to 3.6 V”
from 2.2 V to 2.4 V.
Changed minimum value of VIH parameter corresponding to “2.2 V to 2.7 V”
from 2.0 V to 1.8 V.
Updated Ordering Information:
Updated part numbers.
Updated Disclaimer.
Updated to new template.
*C 5546908 NILE 12/08/2016 Updated Ordering Information:
No change in part numbers.
Removed Disclaimer (text referencing to contact sales).
Completing Sunset Review.
*D 6002325 AESATMP9 12/21/2017 Updated logo and copyright.
Document Number: 001-95418 Rev. *D Revised December 21, 2017 Page 15 of 15
© Cypress Semiconductor Corporation, 2015-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress does not assume any liability arising out of any security breach,
such as unauthorized access to or use of a Cypress product.In addition, the products described in these materials may contain design defects or errors known as errata which may cause the product
to deviate from published specifications. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any
liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming
code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this
information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons
systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances
management, or other uses where the failure of the device or system could cause personal injury, death, or property damage (“Unintended Uses”). A critical component is any component of a device
or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you
shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from
and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
CY62148GN MoBL®
Sales, Solutions, and Legal Information
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closest to you, visit us at Cypress Locations.
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